1 //===-- AlphaISelDAGToDAG.cpp - Alpha pattern matching inst selector ------===//
3 // The LLVM Compiler Infrastructure
5 // This file was developed by Andrew Lenharth and is distributed under
6 // the University of Illinois Open Source License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines a pattern matching instruction selector for Alpha,
11 // converting from a legalized dag to a Alpha dag.
13 //===----------------------------------------------------------------------===//
16 #include "AlphaTargetMachine.h"
17 #include "AlphaISelLowering.h"
18 #include "llvm/CodeGen/MachineInstrBuilder.h"
19 #include "llvm/CodeGen/MachineFrameInfo.h"
20 #include "llvm/CodeGen/MachineFunction.h"
21 #include "llvm/CodeGen/SSARegMap.h"
22 #include "llvm/CodeGen/SelectionDAG.h"
23 #include "llvm/CodeGen/SelectionDAGISel.h"
24 #include "llvm/Target/TargetOptions.h"
25 #include "llvm/ADT/Statistic.h"
26 #include "llvm/Constants.h"
27 #include "llvm/GlobalValue.h"
28 #include "llvm/Support/Debug.h"
29 #include "llvm/Support/MathExtras.h"
35 //===--------------------------------------------------------------------===//
36 /// AlphaDAGToDAGISel - Alpha specific code to select Alpha machine
37 /// instructions for SelectionDAG operations.
39 class AlphaDAGToDAGISel : public SelectionDAGISel {
40 AlphaTargetLowering AlphaLowering;
42 static const int IMM_LOW = -32768;
43 static const int IMM_HIGH = 32767;
44 static const int IMM_MULT = 65536;
47 AlphaDAGToDAGISel(TargetMachine &TM)
48 : SelectionDAGISel(AlphaLowering), AlphaLowering(TM) {}
50 /// getI64Imm - Return a target constant with the specified value, of type
52 inline SDOperand getI64Imm(int64_t Imm) {
53 return CurDAG->getTargetConstant(Imm, MVT::i64);
56 // Select - Convert the specified operand from a target-independent to a
57 // target-specific node if it hasn't already been changed.
58 SDOperand Select(SDOperand Op);
60 /// InstructionSelectBasicBlock - This callback is invoked by
61 /// SelectionDAGISel when it has created a SelectionDAG for us to codegen.
62 virtual void InstructionSelectBasicBlock(SelectionDAG &DAG);
64 virtual const char *getPassName() const {
65 return "Alpha DAG->DAG Pattern Instruction Selection";
68 // Include the pieces autogenerated from the target description.
69 #include "AlphaGenDAGISel.inc"
72 SDOperand getGlobalBaseReg();
73 SDOperand getRASaveReg();
74 SDOperand SelectCALL(SDOperand Op);
79 /// getGlobalBaseReg - Output the instructions required to put the
80 /// GOT address into a register.
82 SDOperand AlphaDAGToDAGISel::getGlobalBaseReg() {
83 return CurDAG->getCopyFromReg(CurDAG->getEntryNode(),
84 AlphaLowering.getVRegGP(),
88 /// getRASaveReg - Grab the return address
90 SDOperand AlphaDAGToDAGISel::getRASaveReg() {
91 return CurDAG->getCopyFromReg(CurDAG->getEntryNode(),
92 AlphaLowering.getVRegRA(),
96 /// InstructionSelectBasicBlock - This callback is invoked by
97 /// SelectionDAGISel when it has created a SelectionDAG for us to codegen.
98 void AlphaDAGToDAGISel::InstructionSelectBasicBlock(SelectionDAG &DAG) {
101 // Select target instructions for the DAG.
102 DAG.setRoot(Select(DAG.getRoot()));
104 DAG.RemoveDeadNodes();
106 // Emit machine code to BB.
107 ScheduleAndEmitDAG(DAG);
110 // Select - Convert the specified operand from a target-independent to a
111 // target-specific node if it hasn't already been changed.
112 SDOperand AlphaDAGToDAGISel::Select(SDOperand Op) {
114 if (N->getOpcode() >= ISD::BUILTIN_OP_END &&
115 N->getOpcode() < AlphaISD::FIRST_NUMBER)
116 return Op; // Already selected.
118 // If this has already been converted, use it.
119 std::map<SDOperand, SDOperand>::iterator CGMI = CodeGenMap.find(Op);
120 if (CGMI != CodeGenMap.end()) return CGMI->second;
122 switch (N->getOpcode()) {
125 case ISD::CALL: return SelectCALL(Op);
127 case ISD::DYNAMIC_STACKALLOC: {
128 if (!isa<ConstantSDNode>(N->getOperand(2)) ||
129 cast<ConstantSDNode>(N->getOperand(2))->getValue() != 0) {
130 std::cerr << "Cannot allocate stack object with greater alignment than"
131 << " the stack alignment yet!";
135 SDOperand Chain = Select(N->getOperand(0));
136 SDOperand Amt = Select(N->getOperand(1));
137 SDOperand Reg = CurDAG->getRegister(Alpha::R30, MVT::i64);
138 SDOperand Val = CurDAG->getCopyFromReg(Chain, Alpha::R30, MVT::i64);
139 Chain = Val.getValue(1);
141 // Subtract the amount (guaranteed to be a multiple of the stack alignment)
142 // from the stack pointer, giving us the result pointer.
143 SDOperand Result = CurDAG->getTargetNode(Alpha::SUBQ, MVT::i64, Val, Amt);
145 // Copy this result back into R30.
146 Chain = CurDAG->getNode(ISD::CopyToReg, MVT::Other, Chain, Reg, Result);
148 // Copy this result back out of R30 to make sure we're not using the stack
149 // space without decrementing the stack pointer.
150 Result = CurDAG->getCopyFromReg(Chain, Alpha::R30, MVT::i64);
152 // Finally, replace the DYNAMIC_STACKALLOC with the copyfromreg.
153 CodeGenMap[Op.getValue(0)] = Result;
154 CodeGenMap[Op.getValue(1)] = Result.getValue(1);
155 return SDOperand(Result.Val, Op.ResNo);
158 SDOperand Chain = Select(N->getOperand(0));
159 SDOperand CC = Select(N->getOperand(1));
160 MachineBasicBlock *Dest =
161 cast<BasicBlockSDNode>(N->getOperand(2))->getBasicBlock();
162 return CurDAG->SelectNodeTo(N, Alpha::BNE, MVT::Other, CC,
163 CurDAG->getBasicBlock(Dest), Chain);
168 case ISD::SEXTLOAD: {
169 SDOperand Chain = Select(N->getOperand(0));
170 SDOperand Address = Select(N->getOperand(1));
171 unsigned opcode = N->getOpcode();
172 unsigned Opc = Alpha::WTF;
173 if (opcode == ISD::LOAD)
174 switch (N->getValueType(0)) {
175 default: N->dump(); assert(0 && "Bad load!");
176 case MVT::i64: Opc = Alpha::LDQ; break;
177 case MVT::f64: Opc = Alpha::LDT; break;
178 case MVT::f32: Opc = Alpha::LDS; break;
181 switch (cast<VTSDNode>(N->getOperand(3))->getVT()) {
182 default: N->dump(); assert(0 && "Bad sign extend!");
183 case MVT::i32: Opc = Alpha::LDL;
184 assert(opcode != ISD::ZEXTLOAD && "Not sext"); break;
185 case MVT::i16: Opc = Alpha::LDWU;
186 assert(opcode != ISD::SEXTLOAD && "Not zext"); break;
187 case MVT::i1: //FIXME: Treat i1 as i8 since there are problems otherwise
188 case MVT::i8: Opc = Alpha::LDBU;
189 assert(opcode != ISD::SEXTLOAD && "Not zext"); break;
192 return CurDAG->SelectNodeTo(N, Opc, N->getValueType(0), MVT::Other,
193 getI64Imm(0), Address,
194 Chain).getValue(Op.ResNo);
197 case ISD::TRUNCSTORE: {
198 SDOperand Chain = Select(N->getOperand(0));
199 SDOperand Value = Select(N->getOperand(1));
200 SDOperand Address = Select(N->getOperand(2));
202 unsigned Opc = Alpha::WTF;
204 if (N->getOpcode() == ISD::STORE) {
205 switch (N->getOperand(1).getValueType()) {
206 case MVT::i64: Opc = Alpha::STQ; break;
207 case MVT::f64: Opc = Alpha::STT; break;
208 case MVT::f32: Opc = Alpha::STS; break;
209 default: assert(0 && "Bad store!");
211 } else { //TRUNCSTORE
212 switch (cast<VTSDNode>(N->getOperand(4))->getVT()) {
213 case MVT::i32: Opc = Alpha::STL; break;
214 case MVT::i16: Opc = Alpha::STW; break;
215 case MVT::i8: Opc = Alpha::STB; break;
216 default: assert(0 && "Bad truncstore!");
219 return CurDAG->SelectNodeTo(N, Opc, MVT::Other, Value, getI64Imm(0),
224 return CurDAG->SelectNodeTo(N, Alpha::BR_DAG, MVT::Other, N->getOperand(1),
225 Select(N->getOperand(0)));
227 case ISD::FrameIndex: {
228 int FI = cast<FrameIndexSDNode>(N)->getIndex();
229 return CurDAG->SelectNodeTo(N, Alpha::LDA, MVT::i64,
230 CurDAG->getTargetFrameIndex(FI, MVT::i32),
233 case ISD::ConstantPool: {
234 Constant *C = cast<ConstantPoolSDNode>(N)->get();
235 SDOperand Tmp, CPI = CurDAG->getTargetConstantPool(C, MVT::i64);
236 Tmp = CurDAG->getTargetNode(Alpha::LDAHr, MVT::i64, CPI, getGlobalBaseReg());
237 return CurDAG->SelectNodeTo(N, Alpha::LDAr, MVT::i64, CPI, Tmp);
239 case ISD::GlobalAddress: {
240 GlobalValue *GV = cast<GlobalAddressSDNode>(N)->getGlobal();
241 SDOperand GA = CurDAG->getTargetGlobalAddress(GV, MVT::i64);
242 return CurDAG->SelectNodeTo(N, Alpha::LDQl, MVT::i64, GA,
245 case ISD::ExternalSymbol:
246 return CurDAG->SelectNodeTo(N, Alpha::LDQl, MVT::i64,
247 CurDAG->getTargetExternalSymbol(cast<ExternalSymbolSDNode>(N)->getSymbol(), MVT::i64),
250 case ISD::CALLSEQ_START:
251 case ISD::CALLSEQ_END: {
252 unsigned Amt = cast<ConstantSDNode>(N->getOperand(1))->getValue();
253 unsigned Opc = N->getOpcode() == ISD::CALLSEQ_START ?
254 Alpha::ADJUSTSTACKDOWN : Alpha::ADJUSTSTACKUP;
255 return CurDAG->SelectNodeTo(N, Opc, MVT::Other,
256 getI64Imm(Amt), Select(N->getOperand(0)));
259 SDOperand Chain = Select(N->getOperand(0)); // Token chain.
262 if (N->getNumOperands() == 2) {
263 SDOperand Val = Select(N->getOperand(1));
264 if (N->getOperand(1).getValueType() == MVT::i64) {
265 Chain = CurDAG->getCopyToReg(Chain, Alpha::R0, Val, InFlag);
266 InFlag = Chain.getValue(1);
269 Chain = CurDAG->getCopyToReg(Chain, Alpha::R26, getRASaveReg(), InFlag);
270 InFlag = Chain.getValue(1);
272 // Finally, select this to a ret instruction.
273 return CurDAG->SelectNodeTo(N, Alpha::RETDAG, MVT::Other, Chain, InFlag);
275 case ISD::Constant: {
276 int64_t val = (int64_t)cast<ConstantSDNode>(N)->getValue();
277 if (val > (int64_t)IMM_HIGH +(int64_t)IMM_HIGH* (int64_t)IMM_MULT ||
278 val < (int64_t)IMM_LOW + (int64_t)IMM_LOW * (int64_t)IMM_MULT) {
279 MachineConstantPool *CP = BB->getParent()->getConstantPool();
281 ConstantUInt::get(Type::getPrimitiveType(Type::ULongTyID) , val);
282 SDOperand Tmp, CPI = CurDAG->getTargetConstantPool(C, MVT::i64);
283 Tmp = CurDAG->getTargetNode(Alpha::LDAHr, MVT::i64, CPI, getGlobalBaseReg());
284 return CurDAG->SelectNodeTo(N, Alpha::LDQr, MVT::i64, CPI, Tmp);
288 case ISD::ConstantFP:
289 if (ConstantFPSDNode *CN = dyn_cast<ConstantFPSDNode>(N)) {
290 bool isDouble = N->getValueType(0) == MVT::f64;
291 MVT::ValueType T = isDouble ? MVT::f64 : MVT::f32;
292 if (CN->isExactlyValue(+0.0)) {
293 return CurDAG->SelectNodeTo(N, isDouble ? Alpha::CPYST : Alpha::CPYSS,
294 T, CurDAG->getRegister(Alpha::F31, T),
295 CurDAG->getRegister(Alpha::F31, T));
296 } else if ( CN->isExactlyValue(-0.0)) {
297 return CurDAG->SelectNodeTo(N, isDouble ? Alpha::CPYSNT : Alpha::CPYSNS,
298 T, CurDAG->getRegister(Alpha::F31, T),
299 CurDAG->getRegister(Alpha::F31, T));
309 if (MVT::isInteger(N->getValueType(0))) {
310 const char* opstr = 0;
311 switch(N->getOpcode()) {
312 case ISD::UREM: opstr = "__remqu"; break;
313 case ISD::SREM: opstr = "__remq"; break;
314 case ISD::UDIV: opstr = "__divqu"; break;
315 case ISD::SDIV: opstr = "__divq"; break;
317 SDOperand Tmp1 = Select(N->getOperand(0)),
318 Tmp2 = Select(N->getOperand(1)),
319 Addr = CurDAG->getExternalSymbol(opstr, AlphaLowering.getPointerTy());
320 SDOperand Tmp3 = Select(Addr);
321 SDOperand Chain = CurDAG->getCopyToReg(CurDAG->getRoot(), Alpha::R24,
323 Chain = CurDAG->getCopyToReg(CurDAG->getRoot(), Alpha::R25,
324 Tmp2, Chain.getValue(1));
325 Chain = CurDAG->getCopyToReg(CurDAG->getRoot(), Alpha::R27,
326 Tmp3, Chain.getValue(1));
327 Chain = CurDAG->getTargetNode(Alpha::JSRs, MVT::i64, MVT::Flag,
328 CurDAG->getRegister(Alpha::R27, MVT::i64),
330 return CurDAG->getCopyFromReg(Chain.getValue(1), Alpha::R27, MVT::i64,
336 if (MVT::isFloatingPoint(N->getOperand(0).Val->getValueType(0))) {
337 unsigned Opc = Alpha::WTF;
338 ISD::CondCode CC = cast<CondCodeSDNode>(N->getOperand(2))->get();
342 default: N->dump(); assert(0 && "Unknown FP comparison!");
343 case ISD::SETEQ: Opc = Alpha::CMPTEQ; break;
344 case ISD::SETLT: Opc = Alpha::CMPTLT; break;
345 case ISD::SETLE: Opc = Alpha::CMPTLE; break;
346 case ISD::SETGT: Opc = Alpha::CMPTLT; rev = true; break;
347 case ISD::SETGE: Opc = Alpha::CMPTLE; rev = true; break;
348 case ISD::SETNE: Opc = Alpha::CMPTEQ; isNE = true; break;
350 SDOperand tmp1 = Select(N->getOperand(0)),
351 tmp2 = Select(N->getOperand(1));
352 SDOperand cmp = CurDAG->getTargetNode(Opc, MVT::f64,
356 cmp = CurDAG->getTargetNode(Alpha::CMPTEQ, MVT::f64, cmp,
357 CurDAG->getRegister(Alpha::F31, MVT::f64));
360 if (AlphaLowering.hasITOF()) {
361 LD = CurDAG->getNode(AlphaISD::FTOIT_, MVT::i64, cmp);
364 CurDAG->getMachineFunction().getFrameInfo()->CreateStackObject(8, 8);
365 SDOperand FI = CurDAG->getFrameIndex(FrameIdx, MVT::i64);
366 SDOperand ST = CurDAG->getTargetNode(Alpha::STT, MVT::Other,
367 cmp, FI, CurDAG->getRegister(Alpha::R31, MVT::i64));
368 LD = CurDAG->getTargetNode(Alpha::LDQ, MVT::i64, FI,
369 CurDAG->getRegister(Alpha::R31, MVT::i64),
372 SDOperand FP = CurDAG->getTargetNode(Alpha::CMPULT, MVT::i64,
373 CurDAG->getRegister(Alpha::R31, MVT::i64),
380 if (MVT::isFloatingPoint(N->getValueType(0))) {
382 bool isDouble = N->getValueType(0) == MVT::f64;
384 cond = Select(N->getOperand(0)),
385 TV = Select(N->getOperand(1)),
386 FV = Select(N->getOperand(2));
388 if (AlphaLowering.hasITOF()) {
389 LD = CurDAG->getNode(AlphaISD::ITOFT_, MVT::f64, cond);
392 CurDAG->getMachineFunction().getFrameInfo()->CreateStackObject(8, 8);
393 SDOperand FI = CurDAG->getFrameIndex(FrameIdx, MVT::i64);
394 SDOperand ST = CurDAG->getTargetNode(Alpha::STQ, MVT::Other,
395 cond, FI, CurDAG->getRegister(Alpha::R31, MVT::i64));
396 LD = CurDAG->getTargetNode(Alpha::LDT, MVT::f64, FI,
397 CurDAG->getRegister(Alpha::R31, MVT::i64),
400 SDOperand FP = CurDAG->getTargetNode(isDouble?Alpha::FCMOVEQT:Alpha::FCMOVEQS,
401 MVT::f64, TV, FV, LD);
408 return SelectCode(Op);
411 SDOperand AlphaDAGToDAGISel::SelectCALL(SDOperand Op) {
412 //TODO: add flag stuff to prevent nondeturministic breakage!
415 SDOperand Chain = Select(N->getOperand(0));
416 SDOperand Addr = Select(N->getOperand(1));
417 SDOperand InFlag; // Null incoming flag value.
419 std::vector<SDOperand> CallOperands;
420 std::vector<MVT::ValueType> TypeOperands;
423 for(int i = 2, e = N->getNumOperands(); i < e; ++i) {
424 TypeOperands.push_back(N->getOperand(i).getValueType());
425 CallOperands.push_back(Select(N->getOperand(i)));
427 int count = N->getNumOperands() - 2;
429 static const unsigned args_int[] = {Alpha::R16, Alpha::R17, Alpha::R18,
430 Alpha::R19, Alpha::R20, Alpha::R21};
431 static const unsigned args_float[] = {Alpha::F16, Alpha::F17, Alpha::F18,
432 Alpha::F19, Alpha::F20, Alpha::F21};
434 for (int i = 6; i < count; ++i) {
435 unsigned Opc = Alpha::WTF;
436 if (MVT::isInteger(TypeOperands[i])) {
438 } else if (TypeOperands[i] == MVT::f32) {
440 } else if (TypeOperands[i] == MVT::f64) {
443 assert(0 && "Unknown operand");
444 Chain = CurDAG->getTargetNode(Opc, MVT::Other, CallOperands[i],
445 getI64Imm((i - 6) * 8),
446 CurDAG->getCopyFromReg(Chain, Alpha::R30, MVT::i64),
449 for (int i = 0; i < std::min(6, count); ++i) {
450 if (MVT::isInteger(TypeOperands[i])) {
451 Chain = CurDAG->getCopyToReg(Chain, args_int[i], CallOperands[i], InFlag);
452 InFlag = Chain.getValue(1);
453 } else if (TypeOperands[i] == MVT::f32 || TypeOperands[i] == MVT::f64) {
454 Chain = CurDAG->getCopyToReg(Chain, args_float[i], CallOperands[i], InFlag);
455 InFlag = Chain.getValue(1);
457 assert(0 && "Unknown operand");
461 Chain = CurDAG->getCopyToReg(Chain, Alpha::R27, Addr, InFlag);
462 InFlag = Chain.getValue(1);
463 // Finally, once everything is in registers to pass to the call, emit the
465 Chain = CurDAG->getTargetNode(Alpha::JSRDAG, MVT::Other, MVT::Flag,
467 InFlag = Chain.getValue(1);
469 std::vector<SDOperand> CallResults;
471 switch (N->getValueType(0)) {
472 default: assert(0 && "Unexpected ret value!");
473 case MVT::Other: break;
475 Chain = CurDAG->getCopyFromReg(Chain, Alpha::R0, MVT::i64, InFlag).getValue(1);
476 CallResults.push_back(Chain.getValue(0));
479 Chain = CurDAG->getCopyFromReg(Chain, Alpha::F0, MVT::f32, InFlag).getValue(1);
480 CallResults.push_back(Chain.getValue(0));
483 Chain = CurDAG->getCopyFromReg(Chain, Alpha::F0, MVT::f64, InFlag).getValue(1);
484 CallResults.push_back(Chain.getValue(0));
488 CallResults.push_back(Chain);
489 for (unsigned i = 0, e = CallResults.size(); i != e; ++i)
490 CodeGenMap[Op.getValue(i)] = CallResults[i];
491 return CallResults[Op.ResNo];
495 /// createAlphaISelDag - This pass converts a legalized DAG into a
496 /// Alpha-specific DAG, ready for instruction scheduling.
498 FunctionPass *llvm::createAlphaISelDag(TargetMachine &TM) {
499 return new AlphaDAGToDAGISel(TM);