1 //===-- AlphaISelDAGToDAG.cpp - Alpha pattern matching inst selector ------===//
3 // The LLVM Compiler Infrastructure
5 // This file was developed by Andrew Lenharth and is distributed under
6 // the University of Illinois Open Source License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines a pattern matching instruction selector for Alpha,
11 // converting from a legalized dag to a Alpha dag.
13 //===----------------------------------------------------------------------===//
16 #include "AlphaTargetMachine.h"
17 #include "AlphaISelLowering.h"
18 #include "llvm/CodeGen/MachineInstrBuilder.h"
19 #include "llvm/CodeGen/MachineFrameInfo.h"
20 #include "llvm/CodeGen/MachineFunction.h"
21 #include "llvm/CodeGen/SSARegMap.h"
22 #include "llvm/CodeGen/SelectionDAG.h"
23 #include "llvm/CodeGen/SelectionDAGISel.h"
24 #include "llvm/Target/TargetOptions.h"
25 #include "llvm/ADT/Statistic.h"
26 #include "llvm/Constants.h"
27 #include "llvm/GlobalValue.h"
28 #include "llvm/Intrinsics.h"
29 #include "llvm/Support/Debug.h"
30 #include "llvm/Support/MathExtras.h"
38 //===--------------------------------------------------------------------===//
39 /// AlphaDAGToDAGISel - Alpha specific code to select Alpha machine
40 /// instructions for SelectionDAG operations.
41 class AlphaDAGToDAGISel : public SelectionDAGISel {
42 AlphaTargetLowering AlphaLowering;
44 static const int64_t IMM_LOW = -32768;
45 static const int64_t IMM_HIGH = 32767;
46 static const int64_t IMM_MULT = 65536;
47 static const int64_t IMM_FULLHIGH = IMM_HIGH + IMM_HIGH * IMM_MULT;
48 static const int64_t IMM_FULLLOW = IMM_LOW + IMM_LOW * IMM_MULT;
50 static int64_t get_ldah16(int64_t x) {
51 int64_t y = x / IMM_MULT;
52 if (x % IMM_MULT > IMM_HIGH)
57 static int64_t get_lda16(int64_t x) {
58 return x - get_ldah16(x) * IMM_MULT;
61 static uint64_t get_zapImm(uint64_t x) {
62 unsigned int build = 0;
63 for(int i = 0; i < 8; ++i)
65 if ((x & 0x00FF) == 0x00FF)
67 else if ((x & 0x00FF) != 0)
74 static bool isFPZ(SDOperand N) {
75 ConstantFPSDNode *CN = dyn_cast<ConstantFPSDNode>(N);
76 return (CN && (CN->isExactlyValue(+0.0) || CN->isExactlyValue(-0.0)));
78 static bool isFPZn(SDOperand N) {
79 ConstantFPSDNode *CN = dyn_cast<ConstantFPSDNode>(N);
80 return (CN && CN->isExactlyValue(-0.0));
82 static bool isFPZp(SDOperand N) {
83 ConstantFPSDNode *CN = dyn_cast<ConstantFPSDNode>(N);
84 return (CN && CN->isExactlyValue(+0.0));
88 AlphaDAGToDAGISel(TargetMachine &TM)
89 : SelectionDAGISel(AlphaLowering), AlphaLowering(TM)
92 /// getI64Imm - Return a target constant with the specified value, of type
94 inline SDOperand getI64Imm(int64_t Imm) {
95 return CurDAG->getTargetConstant(Imm, MVT::i64);
98 // Select - Convert the specified operand from a target-independent to a
99 // target-specific node if it hasn't already been changed.
100 void Select(SDOperand &Result, SDOperand Op);
102 /// InstructionSelectBasicBlock - This callback is invoked by
103 /// SelectionDAGISel when it has created a SelectionDAG for us to codegen.
104 virtual void InstructionSelectBasicBlock(SelectionDAG &DAG);
106 virtual const char *getPassName() const {
107 return "Alpha DAG->DAG Pattern Instruction Selection";
110 // Include the pieces autogenerated from the target description.
111 #include "AlphaGenDAGISel.inc"
114 SDOperand getGlobalBaseReg();
115 SDOperand getRASaveReg();
116 SDOperand SelectCALL(SDOperand Op);
121 /// getGlobalBaseReg - Output the instructions required to put the
122 /// GOT address into a register.
124 SDOperand AlphaDAGToDAGISel::getGlobalBaseReg() {
125 return CurDAG->getCopyFromReg(CurDAG->getEntryNode(),
126 AlphaLowering.getVRegGP(),
130 /// getRASaveReg - Grab the return address
132 SDOperand AlphaDAGToDAGISel::getRASaveReg() {
133 return CurDAG->getCopyFromReg(CurDAG->getEntryNode(),
134 AlphaLowering.getVRegRA(),
138 /// InstructionSelectBasicBlock - This callback is invoked by
139 /// SelectionDAGISel when it has created a SelectionDAG for us to codegen.
140 void AlphaDAGToDAGISel::InstructionSelectBasicBlock(SelectionDAG &DAG) {
143 // Select target instructions for the DAG.
144 DAG.setRoot(SelectRoot(DAG.getRoot()));
146 DAG.RemoveDeadNodes();
148 // Emit machine code to BB.
149 ScheduleAndEmitDAG(DAG);
152 // Select - Convert the specified operand from a target-independent to a
153 // target-specific node if it hasn't already been changed.
154 void AlphaDAGToDAGISel::Select(SDOperand &Result, SDOperand Op) {
156 if (N->getOpcode() >= ISD::BUILTIN_OP_END &&
157 N->getOpcode() < AlphaISD::FIRST_NUMBER) {
159 return; // Already selected.
162 // If this has already been converted, use it.
163 std::map<SDOperand, SDOperand>::iterator CGMI = CodeGenMap.find(Op);
164 if (CGMI != CodeGenMap.end()) {
165 Result = CGMI->second;
169 switch (N->getOpcode()) {
172 Result = SelectCALL(Op);
175 case ISD::FrameIndex: {
176 int FI = cast<FrameIndexSDNode>(N)->getIndex();
177 Result = CurDAG->SelectNodeTo(N, Alpha::LDA, MVT::i64,
178 CurDAG->getTargetFrameIndex(FI, MVT::i32),
182 case AlphaISD::GlobalBaseReg:
183 Result = getGlobalBaseReg();
186 case AlphaISD::DivCall: {
187 SDOperand Chain = CurDAG->getEntryNode();
188 SDOperand N0, N1, N2;
189 Select(N0, Op.getOperand(0));
190 Select(N1, Op.getOperand(1));
191 Select(N2, Op.getOperand(2));
192 Chain = CurDAG->getCopyToReg(Chain, Alpha::R24, N1,
194 Chain = CurDAG->getCopyToReg(Chain, Alpha::R25, N2,
196 Chain = CurDAG->getCopyToReg(Chain, Alpha::R27, N0,
199 CurDAG->getTargetNode(Alpha::JSRs, MVT::Other, MVT::Flag,
200 Chain, Chain.getValue(1));
201 Chain = CurDAG->getCopyFromReg(Chain, Alpha::R27, MVT::i64,
202 SDOperand(CNode, 1));
203 Result = CurDAG->SelectNodeTo(N, Alpha::BIS, MVT::i64, Chain, Chain);
207 case ISD::READCYCLECOUNTER: {
209 Select(Chain, N->getOperand(0)); //Select chain
210 Result = CurDAG->SelectNodeTo(N, Alpha::RPCC, MVT::i64, Chain);
216 Select(Chain, N->getOperand(0)); // Token chain.
219 if (N->getNumOperands() == 2) {
221 Select(Val, N->getOperand(1));
222 if (N->getOperand(1).getValueType() == MVT::i64) {
223 Chain = CurDAG->getCopyToReg(Chain, Alpha::R0, Val, InFlag);
224 InFlag = Chain.getValue(1);
225 } else if (N->getOperand(1).getValueType() == MVT::f64 ||
226 N->getOperand(1).getValueType() == MVT::f32) {
227 Chain = CurDAG->getCopyToReg(Chain, Alpha::F0, Val, InFlag);
228 InFlag = Chain.getValue(1);
231 Chain = CurDAG->getCopyToReg(Chain, Alpha::R26, getRASaveReg(), InFlag);
232 InFlag = Chain.getValue(1);
234 // Finally, select this to a ret instruction.
235 Result = CurDAG->SelectNodeTo(N, Alpha::RETDAG, MVT::Other, Chain, InFlag);
238 case ISD::Constant: {
239 uint64_t uval = cast<ConstantSDNode>(N)->getValue();
242 Result = CurDAG->getCopyFromReg(CurDAG->getEntryNode(), Alpha::R31,
247 int64_t val = (int64_t)uval;
248 int32_t val32 = (int32_t)val;
249 if (val <= IMM_HIGH + IMM_HIGH * IMM_MULT &&
250 val >= IMM_LOW + IMM_LOW * IMM_MULT)
251 break; //(LDAH (LDA))
252 if ((uval >> 32) == 0 && //empty upper bits
253 val32 <= IMM_HIGH + IMM_HIGH * IMM_MULT)
254 // val32 >= IMM_LOW + IMM_LOW * IMM_MULT) //always true
255 break; //(zext (LDAH (LDA)))
256 //Else use the constant pool
257 MachineConstantPool *CP = BB->getParent()->getConstantPool();
259 ConstantUInt::get(Type::getPrimitiveType(Type::ULongTyID) , uval);
260 SDOperand CPI = CurDAG->getTargetConstantPool(C, MVT::i64);
261 SDNode *Tmp = CurDAG->getTargetNode(Alpha::LDAHr, MVT::i64, CPI,
263 Result = CurDAG->SelectNodeTo(N, Alpha::LDQr, MVT::i64, MVT::Other,
264 CPI, SDOperand(Tmp, 0), CurDAG->getEntryNode());
267 case ISD::TargetConstantFP: {
268 ConstantFPSDNode *CN = cast<ConstantFPSDNode>(N);
269 bool isDouble = N->getValueType(0) == MVT::f64;
270 MVT::ValueType T = isDouble ? MVT::f64 : MVT::f32;
271 if (CN->isExactlyValue(+0.0)) {
272 Result = CurDAG->SelectNodeTo(N, isDouble ? Alpha::CPYST : Alpha::CPYSS,
273 T, CurDAG->getRegister(Alpha::F31, T),
274 CurDAG->getRegister(Alpha::F31, T));
276 } else if ( CN->isExactlyValue(-0.0)) {
277 Result = CurDAG->SelectNodeTo(N, isDouble ? Alpha::CPYSNT : Alpha::CPYSNS,
278 T, CurDAG->getRegister(Alpha::F31, T),
279 CurDAG->getRegister(Alpha::F31, T));
288 if (MVT::isFloatingPoint(N->getOperand(0).Val->getValueType(0))) {
289 unsigned Opc = Alpha::WTF;
290 ISD::CondCode CC = cast<CondCodeSDNode>(N->getOperand(2))->get();
294 default: N->dump(); assert(0 && "Unknown FP comparison!");
295 case ISD::SETEQ: Opc = Alpha::CMPTEQ; break;
296 case ISD::SETLT: Opc = Alpha::CMPTLT; break;
297 case ISD::SETLE: Opc = Alpha::CMPTLE; break;
298 case ISD::SETGT: Opc = Alpha::CMPTLT; rev = true; break;
299 case ISD::SETGE: Opc = Alpha::CMPTLE; rev = true; break;
300 case ISD::SETNE: Opc = Alpha::CMPTEQ; isNE = true; break;
302 SDOperand tmp1, tmp2;
303 Select(tmp1, N->getOperand(0));
304 Select(tmp2, N->getOperand(1));
305 SDNode *cmp = CurDAG->getTargetNode(Opc, MVT::f64,
309 cmp = CurDAG->getTargetNode(Alpha::CMPTEQ, MVT::f64, SDOperand(cmp, 0),
310 CurDAG->getRegister(Alpha::F31, MVT::f64));
313 if (AlphaLowering.hasITOF()) {
314 LD = CurDAG->getNode(AlphaISD::FTOIT_, MVT::i64, SDOperand(cmp, 0));
317 CurDAG->getMachineFunction().getFrameInfo()->CreateStackObject(8, 8);
318 SDOperand FI = CurDAG->getFrameIndex(FrameIdx, MVT::i64);
320 SDOperand(CurDAG->getTargetNode(Alpha::STT, MVT::Other,
321 SDOperand(cmp, 0), FI,
322 CurDAG->getRegister(Alpha::R31, MVT::i64)), 0);
323 LD = SDOperand(CurDAG->getTargetNode(Alpha::LDQ, MVT::i64, FI,
324 CurDAG->getRegister(Alpha::R31, MVT::i64),
327 Result = SDOperand(CurDAG->getTargetNode(Alpha::CMPULT, MVT::i64,
328 CurDAG->getRegister(Alpha::R31, MVT::i64),
335 if (MVT::isFloatingPoint(N->getValueType(0)) &&
336 (N->getOperand(0).getOpcode() != ISD::SETCC ||
337 !MVT::isFloatingPoint(N->getOperand(0).getOperand(1).getValueType()))) {
338 //This should be the condition not covered by the Patterns
339 //FIXME: Don't have SelectCode die, but rather return something testable
340 // so that things like this can be caught in fall though code
342 bool isDouble = N->getValueType(0) == MVT::f64;
343 SDOperand LD, cond, TV, FV;
344 Select(cond, N->getOperand(0));
345 Select(TV, N->getOperand(1));
346 Select(FV, N->getOperand(2));
348 if (AlphaLowering.hasITOF()) {
349 LD = CurDAG->getNode(AlphaISD::ITOFT_, MVT::f64, cond);
352 CurDAG->getMachineFunction().getFrameInfo()->CreateStackObject(8, 8);
353 SDOperand FI = CurDAG->getFrameIndex(FrameIdx, MVT::i64);
355 SDOperand(CurDAG->getTargetNode(Alpha::STQ, MVT::Other,
356 cond, FI, CurDAG->getRegister(Alpha::R31, MVT::i64)), 0);
357 LD = SDOperand(CurDAG->getTargetNode(Alpha::LDT, MVT::f64, FI,
358 CurDAG->getRegister(Alpha::R31, MVT::i64),
361 Result = SDOperand(CurDAG->getTargetNode(isDouble?Alpha::FCMOVNET:Alpha::FCMOVNES,
362 MVT::f64, FV, TV, LD), 0);
370 if (N->getOperand(0).getOpcode() == ISD::SRL &&
371 (MC = dyn_cast<ConstantSDNode>(N->getOperand(1))) &&
372 (SC = dyn_cast<ConstantSDNode>(N->getOperand(0).getOperand(1))))
374 uint64_t sval = SC->getValue();
375 uint64_t mval = MC->getValue();
376 if (get_zapImm(mval)) //the result is a zap, let the autogened stuff deal
378 // given mask X, and shift S, we want to see if there is any zap in the mask
379 // if we play around with the botton S bits
380 uint64_t dontcare = (~0ULL) >> (64 - sval);
381 uint64_t mask = mval << sval;
383 if (get_zapImm(mask | dontcare))
384 mask = mask | dontcare;
386 if (get_zapImm(mask)) {
388 Select(Src, N->getOperand(0).getOperand(0));
390 SDOperand(CurDAG->getTargetNode(Alpha::ZAPNOTi, MVT::i64, Src,
391 getI64Imm(get_zapImm(mask))), 0);
392 Result = SDOperand(CurDAG->getTargetNode(Alpha::SRL, MVT::i64, Z,
393 getI64Imm(sval)), 0);
402 SelectCode(Result, Op);
405 SDOperand AlphaDAGToDAGISel::SelectCALL(SDOperand Op) {
406 //TODO: add flag stuff to prevent nondeturministic breakage!
410 SDOperand Addr = N->getOperand(1);
411 SDOperand InFlag; // Null incoming flag value.
412 Select(Chain, N->getOperand(0));
414 std::vector<SDOperand> CallOperands;
415 std::vector<MVT::ValueType> TypeOperands;
418 for(int i = 2, e = N->getNumOperands(); i < e; ++i) {
420 TypeOperands.push_back(N->getOperand(i).getValueType());
421 Select(Tmp, N->getOperand(i));
422 CallOperands.push_back(Tmp);
424 int count = N->getNumOperands() - 2;
426 static const unsigned args_int[] = {Alpha::R16, Alpha::R17, Alpha::R18,
427 Alpha::R19, Alpha::R20, Alpha::R21};
428 static const unsigned args_float[] = {Alpha::F16, Alpha::F17, Alpha::F18,
429 Alpha::F19, Alpha::F20, Alpha::F21};
431 for (int i = 6; i < count; ++i) {
432 unsigned Opc = Alpha::WTF;
433 if (MVT::isInteger(TypeOperands[i])) {
435 } else if (TypeOperands[i] == MVT::f32) {
437 } else if (TypeOperands[i] == MVT::f64) {
440 assert(0 && "Unknown operand");
441 Chain = SDOperand(CurDAG->getTargetNode(Opc, MVT::Other, CallOperands[i],
442 getI64Imm((i - 6) * 8),
443 CurDAG->getCopyFromReg(Chain, Alpha::R30, MVT::i64),
446 for (int i = 0; i < std::min(6, count); ++i) {
447 if (MVT::isInteger(TypeOperands[i])) {
448 Chain = CurDAG->getCopyToReg(Chain, args_int[i], CallOperands[i], InFlag);
449 InFlag = Chain.getValue(1);
450 } else if (TypeOperands[i] == MVT::f32 || TypeOperands[i] == MVT::f64) {
451 Chain = CurDAG->getCopyToReg(Chain, args_float[i], CallOperands[i], InFlag);
452 InFlag = Chain.getValue(1);
454 assert(0 && "Unknown operand");
458 // Finally, once everything is in registers to pass to the call, emit the
460 if (Addr.getOpcode() == AlphaISD::GPRelLo) {
461 SDOperand GOT = getGlobalBaseReg();
462 Chain = CurDAG->getCopyToReg(Chain, Alpha::R29, GOT, InFlag);
463 InFlag = Chain.getValue(1);
464 Chain = SDOperand(CurDAG->getTargetNode(Alpha::BSR, MVT::Other, MVT::Flag,
465 Addr.getOperand(0), Chain, InFlag), 0);
468 Chain = CurDAG->getCopyToReg(Chain, Alpha::R27, Addr, InFlag);
469 InFlag = Chain.getValue(1);
470 Chain = SDOperand(CurDAG->getTargetNode(Alpha::JSR, MVT::Other, MVT::Flag,
473 InFlag = Chain.getValue(1);
475 std::vector<SDOperand> CallResults;
477 switch (N->getValueType(0)) {
478 default: assert(0 && "Unexpected ret value!");
479 case MVT::Other: break;
481 Chain = CurDAG->getCopyFromReg(Chain, Alpha::R0, MVT::i64, InFlag).getValue(1);
482 CallResults.push_back(Chain.getValue(0));
485 Chain = CurDAG->getCopyFromReg(Chain, Alpha::F0, MVT::f32, InFlag).getValue(1);
486 CallResults.push_back(Chain.getValue(0));
489 Chain = CurDAG->getCopyFromReg(Chain, Alpha::F0, MVT::f64, InFlag).getValue(1);
490 CallResults.push_back(Chain.getValue(0));
494 CallResults.push_back(Chain);
495 for (unsigned i = 0, e = CallResults.size(); i != e; ++i)
496 CodeGenMap[Op.getValue(i)] = CallResults[i];
497 return CallResults[Op.ResNo];
501 /// createAlphaISelDag - This pass converts a legalized DAG into a
502 /// Alpha-specific DAG, ready for instruction scheduling.
504 FunctionPass *llvm::createAlphaISelDag(TargetMachine &TM) {
505 return new AlphaDAGToDAGISel(TM);