1 //===-- AlphaISelDAGToDAG.cpp - Alpha pattern matching inst selector ------===//
3 // The LLVM Compiler Infrastructure
5 // This file was developed by Andrew Lenharth and is distributed under
6 // the University of Illinois Open Source License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines a pattern matching instruction selector for Alpha,
11 // converting from a legalized dag to a Alpha dag.
13 //===----------------------------------------------------------------------===//
16 #include "AlphaTargetMachine.h"
17 #include "AlphaISelLowering.h"
18 #include "llvm/CodeGen/MachineInstrBuilder.h"
19 #include "llvm/CodeGen/MachineFrameInfo.h"
20 #include "llvm/CodeGen/MachineFunction.h"
21 #include "llvm/CodeGen/SSARegMap.h"
22 #include "llvm/CodeGen/SelectionDAG.h"
23 #include "llvm/CodeGen/SelectionDAGISel.h"
24 #include "llvm/Target/TargetOptions.h"
25 #include "llvm/ADT/Statistic.h"
26 #include "llvm/Constants.h"
27 #include "llvm/GlobalValue.h"
28 #include "llvm/Intrinsics.h"
29 #include "llvm/Support/Debug.h"
30 #include "llvm/Support/MathExtras.h"
39 //===--------------------------------------------------------------------===//
40 /// AlphaDAGToDAGISel - Alpha specific code to select Alpha machine
41 /// instructions for SelectionDAG operations.
42 class AlphaDAGToDAGISel : public SelectionDAGISel {
43 AlphaTargetLowering AlphaLowering;
45 static const int64_t IMM_LOW = -32768;
46 static const int64_t IMM_HIGH = 32767;
47 static const int64_t IMM_MULT = 65536;
48 static const int64_t IMM_FULLHIGH = IMM_HIGH + IMM_HIGH * IMM_MULT;
49 static const int64_t IMM_FULLLOW = IMM_LOW + IMM_LOW * IMM_MULT;
51 static int64_t get_ldah16(int64_t x) {
52 int64_t y = x / IMM_MULT;
53 if (x % IMM_MULT > IMM_HIGH)
58 static int64_t get_lda16(int64_t x) {
59 return x - get_ldah16(x) * IMM_MULT;
62 /// get_zapImm - Return a zap mask if X is a valid immediate for a zapnot
63 /// instruction (if not, return 0). Note that this code accepts partial
64 /// zap masks. For example (and LHS, 1) is a valid zap, as long we know
65 /// that the bits 1-7 of LHS are already zero. If LHS is non-null, we are
66 /// in checking mode. If LHS is null, we assume that the mask has already
67 /// been validated before.
68 uint64_t get_zapImm(SDOperand LHS, uint64_t Constant) {
69 uint64_t BitsToCheck = 0;
71 for (unsigned i = 0; i != 8; ++i) {
72 if (((Constant >> 8*i) & 0xFF) == 0) {
76 if (((Constant >> 8*i) & 0xFF) == 0xFF) {
77 // If the entire byte is set, zapnot the byte.
78 } else if (LHS.Val == 0) {
79 // Otherwise, if the mask was previously validated, we know its okay
80 // to zapnot this entire byte even though all the bits aren't set.
82 // Otherwise we don't know that the it's okay to zapnot this entire
83 // byte. Only do this iff we can prove that the missing bits are
84 // already null, so the bytezap doesn't need to really null them.
85 BitsToCheck |= ~Constant & (0xFF << 8*i);
90 // If there are missing bits in a byte (for example, X & 0xEF00), check to
91 // see if the missing bits (0x1000) are already known zero if not, the zap
92 // isn't okay to do, as it won't clear all the required bits.
94 !getTargetLowering().MaskedValueIsZero(LHS, BitsToCheck))
100 static uint64_t get_zapImm(uint64_t x) {
102 for(int i = 0; i != 8; ++i) {
103 if ((x & 0x00FF) == 0x00FF)
105 else if ((x & 0x00FF) != 0)
113 static uint64_t getNearPower2(uint64_t x) {
115 unsigned at = CountLeadingZeros_64(x);
116 uint64_t complow = 1 << (63 - at);
117 uint64_t comphigh = 1 << (64 - at);
118 //std::cerr << x << ":" << complow << ":" << comphigh << "\n";
119 if (abs(complow - x) <= abs(comphigh - x))
125 static bool isFPZ(SDOperand N) {
126 ConstantFPSDNode *CN = dyn_cast<ConstantFPSDNode>(N);
127 return (CN && (CN->isExactlyValue(+0.0) || CN->isExactlyValue(-0.0)));
129 static bool isFPZn(SDOperand N) {
130 ConstantFPSDNode *CN = dyn_cast<ConstantFPSDNode>(N);
131 return (CN && CN->isExactlyValue(-0.0));
133 static bool isFPZp(SDOperand N) {
134 ConstantFPSDNode *CN = dyn_cast<ConstantFPSDNode>(N);
135 return (CN && CN->isExactlyValue(+0.0));
139 AlphaDAGToDAGISel(TargetMachine &TM)
140 : SelectionDAGISel(AlphaLowering),
141 AlphaLowering(*(AlphaTargetLowering*)(TM.getTargetLowering()))
144 /// getI64Imm - Return a target constant with the specified value, of type
146 inline SDOperand getI64Imm(int64_t Imm) {
147 return CurDAG->getTargetConstant(Imm, MVT::i64);
150 // Select - Convert the specified operand from a target-independent to a
151 // target-specific node if it hasn't already been changed.
152 SDNode *Select(SDOperand Op);
154 /// InstructionSelectBasicBlock - This callback is invoked by
155 /// SelectionDAGISel when it has created a SelectionDAG for us to codegen.
156 virtual void InstructionSelectBasicBlock(SelectionDAG &DAG);
158 virtual const char *getPassName() const {
159 return "Alpha DAG->DAG Pattern Instruction Selection";
162 /// SelectInlineAsmMemoryOperand - Implement addressing mode selection for
163 /// inline asm expressions.
164 virtual bool SelectInlineAsmMemoryOperand(const SDOperand &Op,
166 std::vector<SDOperand> &OutOps,
169 switch (ConstraintCode) {
170 default: return true;
177 OutOps.push_back(Op0);
181 // Include the pieces autogenerated from the target description.
182 #include "AlphaGenDAGISel.inc"
185 SDOperand getGlobalBaseReg();
186 SDOperand getGlobalRetAddr();
187 void SelectCALL(SDOperand Op);
192 /// getGlobalBaseReg - Output the instructions required to put the
193 /// GOT address into a register.
195 SDOperand AlphaDAGToDAGISel::getGlobalBaseReg() {
196 MachineFunction* MF = BB->getParent();
198 for(MachineFunction::livein_iterator ii = MF->livein_begin(),
199 ee = MF->livein_end(); ii != ee; ++ii)
200 if (ii->first == Alpha::R29) {
204 assert(GP && "GOT PTR not in liveins");
205 return CurDAG->getCopyFromReg(CurDAG->getEntryNode(),
209 /// getRASaveReg - Grab the return address
211 SDOperand AlphaDAGToDAGISel::getGlobalRetAddr() {
212 MachineFunction* MF = BB->getParent();
214 for(MachineFunction::livein_iterator ii = MF->livein_begin(),
215 ee = MF->livein_end(); ii != ee; ++ii)
216 if (ii->first == Alpha::R26) {
220 assert(RA && "RA PTR not in liveins");
221 return CurDAG->getCopyFromReg(CurDAG->getEntryNode(),
225 /// InstructionSelectBasicBlock - This callback is invoked by
226 /// SelectionDAGISel when it has created a SelectionDAG for us to codegen.
227 void AlphaDAGToDAGISel::InstructionSelectBasicBlock(SelectionDAG &DAG) {
230 // Select target instructions for the DAG.
231 DAG.setRoot(SelectRoot(DAG.getRoot()));
232 DAG.RemoveDeadNodes();
234 // Emit machine code to BB.
235 ScheduleAndEmitDAG(DAG);
238 // Select - Convert the specified operand from a target-independent to a
239 // target-specific node if it hasn't already been changed.
240 SDNode *AlphaDAGToDAGISel::Select(SDOperand Op) {
242 if (N->getOpcode() >= ISD::BUILTIN_OP_END &&
243 N->getOpcode() < AlphaISD::FIRST_NUMBER) {
244 return NULL; // Already selected.
247 switch (N->getOpcode()) {
253 case ISD::FrameIndex: {
254 int FI = cast<FrameIndexSDNode>(N)->getIndex();
255 return CurDAG->SelectNodeTo(N, Alpha::LDA, MVT::i64,
256 CurDAG->getTargetFrameIndex(FI, MVT::i32),
259 case ISD::GLOBAL_OFFSET_TABLE: {
260 SDOperand Result = getGlobalBaseReg();
261 ReplaceUses(Op, Result);
264 case AlphaISD::GlobalRetAddr: {
265 SDOperand Result = getGlobalRetAddr();
266 ReplaceUses(Op, Result);
270 case AlphaISD::DivCall: {
271 SDOperand Chain = CurDAG->getEntryNode();
272 SDOperand N0 = Op.getOperand(0);
273 SDOperand N1 = Op.getOperand(1);
274 SDOperand N2 = Op.getOperand(2);
278 Chain = CurDAG->getCopyToReg(Chain, Alpha::R24, N1,
280 Chain = CurDAG->getCopyToReg(Chain, Alpha::R25, N2,
282 Chain = CurDAG->getCopyToReg(Chain, Alpha::R27, N0,
285 CurDAG->getTargetNode(Alpha::JSRs, MVT::Other, MVT::Flag,
286 Chain, Chain.getValue(1));
287 Chain = CurDAG->getCopyFromReg(Chain, Alpha::R27, MVT::i64,
288 SDOperand(CNode, 1));
289 return CurDAG->SelectNodeTo(N, Alpha::BIS, MVT::i64, Chain, Chain);
292 case ISD::READCYCLECOUNTER: {
293 SDOperand Chain = N->getOperand(0);
294 AddToISelQueue(Chain); //Select chain
295 return CurDAG->getTargetNode(Alpha::RPCC, MVT::i64, MVT::Other,
299 case ISD::Constant: {
300 uint64_t uval = cast<ConstantSDNode>(N)->getValue();
303 SDOperand Result = CurDAG->getCopyFromReg(CurDAG->getEntryNode(),
304 Alpha::R31, MVT::i64);
305 ReplaceUses(Op, Result);
309 int64_t val = (int64_t)uval;
310 int32_t val32 = (int32_t)val;
311 if (val <= IMM_HIGH + IMM_HIGH * IMM_MULT &&
312 val >= IMM_LOW + IMM_LOW * IMM_MULT)
313 break; //(LDAH (LDA))
314 if ((uval >> 32) == 0 && //empty upper bits
315 val32 <= IMM_HIGH + IMM_HIGH * IMM_MULT)
316 // val32 >= IMM_LOW + IMM_LOW * IMM_MULT) //always true
317 break; //(zext (LDAH (LDA)))
318 //Else use the constant pool
319 MachineConstantPool *CP = BB->getParent()->getConstantPool();
321 ConstantUInt::get(Type::getPrimitiveType(Type::ULongTyID) , uval);
322 SDOperand CPI = CurDAG->getTargetConstantPool(C, MVT::i64);
323 SDNode *Tmp = CurDAG->getTargetNode(Alpha::LDAHr, MVT::i64, CPI,
325 return CurDAG->SelectNodeTo(N, Alpha::LDQr, MVT::i64, MVT::Other,
326 CPI, SDOperand(Tmp, 0), CurDAG->getEntryNode());
328 case ISD::TargetConstantFP: {
329 ConstantFPSDNode *CN = cast<ConstantFPSDNode>(N);
330 bool isDouble = N->getValueType(0) == MVT::f64;
331 MVT::ValueType T = isDouble ? MVT::f64 : MVT::f32;
332 if (CN->isExactlyValue(+0.0)) {
333 return CurDAG->SelectNodeTo(N, isDouble ? Alpha::CPYST : Alpha::CPYSS,
334 T, CurDAG->getRegister(Alpha::F31, T),
335 CurDAG->getRegister(Alpha::F31, T));
336 } else if ( CN->isExactlyValue(-0.0)) {
337 return CurDAG->SelectNodeTo(N, isDouble ? Alpha::CPYSNT : Alpha::CPYSNS,
338 T, CurDAG->getRegister(Alpha::F31, T),
339 CurDAG->getRegister(Alpha::F31, T));
347 if (MVT::isFloatingPoint(N->getOperand(0).Val->getValueType(0))) {
348 unsigned Opc = Alpha::WTF;
349 ISD::CondCode CC = cast<CondCodeSDNode>(N->getOperand(2))->get();
353 default: DEBUG(N->dump()); assert(0 && "Unknown FP comparison!");
354 case ISD::SETEQ: case ISD::SETOEQ: case ISD::SETUEQ: Opc = Alpha::CMPTEQ; break;
355 case ISD::SETLT: case ISD::SETOLT: case ISD::SETULT: Opc = Alpha::CMPTLT; break;
356 case ISD::SETLE: case ISD::SETOLE: case ISD::SETULE: Opc = Alpha::CMPTLE; break;
357 case ISD::SETGT: case ISD::SETOGT: case ISD::SETUGT: Opc = Alpha::CMPTLT; rev = true; break;
358 case ISD::SETGE: case ISD::SETOGE: case ISD::SETUGE: Opc = Alpha::CMPTLE; rev = true; break;
359 case ISD::SETNE: case ISD::SETONE: case ISD::SETUNE: Opc = Alpha::CMPTEQ; isNE = true; break;
361 SDOperand tmp1 = N->getOperand(0);
362 SDOperand tmp2 = N->getOperand(1);
363 AddToISelQueue(tmp1);
364 AddToISelQueue(tmp2);
365 SDNode *cmp = CurDAG->getTargetNode(Opc, MVT::f64,
369 cmp = CurDAG->getTargetNode(Alpha::CMPTEQ, MVT::f64, SDOperand(cmp, 0),
370 CurDAG->getRegister(Alpha::F31, MVT::f64));
373 if (AlphaLowering.hasITOF()) {
374 LD = CurDAG->getNode(AlphaISD::FTOIT_, MVT::i64, SDOperand(cmp, 0));
377 CurDAG->getMachineFunction().getFrameInfo()->CreateStackObject(8, 8);
378 SDOperand FI = CurDAG->getFrameIndex(FrameIdx, MVT::i64);
380 SDOperand(CurDAG->getTargetNode(Alpha::STT, MVT::Other,
381 SDOperand(cmp, 0), FI,
382 CurDAG->getRegister(Alpha::R31, MVT::i64)), 0);
383 LD = SDOperand(CurDAG->getTargetNode(Alpha::LDQ, MVT::i64, FI,
384 CurDAG->getRegister(Alpha::R31, MVT::i64),
387 return CurDAG->getTargetNode(Alpha::CMPULT, MVT::i64,
388 CurDAG->getRegister(Alpha::R31, MVT::i64),
394 if (MVT::isFloatingPoint(N->getValueType(0)) &&
395 (N->getOperand(0).getOpcode() != ISD::SETCC ||
396 !MVT::isFloatingPoint(N->getOperand(0).getOperand(1).getValueType()))) {
397 //This should be the condition not covered by the Patterns
398 //FIXME: Don't have SelectCode die, but rather return something testable
399 // so that things like this can be caught in fall though code
401 bool isDouble = N->getValueType(0) == MVT::f64;
403 SDOperand cond = N->getOperand(0);
404 SDOperand TV = N->getOperand(1);
405 SDOperand FV = N->getOperand(2);
406 AddToISelQueue(cond);
410 if (AlphaLowering.hasITOF()) {
411 LD = CurDAG->getNode(AlphaISD::ITOFT_, MVT::f64, cond);
414 CurDAG->getMachineFunction().getFrameInfo()->CreateStackObject(8, 8);
415 SDOperand FI = CurDAG->getFrameIndex(FrameIdx, MVT::i64);
417 SDOperand(CurDAG->getTargetNode(Alpha::STQ, MVT::Other,
418 cond, FI, CurDAG->getRegister(Alpha::R31, MVT::i64)), 0);
419 LD = SDOperand(CurDAG->getTargetNode(Alpha::LDT, MVT::f64, FI,
420 CurDAG->getRegister(Alpha::R31, MVT::i64),
423 return CurDAG->getTargetNode(isDouble?Alpha::FCMOVNET:Alpha::FCMOVNES,
424 MVT::f64, FV, TV, LD);
429 ConstantSDNode* SC = NULL;
430 ConstantSDNode* MC = NULL;
431 if (N->getOperand(0).getOpcode() == ISD::SRL &&
432 (MC = dyn_cast<ConstantSDNode>(N->getOperand(1))) &&
433 (SC = dyn_cast<ConstantSDNode>(N->getOperand(0).getOperand(1))))
435 uint64_t sval = SC->getValue();
436 uint64_t mval = MC->getValue();
437 // If the result is a zap, let the autogened stuff handle it.
438 if (get_zapImm(N->getOperand(0), mval))
440 // given mask X, and shift S, we want to see if there is any zap in the
441 // mask if we play around with the botton S bits
442 uint64_t dontcare = (~0ULL) >> (64 - sval);
443 uint64_t mask = mval << sval;
445 if (get_zapImm(mask | dontcare))
446 mask = mask | dontcare;
448 if (get_zapImm(mask)) {
449 AddToISelQueue(N->getOperand(0).getOperand(0));
451 SDOperand(CurDAG->getTargetNode(Alpha::ZAPNOTi, MVT::i64,
452 N->getOperand(0).getOperand(0),
453 getI64Imm(get_zapImm(mask))), 0);
454 return CurDAG->getTargetNode(Alpha::SRL, MVT::i64, Z,
463 return SelectCode(Op);
466 void AlphaDAGToDAGISel::SelectCALL(SDOperand Op) {
467 //TODO: add flag stuff to prevent nondeturministic breakage!
470 SDOperand Chain = N->getOperand(0);
471 SDOperand Addr = N->getOperand(1);
472 SDOperand InFlag(0,0); // Null incoming flag value.
473 AddToISelQueue(Chain);
475 std::vector<SDOperand> CallOperands;
476 std::vector<MVT::ValueType> TypeOperands;
479 for(int i = 2, e = N->getNumOperands(); i < e; ++i) {
480 TypeOperands.push_back(N->getOperand(i).getValueType());
481 AddToISelQueue(N->getOperand(i));
482 CallOperands.push_back(N->getOperand(i));
484 int count = N->getNumOperands() - 2;
486 static const unsigned args_int[] = {Alpha::R16, Alpha::R17, Alpha::R18,
487 Alpha::R19, Alpha::R20, Alpha::R21};
488 static const unsigned args_float[] = {Alpha::F16, Alpha::F17, Alpha::F18,
489 Alpha::F19, Alpha::F20, Alpha::F21};
491 for (int i = 6; i < count; ++i) {
492 unsigned Opc = Alpha::WTF;
493 if (MVT::isInteger(TypeOperands[i])) {
495 } else if (TypeOperands[i] == MVT::f32) {
497 } else if (TypeOperands[i] == MVT::f64) {
500 assert(0 && "Unknown operand");
502 SDOperand Ops[] = { CallOperands[i], getI64Imm((i - 6) * 8),
503 CurDAG->getCopyFromReg(Chain, Alpha::R30, MVT::i64),
505 Chain = SDOperand(CurDAG->getTargetNode(Opc, MVT::Other, Ops, 4), 0);
507 for (int i = 0; i < std::min(6, count); ++i) {
508 if (MVT::isInteger(TypeOperands[i])) {
509 Chain = CurDAG->getCopyToReg(Chain, args_int[i], CallOperands[i], InFlag);
510 InFlag = Chain.getValue(1);
511 } else if (TypeOperands[i] == MVT::f32 || TypeOperands[i] == MVT::f64) {
512 Chain = CurDAG->getCopyToReg(Chain, args_float[i], CallOperands[i], InFlag);
513 InFlag = Chain.getValue(1);
515 assert(0 && "Unknown operand");
518 // Finally, once everything is in registers to pass to the call, emit the
520 if (Addr.getOpcode() == AlphaISD::GPRelLo) {
521 SDOperand GOT = getGlobalBaseReg();
522 Chain = CurDAG->getCopyToReg(Chain, Alpha::R29, GOT, InFlag);
523 InFlag = Chain.getValue(1);
524 Chain = SDOperand(CurDAG->getTargetNode(Alpha::BSR, MVT::Other, MVT::Flag,
525 Addr.getOperand(0), Chain, InFlag), 0);
527 AddToISelQueue(Addr);
528 Chain = CurDAG->getCopyToReg(Chain, Alpha::R27, Addr, InFlag);
529 InFlag = Chain.getValue(1);
530 Chain = SDOperand(CurDAG->getTargetNode(Alpha::JSR, MVT::Other, MVT::Flag,
533 InFlag = Chain.getValue(1);
535 std::vector<SDOperand> CallResults;
537 switch (N->getValueType(0)) {
538 default: assert(0 && "Unexpected ret value!");
539 case MVT::Other: break;
541 Chain = CurDAG->getCopyFromReg(Chain, Alpha::R0, MVT::i64, InFlag).getValue(1);
542 CallResults.push_back(Chain.getValue(0));
545 Chain = CurDAG->getCopyFromReg(Chain, Alpha::F0, MVT::f32, InFlag).getValue(1);
546 CallResults.push_back(Chain.getValue(0));
549 Chain = CurDAG->getCopyFromReg(Chain, Alpha::F0, MVT::f64, InFlag).getValue(1);
550 CallResults.push_back(Chain.getValue(0));
554 CallResults.push_back(Chain);
555 for (unsigned i = 0, e = CallResults.size(); i != e; ++i)
556 ReplaceUses(Op.getValue(i), CallResults[i]);
560 /// createAlphaISelDag - This pass converts a legalized DAG into a
561 /// Alpha-specific DAG, ready for instruction scheduling.
563 FunctionPass *llvm::createAlphaISelDag(TargetMachine &TM) {
564 return new AlphaDAGToDAGISel(TM);