1 //===-- AlphaISelDAGToDAG.cpp - Alpha pattern matching inst selector ------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines a pattern matching instruction selector for Alpha,
11 // converting from a legalized dag to a Alpha dag.
13 //===----------------------------------------------------------------------===//
16 #include "AlphaTargetMachine.h"
17 #include "AlphaISelLowering.h"
18 #include "llvm/CodeGen/MachineInstrBuilder.h"
19 #include "llvm/CodeGen/MachineFrameInfo.h"
20 #include "llvm/CodeGen/MachineFunction.h"
21 #include "llvm/CodeGen/MachineRegisterInfo.h"
22 #include "llvm/CodeGen/SelectionDAG.h"
23 #include "llvm/CodeGen/SelectionDAGISel.h"
24 #include "llvm/Target/TargetOptions.h"
25 #include "llvm/Constants.h"
26 #include "llvm/DerivedTypes.h"
27 #include "llvm/GlobalValue.h"
28 #include "llvm/Intrinsics.h"
29 #include "llvm/Support/Compiler.h"
30 #include "llvm/Support/Debug.h"
31 #include "llvm/Support/MathExtras.h"
39 //===--------------------------------------------------------------------===//
40 /// AlphaDAGToDAGISel - Alpha specific code to select Alpha machine
41 /// instructions for SelectionDAG operations.
42 class AlphaDAGToDAGISel : public SelectionDAGISel {
43 AlphaTargetLowering AlphaLowering;
45 static const int64_t IMM_LOW = -32768;
46 static const int64_t IMM_HIGH = 32767;
47 static const int64_t IMM_MULT = 65536;
48 static const int64_t IMM_FULLHIGH = IMM_HIGH + IMM_HIGH * IMM_MULT;
49 static const int64_t IMM_FULLLOW = IMM_LOW + IMM_LOW * IMM_MULT;
51 static int64_t get_ldah16(int64_t x) {
52 int64_t y = x / IMM_MULT;
53 if (x % IMM_MULT > IMM_HIGH)
58 static int64_t get_lda16(int64_t x) {
59 return x - get_ldah16(x) * IMM_MULT;
62 /// get_zapImm - Return a zap mask if X is a valid immediate for a zapnot
63 /// instruction (if not, return 0). Note that this code accepts partial
64 /// zap masks. For example (and LHS, 1) is a valid zap, as long we know
65 /// that the bits 1-7 of LHS are already zero. If LHS is non-null, we are
66 /// in checking mode. If LHS is null, we assume that the mask has already
67 /// been validated before.
68 uint64_t get_zapImm(SDOperand LHS, uint64_t Constant) {
69 uint64_t BitsToCheck = 0;
71 for (unsigned i = 0; i != 8; ++i) {
72 if (((Constant >> 8*i) & 0xFF) == 0) {
76 if (((Constant >> 8*i) & 0xFF) == 0xFF) {
77 // If the entire byte is set, zapnot the byte.
78 } else if (LHS.Val == 0) {
79 // Otherwise, if the mask was previously validated, we know its okay
80 // to zapnot this entire byte even though all the bits aren't set.
82 // Otherwise we don't know that the it's okay to zapnot this entire
83 // byte. Only do this iff we can prove that the missing bits are
84 // already null, so the bytezap doesn't need to really null them.
85 BitsToCheck |= ~Constant & (0xFF << 8*i);
90 // If there are missing bits in a byte (for example, X & 0xEF00), check to
91 // see if the missing bits (0x1000) are already known zero if not, the zap
92 // isn't okay to do, as it won't clear all the required bits.
94 !CurDAG->MaskedValueIsZero(LHS,
95 APInt(LHS.getValueSizeInBits(),
102 static uint64_t get_zapImm(uint64_t x) {
104 for(int i = 0; i != 8; ++i) {
105 if ((x & 0x00FF) == 0x00FF)
107 else if ((x & 0x00FF) != 0)
115 static uint64_t getNearPower2(uint64_t x) {
117 unsigned at = CountLeadingZeros_64(x);
118 uint64_t complow = 1 << (63 - at);
119 uint64_t comphigh = 1 << (64 - at);
120 //cerr << x << ":" << complow << ":" << comphigh << "\n";
121 if (abs(complow - x) <= abs(comphigh - x))
127 static bool chkRemNearPower2(uint64_t x, uint64_t r, bool swap) {
128 uint64_t y = getNearPower2(x);
135 static bool isFPZ(SDOperand N) {
136 ConstantFPSDNode *CN = dyn_cast<ConstantFPSDNode>(N);
137 return (CN && (CN->getValueAPF().isZero()));
139 static bool isFPZn(SDOperand N) {
140 ConstantFPSDNode *CN = dyn_cast<ConstantFPSDNode>(N);
141 return (CN && CN->getValueAPF().isNegZero());
143 static bool isFPZp(SDOperand N) {
144 ConstantFPSDNode *CN = dyn_cast<ConstantFPSDNode>(N);
145 return (CN && CN->getValueAPF().isPosZero());
149 explicit AlphaDAGToDAGISel(AlphaTargetMachine &TM)
150 : SelectionDAGISel(AlphaLowering),
151 AlphaLowering(*TM.getTargetLowering())
154 /// getI64Imm - Return a target constant with the specified value, of type
156 inline SDOperand getI64Imm(int64_t Imm) {
157 return CurDAG->getTargetConstant(Imm, MVT::i64);
160 // Select - Convert the specified operand from a target-independent to a
161 // target-specific node if it hasn't already been changed.
162 SDNode *Select(SDOperand Op);
164 /// InstructionSelectBasicBlock - This callback is invoked by
165 /// SelectionDAGISel when it has created a SelectionDAG for us to codegen.
166 virtual void InstructionSelectBasicBlock(SelectionDAG &DAG);
168 virtual const char *getPassName() const {
169 return "Alpha DAG->DAG Pattern Instruction Selection";
172 /// SelectInlineAsmMemoryOperand - Implement addressing mode selection for
173 /// inline asm expressions.
174 virtual bool SelectInlineAsmMemoryOperand(const SDOperand &Op,
176 std::vector<SDOperand> &OutOps,
179 switch (ConstraintCode) {
180 default: return true;
187 OutOps.push_back(Op0);
191 // Include the pieces autogenerated from the target description.
192 #include "AlphaGenDAGISel.inc"
195 SDOperand getGlobalBaseReg();
196 SDOperand getGlobalRetAddr();
197 void SelectCALL(SDOperand Op);
202 /// getGlobalBaseReg - Output the instructions required to put the
203 /// GOT address into a register.
205 SDOperand AlphaDAGToDAGISel::getGlobalBaseReg() {
207 for(MachineRegisterInfo::livein_iterator ii = RegInfo->livein_begin(),
208 ee = RegInfo->livein_end(); ii != ee; ++ii)
209 if (ii->first == Alpha::R29) {
213 assert(GP && "GOT PTR not in liveins");
214 return CurDAG->getCopyFromReg(CurDAG->getEntryNode(),
218 /// getRASaveReg - Grab the return address
220 SDOperand AlphaDAGToDAGISel::getGlobalRetAddr() {
222 for(MachineRegisterInfo::livein_iterator ii = RegInfo->livein_begin(),
223 ee = RegInfo->livein_end(); ii != ee; ++ii)
224 if (ii->first == Alpha::R26) {
228 assert(RA && "RA PTR not in liveins");
229 return CurDAG->getCopyFromReg(CurDAG->getEntryNode(),
233 /// InstructionSelectBasicBlock - This callback is invoked by
234 /// SelectionDAGISel when it has created a SelectionDAG for us to codegen.
235 void AlphaDAGToDAGISel::InstructionSelectBasicBlock(SelectionDAG &DAG) {
238 // Select target instructions for the DAG.
239 DAG.setRoot(SelectRoot(DAG.getRoot()));
240 DAG.RemoveDeadNodes();
242 // Emit machine code to BB.
243 ScheduleAndEmitDAG(DAG);
246 // Select - Convert the specified operand from a target-independent to a
247 // target-specific node if it hasn't already been changed.
248 SDNode *AlphaDAGToDAGISel::Select(SDOperand Op) {
250 if (N->getOpcode() >= ISD::BUILTIN_OP_END &&
251 N->getOpcode() < AlphaISD::FIRST_NUMBER) {
252 return NULL; // Already selected.
255 switch (N->getOpcode()) {
261 case ISD::FrameIndex: {
262 int FI = cast<FrameIndexSDNode>(N)->getIndex();
263 return CurDAG->SelectNodeTo(N, Alpha::LDA, MVT::i64,
264 CurDAG->getTargetFrameIndex(FI, MVT::i32),
267 case ISD::GLOBAL_OFFSET_TABLE: {
268 SDOperand Result = getGlobalBaseReg();
269 ReplaceUses(Op, Result);
272 case AlphaISD::GlobalRetAddr: {
273 SDOperand Result = getGlobalRetAddr();
274 ReplaceUses(Op, Result);
278 case AlphaISD::DivCall: {
279 SDOperand Chain = CurDAG->getEntryNode();
280 SDOperand N0 = Op.getOperand(0);
281 SDOperand N1 = Op.getOperand(1);
282 SDOperand N2 = Op.getOperand(2);
286 Chain = CurDAG->getCopyToReg(Chain, Alpha::R24, N1,
288 Chain = CurDAG->getCopyToReg(Chain, Alpha::R25, N2,
290 Chain = CurDAG->getCopyToReg(Chain, Alpha::R27, N0,
293 CurDAG->getTargetNode(Alpha::JSRs, MVT::Other, MVT::Flag,
294 Chain, Chain.getValue(1));
295 Chain = CurDAG->getCopyFromReg(Chain, Alpha::R27, MVT::i64,
296 SDOperand(CNode, 1));
297 return CurDAG->SelectNodeTo(N, Alpha::BISr, MVT::i64, Chain, Chain);
300 case ISD::READCYCLECOUNTER: {
301 SDOperand Chain = N->getOperand(0);
302 AddToISelQueue(Chain); //Select chain
303 return CurDAG->getTargetNode(Alpha::RPCC, MVT::i64, MVT::Other,
307 case ISD::Constant: {
308 uint64_t uval = cast<ConstantSDNode>(N)->getValue();
311 SDOperand Result = CurDAG->getCopyFromReg(CurDAG->getEntryNode(),
312 Alpha::R31, MVT::i64);
313 ReplaceUses(Op, Result);
317 int64_t val = (int64_t)uval;
318 int32_t val32 = (int32_t)val;
319 if (val <= IMM_HIGH + IMM_HIGH * IMM_MULT &&
320 val >= IMM_LOW + IMM_LOW * IMM_MULT)
321 break; //(LDAH (LDA))
322 if ((uval >> 32) == 0 && //empty upper bits
323 val32 <= IMM_HIGH + IMM_HIGH * IMM_MULT)
324 // val32 >= IMM_LOW + IMM_LOW * IMM_MULT) //always true
325 break; //(zext (LDAH (LDA)))
326 //Else use the constant pool
327 ConstantInt *C = ConstantInt::get(Type::Int64Ty, uval);
328 SDOperand CPI = CurDAG->getTargetConstantPool(C, MVT::i64);
329 SDNode *Tmp = CurDAG->getTargetNode(Alpha::LDAHr, MVT::i64, CPI,
331 return CurDAG->SelectNodeTo(N, Alpha::LDQr, MVT::i64, MVT::Other,
332 CPI, SDOperand(Tmp, 0), CurDAG->getEntryNode());
334 case ISD::TargetConstantFP: {
335 ConstantFPSDNode *CN = cast<ConstantFPSDNode>(N);
336 bool isDouble = N->getValueType(0) == MVT::f64;
337 MVT T = isDouble ? MVT::f64 : MVT::f32;
338 if (CN->getValueAPF().isPosZero()) {
339 return CurDAG->SelectNodeTo(N, isDouble ? Alpha::CPYST : Alpha::CPYSS,
340 T, CurDAG->getRegister(Alpha::F31, T),
341 CurDAG->getRegister(Alpha::F31, T));
342 } else if (CN->getValueAPF().isNegZero()) {
343 return CurDAG->SelectNodeTo(N, isDouble ? Alpha::CPYSNT : Alpha::CPYSNS,
344 T, CurDAG->getRegister(Alpha::F31, T),
345 CurDAG->getRegister(Alpha::F31, T));
353 if (N->getOperand(0).Val->getValueType(0).isFloatingPoint()) {
354 ISD::CondCode CC = cast<CondCodeSDNode>(N->getOperand(2))->get();
356 unsigned Opc = Alpha::WTF;
360 default: DEBUG(N->dump(CurDAG)); assert(0 && "Unknown FP comparison!");
361 case ISD::SETEQ: case ISD::SETOEQ: case ISD::SETUEQ:
362 Opc = Alpha::CMPTEQ; break;
363 case ISD::SETLT: case ISD::SETOLT: case ISD::SETULT:
364 Opc = Alpha::CMPTLT; break;
365 case ISD::SETLE: case ISD::SETOLE: case ISD::SETULE:
366 Opc = Alpha::CMPTLE; break;
367 case ISD::SETGT: case ISD::SETOGT: case ISD::SETUGT:
368 Opc = Alpha::CMPTLT; rev = true; break;
369 case ISD::SETGE: case ISD::SETOGE: case ISD::SETUGE:
370 Opc = Alpha::CMPTLE; rev = true; break;
371 case ISD::SETNE: case ISD::SETONE: case ISD::SETUNE:
372 Opc = Alpha::CMPTEQ; inv = true; break;
374 Opc = Alpha::CMPTUN; inv = true; break;
376 Opc = Alpha::CMPTUN; break;
378 SDOperand tmp1 = N->getOperand(rev?1:0);
379 SDOperand tmp2 = N->getOperand(rev?0:1);
380 AddToISelQueue(tmp1);
381 AddToISelQueue(tmp2);
382 SDNode *cmp = CurDAG->getTargetNode(Opc, MVT::f64, tmp1, tmp2);
384 cmp = CurDAG->getTargetNode(Alpha::CMPTEQ, MVT::f64, SDOperand(cmp, 0),
385 CurDAG->getRegister(Alpha::F31, MVT::f64));
387 case ISD::SETUEQ: case ISD::SETULT: case ISD::SETULE:
388 case ISD::SETUNE: case ISD::SETUGT: case ISD::SETUGE:
390 SDNode* cmp2 = CurDAG->getTargetNode(Alpha::CMPTUN, MVT::f64,
392 cmp = CurDAG->getTargetNode(Alpha::ADDT, MVT::f64,
393 SDOperand(cmp2, 0), SDOperand(cmp, 0));
399 SDNode* LD = CurDAG->getTargetNode(Alpha::FTOIT, MVT::i64, SDOperand(cmp, 0));
400 return CurDAG->getTargetNode(Alpha::CMPULT, MVT::i64,
401 CurDAG->getRegister(Alpha::R31, MVT::i64),
407 if (N->getValueType(0).isFloatingPoint() &&
408 (N->getOperand(0).getOpcode() != ISD::SETCC ||
409 !N->getOperand(0).getOperand(1).getValueType().isFloatingPoint())) {
410 //This should be the condition not covered by the Patterns
411 //FIXME: Don't have SelectCode die, but rather return something testable
412 // so that things like this can be caught in fall though code
414 bool isDouble = N->getValueType(0) == MVT::f64;
415 SDOperand cond = N->getOperand(0);
416 SDOperand TV = N->getOperand(1);
417 SDOperand FV = N->getOperand(2);
418 AddToISelQueue(cond);
422 SDNode* LD = CurDAG->getTargetNode(Alpha::ITOFT, MVT::f64, cond);
423 return CurDAG->getTargetNode(isDouble?Alpha::FCMOVNET:Alpha::FCMOVNES,
424 MVT::f64, FV, TV, SDOperand(LD,0));
429 ConstantSDNode* SC = NULL;
430 ConstantSDNode* MC = NULL;
431 if (N->getOperand(0).getOpcode() == ISD::SRL &&
432 (MC = dyn_cast<ConstantSDNode>(N->getOperand(1))) &&
433 (SC = dyn_cast<ConstantSDNode>(N->getOperand(0).getOperand(1)))) {
434 uint64_t sval = SC->getValue();
435 uint64_t mval = MC->getValue();
436 // If the result is a zap, let the autogened stuff handle it.
437 if (get_zapImm(N->getOperand(0), mval))
439 // given mask X, and shift S, we want to see if there is any zap in the
440 // mask if we play around with the botton S bits
441 uint64_t dontcare = (~0ULL) >> (64 - sval);
442 uint64_t mask = mval << sval;
444 if (get_zapImm(mask | dontcare))
445 mask = mask | dontcare;
447 if (get_zapImm(mask)) {
448 AddToISelQueue(N->getOperand(0).getOperand(0));
450 SDOperand(CurDAG->getTargetNode(Alpha::ZAPNOTi, MVT::i64,
451 N->getOperand(0).getOperand(0),
452 getI64Imm(get_zapImm(mask))), 0);
453 return CurDAG->getTargetNode(Alpha::SRLr, MVT::i64, Z,
462 return SelectCode(Op);
465 void AlphaDAGToDAGISel::SelectCALL(SDOperand Op) {
466 //TODO: add flag stuff to prevent nondeturministic breakage!
469 SDOperand Chain = N->getOperand(0);
470 SDOperand Addr = N->getOperand(1);
471 SDOperand InFlag(0,0); // Null incoming flag value.
472 AddToISelQueue(Chain);
474 std::vector<SDOperand> CallOperands;
475 std::vector<MVT> TypeOperands;
478 for(int i = 2, e = N->getNumOperands(); i < e; ++i) {
479 TypeOperands.push_back(N->getOperand(i).getValueType());
480 AddToISelQueue(N->getOperand(i));
481 CallOperands.push_back(N->getOperand(i));
483 int count = N->getNumOperands() - 2;
485 static const unsigned args_int[] = {Alpha::R16, Alpha::R17, Alpha::R18,
486 Alpha::R19, Alpha::R20, Alpha::R21};
487 static const unsigned args_float[] = {Alpha::F16, Alpha::F17, Alpha::F18,
488 Alpha::F19, Alpha::F20, Alpha::F21};
490 for (int i = 6; i < count; ++i) {
491 unsigned Opc = Alpha::WTF;
492 if (TypeOperands[i].isInteger()) {
494 } else if (TypeOperands[i] == MVT::f32) {
496 } else if (TypeOperands[i] == MVT::f64) {
499 assert(0 && "Unknown operand");
501 SDOperand Ops[] = { CallOperands[i], getI64Imm((i - 6) * 8),
502 CurDAG->getCopyFromReg(Chain, Alpha::R30, MVT::i64),
504 Chain = SDOperand(CurDAG->getTargetNode(Opc, MVT::Other, Ops, 4), 0);
506 for (int i = 0; i < std::min(6, count); ++i) {
507 if (TypeOperands[i].isInteger()) {
508 Chain = CurDAG->getCopyToReg(Chain, args_int[i], CallOperands[i], InFlag);
509 InFlag = Chain.getValue(1);
510 } else if (TypeOperands[i] == MVT::f32 || TypeOperands[i] == MVT::f64) {
511 Chain = CurDAG->getCopyToReg(Chain, args_float[i], CallOperands[i], InFlag);
512 InFlag = Chain.getValue(1);
514 assert(0 && "Unknown operand");
517 // Finally, once everything is in registers to pass to the call, emit the
519 if (Addr.getOpcode() == AlphaISD::GPRelLo) {
520 SDOperand GOT = getGlobalBaseReg();
521 Chain = CurDAG->getCopyToReg(Chain, Alpha::R29, GOT, InFlag);
522 InFlag = Chain.getValue(1);
523 Chain = SDOperand(CurDAG->getTargetNode(Alpha::BSR, MVT::Other, MVT::Flag,
524 Addr.getOperand(0), Chain, InFlag), 0);
526 AddToISelQueue(Addr);
527 Chain = CurDAG->getCopyToReg(Chain, Alpha::R27, Addr, InFlag);
528 InFlag = Chain.getValue(1);
529 Chain = SDOperand(CurDAG->getTargetNode(Alpha::JSR, MVT::Other, MVT::Flag,
532 InFlag = Chain.getValue(1);
534 std::vector<SDOperand> CallResults;
536 switch (N->getValueType(0).getSimpleVT()) {
537 default: assert(0 && "Unexpected ret value!");
538 case MVT::Other: break;
540 Chain = CurDAG->getCopyFromReg(Chain, Alpha::R0, MVT::i64, InFlag).getValue(1);
541 CallResults.push_back(Chain.getValue(0));
544 Chain = CurDAG->getCopyFromReg(Chain, Alpha::F0, MVT::f32, InFlag).getValue(1);
545 CallResults.push_back(Chain.getValue(0));
548 Chain = CurDAG->getCopyFromReg(Chain, Alpha::F0, MVT::f64, InFlag).getValue(1);
549 CallResults.push_back(Chain.getValue(0));
553 CallResults.push_back(Chain);
554 for (unsigned i = 0, e = CallResults.size(); i != e; ++i)
555 ReplaceUses(Op.getValue(i), CallResults[i]);
559 /// createAlphaISelDag - This pass converts a legalized DAG into a
560 /// Alpha-specific DAG, ready for instruction scheduling.
562 FunctionPass *llvm::createAlphaISelDag(AlphaTargetMachine &TM) {
563 return new AlphaDAGToDAGISel(TM);