1 //===-- AlphaISelDAGToDAG.cpp - Alpha pattern matching inst selector ------===//
3 // The LLVM Compiler Infrastructure
5 // This file was developed by Andrew Lenharth and is distributed under
6 // the University of Illinois Open Source License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines a pattern matching instruction selector for Alpha,
11 // converting from a legalized dag to a Alpha dag.
13 //===----------------------------------------------------------------------===//
16 #include "AlphaTargetMachine.h"
17 #include "AlphaISelLowering.h"
18 #include "llvm/CodeGen/MachineInstrBuilder.h"
19 #include "llvm/CodeGen/MachineFrameInfo.h"
20 #include "llvm/CodeGen/MachineFunction.h"
21 #include "llvm/CodeGen/SSARegMap.h"
22 #include "llvm/CodeGen/SelectionDAG.h"
23 #include "llvm/CodeGen/SelectionDAGISel.h"
24 #include "llvm/Target/TargetOptions.h"
25 #include "llvm/ADT/Statistic.h"
26 #include "llvm/Constants.h"
27 #include "llvm/GlobalValue.h"
28 #include "llvm/Support/Debug.h"
29 #include "llvm/Support/MathExtras.h"
35 //===--------------------------------------------------------------------===//
36 /// AlphaDAGToDAGISel - Alpha specific code to select Alpha machine
37 /// instructions for SelectionDAG operations.
38 class AlphaDAGToDAGISel : public SelectionDAGISel {
39 AlphaTargetLowering AlphaLowering;
41 static const int64_t IMM_LOW = -32768;
42 static const int64_t IMM_HIGH = 32767;
43 static const int64_t IMM_MULT = 65536;
46 AlphaDAGToDAGISel(TargetMachine &TM)
47 : SelectionDAGISel(AlphaLowering), AlphaLowering(TM)
50 /// getI64Imm - Return a target constant with the specified value, of type
52 inline SDOperand getI64Imm(int64_t Imm) {
53 return CurDAG->getTargetConstant(Imm, MVT::i64);
56 // Select - Convert the specified operand from a target-independent to a
57 // target-specific node if it hasn't already been changed.
58 SDOperand Select(SDOperand Op);
60 /// InstructionSelectBasicBlock - This callback is invoked by
61 /// SelectionDAGISel when it has created a SelectionDAG for us to codegen.
62 virtual void InstructionSelectBasicBlock(SelectionDAG &DAG);
64 virtual const char *getPassName() const {
65 return "Alpha DAG->DAG Pattern Instruction Selection";
68 // Include the pieces autogenerated from the target description.
69 #include "AlphaGenDAGISel.inc"
72 SDOperand getGlobalBaseReg();
73 SDOperand getRASaveReg();
74 SDOperand SelectCALL(SDOperand Op);
79 /// getGlobalBaseReg - Output the instructions required to put the
80 /// GOT address into a register.
82 SDOperand AlphaDAGToDAGISel::getGlobalBaseReg() {
83 return CurDAG->getCopyFromReg(CurDAG->getEntryNode(),
84 AlphaLowering.getVRegGP(),
88 /// getRASaveReg - Grab the return address
90 SDOperand AlphaDAGToDAGISel::getRASaveReg() {
91 return CurDAG->getCopyFromReg(CurDAG->getEntryNode(),
92 AlphaLowering.getVRegRA(),
96 /// InstructionSelectBasicBlock - This callback is invoked by
97 /// SelectionDAGISel when it has created a SelectionDAG for us to codegen.
98 void AlphaDAGToDAGISel::InstructionSelectBasicBlock(SelectionDAG &DAG) {
101 // Select target instructions for the DAG.
102 DAG.setRoot(Select(DAG.getRoot()));
104 DAG.RemoveDeadNodes();
106 // Emit machine code to BB.
107 ScheduleAndEmitDAG(DAG);
110 // Select - Convert the specified operand from a target-independent to a
111 // target-specific node if it hasn't already been changed.
112 SDOperand AlphaDAGToDAGISel::Select(SDOperand Op) {
114 if (N->getOpcode() >= ISD::BUILTIN_OP_END &&
115 N->getOpcode() < AlphaISD::FIRST_NUMBER)
116 return Op; // Already selected.
118 // If this has already been converted, use it.
119 std::map<SDOperand, SDOperand>::iterator CGMI = CodeGenMap.find(Op);
120 if (CGMI != CodeGenMap.end()) return CGMI->second;
122 switch (N->getOpcode()) {
125 case ISD::CALL: return SelectCALL(Op);
127 case ISD::DYNAMIC_STACKALLOC: {
128 if (!isa<ConstantSDNode>(N->getOperand(2)) ||
129 cast<ConstantSDNode>(N->getOperand(2))->getValue() != 0) {
130 std::cerr << "Cannot allocate stack object with greater alignment than"
131 << " the stack alignment yet!";
135 SDOperand Chain = Select(N->getOperand(0));
136 SDOperand Amt = Select(N->getOperand(1));
137 SDOperand Reg = CurDAG->getRegister(Alpha::R30, MVT::i64);
138 SDOperand Val = CurDAG->getCopyFromReg(Chain, Alpha::R30, MVT::i64);
139 Chain = Val.getValue(1);
141 // Subtract the amount (guaranteed to be a multiple of the stack alignment)
142 // from the stack pointer, giving us the result pointer.
143 SDOperand Result = CurDAG->getTargetNode(Alpha::SUBQ, MVT::i64, Val, Amt);
145 // Copy this result back into R30.
146 Chain = CurDAG->getNode(ISD::CopyToReg, MVT::Other, Chain, Reg, Result);
148 // Copy this result back out of R30 to make sure we're not using the stack
149 // space without decrementing the stack pointer.
150 Result = CurDAG->getCopyFromReg(Chain, Alpha::R30, MVT::i64);
152 // Finally, replace the DYNAMIC_STACKALLOC with the copyfromreg.
153 CodeGenMap[Op.getValue(0)] = Result;
154 CodeGenMap[Op.getValue(1)] = Result.getValue(1);
155 return SDOperand(Result.Val, Op.ResNo);
158 if (N->getOperand(1).getOpcode() == ISD::SETCC &&
159 MVT::isFloatingPoint(N->getOperand(1).getOperand(0).getValueType())) {
160 SDOperand Chain = Select(N->getOperand(0));
161 SDOperand CC1 = Select(N->getOperand(1).getOperand(0));
162 SDOperand CC2 = Select(N->getOperand(1).getOperand(1));
163 ISD::CondCode cCode= cast<CondCodeSDNode>(N->getOperand(1).getOperand(2))->get();
167 unsigned Opc = Alpha::WTF;
169 default: N->dump(); assert(0 && "Unknown FP comparison!");
170 case ISD::SETEQ: Opc = Alpha::CMPTEQ; break;
171 case ISD::SETLT: Opc = Alpha::CMPTLT; break;
172 case ISD::SETLE: Opc = Alpha::CMPTLE; break;
173 case ISD::SETGT: Opc = Alpha::CMPTLT; rev = true; break;
174 case ISD::SETGE: Opc = Alpha::CMPTLE; rev = true; break;
175 case ISD::SETNE: Opc = Alpha::CMPTEQ; isNE = true; break;
177 SDOperand cmp = CurDAG->getTargetNode(Opc, MVT::f64,
181 MachineBasicBlock *Dest =
182 cast<BasicBlockSDNode>(N->getOperand(2))->getBasicBlock();
184 return CurDAG->SelectNodeTo(N, Alpha::FBEQ, MVT::Other, cmp,
185 CurDAG->getBasicBlock(Dest), Chain);
187 return CurDAG->SelectNodeTo(N, Alpha::FBNE, MVT::Other, cmp,
188 CurDAG->getBasicBlock(Dest), Chain);
190 SDOperand Chain = Select(N->getOperand(0));
191 SDOperand CC = Select(N->getOperand(1));
192 MachineBasicBlock *Dest =
193 cast<BasicBlockSDNode>(N->getOperand(2))->getBasicBlock();
194 return CurDAG->SelectNodeTo(N, Alpha::BNE, MVT::Other, CC,
195 CurDAG->getBasicBlock(Dest), Chain);
198 case ISD::FrameIndex: {
199 int FI = cast<FrameIndexSDNode>(N)->getIndex();
200 return CurDAG->SelectNodeTo(N, Alpha::LDA, MVT::i64,
201 CurDAG->getTargetFrameIndex(FI, MVT::i32),
204 case AlphaISD::GlobalBaseReg:
205 return getGlobalBaseReg();
207 case AlphaISD::DivCall: {
208 SDOperand Chain = CurDAG->getEntryNode();
209 Chain = CurDAG->getCopyToReg(Chain, Alpha::R24, Select(Op.getOperand(1)),
211 Chain = CurDAG->getCopyToReg(Chain, Alpha::R25, Select(Op.getOperand(2)),
213 Chain = CurDAG->getCopyToReg(Chain, Alpha::R27, Select(Op.getOperand(0)),
215 Chain = CurDAG->getTargetNode(Alpha::JSRs, MVT::Other, MVT::Flag,
216 Chain, Chain.getValue(1));
217 Chain = CurDAG->getCopyFromReg(Chain, Alpha::R27, MVT::i64,
219 return CurDAG->SelectNodeTo(N, Alpha::BIS, MVT::i64, Chain, Chain);
223 SDOperand Chain = Select(N->getOperand(0)); // Token chain.
226 if (N->getNumOperands() == 2) {
227 SDOperand Val = Select(N->getOperand(1));
228 if (N->getOperand(1).getValueType() == MVT::i64) {
229 Chain = CurDAG->getCopyToReg(Chain, Alpha::R0, Val, InFlag);
230 InFlag = Chain.getValue(1);
231 } else if (N->getOperand(1).getValueType() == MVT::f64 ||
232 N->getOperand(1).getValueType() == MVT::f32) {
233 Chain = CurDAG->getCopyToReg(Chain, Alpha::F0, Val, InFlag);
234 InFlag = Chain.getValue(1);
237 Chain = CurDAG->getCopyToReg(Chain, Alpha::R26, getRASaveReg(), InFlag);
238 InFlag = Chain.getValue(1);
240 // Finally, select this to a ret instruction.
241 return CurDAG->SelectNodeTo(N, Alpha::RETDAG, MVT::Other, Chain, InFlag);
243 case ISD::Constant: {
244 uint64_t uval = cast<ConstantSDNode>(N)->getValue();
245 int64_t val = (int64_t)uval;
246 int32_t val32 = (int32_t)val;
247 if (val <= IMM_HIGH + IMM_HIGH * IMM_MULT &&
248 val >= IMM_LOW + IMM_LOW * IMM_MULT)
249 break; //(LDAH (LDA))
250 if ((uval >> 32) == 0 && //empty upper bits
251 val32 <= IMM_HIGH + IMM_HIGH * IMM_MULT &&
252 val32 >= IMM_LOW + IMM_LOW * IMM_MULT)
253 break; //(zext (LDAH (LDA)))
254 //Else use the constant pool
255 MachineConstantPool *CP = BB->getParent()->getConstantPool();
257 ConstantUInt::get(Type::getPrimitiveType(Type::ULongTyID) , uval);
258 SDOperand Tmp, CPI = CurDAG->getTargetConstantPool(C, MVT::i64);
259 Tmp = CurDAG->getTargetNode(Alpha::LDAHr, MVT::i64, CPI, getGlobalBaseReg());
260 return CurDAG->SelectNodeTo(N, Alpha::LDQr, MVT::i64, MVT::Other,
261 CPI, Tmp, CurDAG->getEntryNode());
263 case ISD::ConstantFP:
264 if (ConstantFPSDNode *CN = dyn_cast<ConstantFPSDNode>(N)) {
265 bool isDouble = N->getValueType(0) == MVT::f64;
266 MVT::ValueType T = isDouble ? MVT::f64 : MVT::f32;
267 if (CN->isExactlyValue(+0.0)) {
268 return CurDAG->SelectNodeTo(N, isDouble ? Alpha::CPYST : Alpha::CPYSS,
269 T, CurDAG->getRegister(Alpha::F31, T),
270 CurDAG->getRegister(Alpha::F31, T));
271 } else if ( CN->isExactlyValue(-0.0)) {
272 return CurDAG->SelectNodeTo(N, isDouble ? Alpha::CPYSNT : Alpha::CPYSNS,
273 T, CurDAG->getRegister(Alpha::F31, T),
274 CurDAG->getRegister(Alpha::F31, T));
282 if (MVT::isFloatingPoint(N->getOperand(0).Val->getValueType(0))) {
283 unsigned Opc = Alpha::WTF;
284 ISD::CondCode CC = cast<CondCodeSDNode>(N->getOperand(2))->get();
288 default: N->dump(); assert(0 && "Unknown FP comparison!");
289 case ISD::SETEQ: Opc = Alpha::CMPTEQ; break;
290 case ISD::SETLT: Opc = Alpha::CMPTLT; break;
291 case ISD::SETLE: Opc = Alpha::CMPTLE; break;
292 case ISD::SETGT: Opc = Alpha::CMPTLT; rev = true; break;
293 case ISD::SETGE: Opc = Alpha::CMPTLE; rev = true; break;
294 case ISD::SETNE: Opc = Alpha::CMPTEQ; isNE = true; break;
296 SDOperand tmp1 = Select(N->getOperand(0)),
297 tmp2 = Select(N->getOperand(1));
298 SDOperand cmp = CurDAG->getTargetNode(Opc, MVT::f64,
302 cmp = CurDAG->getTargetNode(Alpha::CMPTEQ, MVT::f64, cmp,
303 CurDAG->getRegister(Alpha::F31, MVT::f64));
306 if (AlphaLowering.hasITOF()) {
307 LD = CurDAG->getNode(AlphaISD::FTOIT_, MVT::i64, cmp);
310 CurDAG->getMachineFunction().getFrameInfo()->CreateStackObject(8, 8);
311 SDOperand FI = CurDAG->getFrameIndex(FrameIdx, MVT::i64);
312 SDOperand ST = CurDAG->getTargetNode(Alpha::STT, MVT::Other,
313 cmp, FI, CurDAG->getRegister(Alpha::R31, MVT::i64));
314 LD = CurDAG->getTargetNode(Alpha::LDQ, MVT::i64, FI,
315 CurDAG->getRegister(Alpha::R31, MVT::i64),
318 SDOperand FP = CurDAG->getTargetNode(Alpha::CMPULT, MVT::i64,
319 CurDAG->getRegister(Alpha::R31, MVT::i64),
326 if (MVT::isFloatingPoint(N->getValueType(0)) &&
327 (N->getOperand(0).getOpcode() != ISD::SETCC ||
328 !MVT::isFloatingPoint(N->getOperand(0).getOperand(1).getValueType()))) {
329 //This should be the condition not covered by the Patterns
330 //FIXME: Don't have SelectCode die, but rather return something testable
331 // so that things like this can be caught in fall though code
333 bool isDouble = N->getValueType(0) == MVT::f64;
335 cond = Select(N->getOperand(0)),
336 TV = Select(N->getOperand(1)),
337 FV = Select(N->getOperand(2));
339 if (AlphaLowering.hasITOF()) {
340 LD = CurDAG->getNode(AlphaISD::ITOFT_, MVT::f64, cond);
343 CurDAG->getMachineFunction().getFrameInfo()->CreateStackObject(8, 8);
344 SDOperand FI = CurDAG->getFrameIndex(FrameIdx, MVT::i64);
345 SDOperand ST = CurDAG->getTargetNode(Alpha::STQ, MVT::Other,
346 cond, FI, CurDAG->getRegister(Alpha::R31, MVT::i64));
347 LD = CurDAG->getTargetNode(Alpha::LDT, MVT::f64, FI,
348 CurDAG->getRegister(Alpha::R31, MVT::i64),
351 SDOperand FP = CurDAG->getTargetNode(isDouble?Alpha::FCMOVNET:Alpha::FCMOVNES,
352 MVT::f64, FV, TV, LD);
359 return SelectCode(Op);
362 SDOperand AlphaDAGToDAGISel::SelectCALL(SDOperand Op) {
363 //TODO: add flag stuff to prevent nondeturministic breakage!
366 SDOperand Chain = Select(N->getOperand(0));
367 SDOperand Addr = N->getOperand(1);
368 SDOperand InFlag; // Null incoming flag value.
370 std::vector<SDOperand> CallOperands;
371 std::vector<MVT::ValueType> TypeOperands;
374 for(int i = 2, e = N->getNumOperands(); i < e; ++i) {
375 TypeOperands.push_back(N->getOperand(i).getValueType());
376 CallOperands.push_back(Select(N->getOperand(i)));
378 int count = N->getNumOperands() - 2;
380 static const unsigned args_int[] = {Alpha::R16, Alpha::R17, Alpha::R18,
381 Alpha::R19, Alpha::R20, Alpha::R21};
382 static const unsigned args_float[] = {Alpha::F16, Alpha::F17, Alpha::F18,
383 Alpha::F19, Alpha::F20, Alpha::F21};
385 for (int i = 6; i < count; ++i) {
386 unsigned Opc = Alpha::WTF;
387 if (MVT::isInteger(TypeOperands[i])) {
389 } else if (TypeOperands[i] == MVT::f32) {
391 } else if (TypeOperands[i] == MVT::f64) {
394 assert(0 && "Unknown operand");
395 Chain = CurDAG->getTargetNode(Opc, MVT::Other, CallOperands[i],
396 getI64Imm((i - 6) * 8),
397 CurDAG->getCopyFromReg(Chain, Alpha::R30, MVT::i64),
400 for (int i = 0; i < std::min(6, count); ++i) {
401 if (MVT::isInteger(TypeOperands[i])) {
402 Chain = CurDAG->getCopyToReg(Chain, args_int[i], CallOperands[i], InFlag);
403 InFlag = Chain.getValue(1);
404 } else if (TypeOperands[i] == MVT::f32 || TypeOperands[i] == MVT::f64) {
405 Chain = CurDAG->getCopyToReg(Chain, args_float[i], CallOperands[i], InFlag);
406 InFlag = Chain.getValue(1);
408 assert(0 && "Unknown operand");
412 // Finally, once everything is in registers to pass to the call, emit the
414 if (Addr.getOpcode() == AlphaISD::GPRelLo) {
415 SDOperand GOT = getGlobalBaseReg();
416 Chain = CurDAG->getCopyToReg(Chain, Alpha::R29, GOT, InFlag);
417 InFlag = Chain.getValue(1);
418 Chain = CurDAG->getTargetNode(Alpha::BSR, MVT::Other, MVT::Flag,
419 Addr.getOperand(0), Chain, InFlag);
421 Chain = CurDAG->getCopyToReg(Chain, Alpha::R27, Select(Addr), InFlag);
422 InFlag = Chain.getValue(1);
423 Chain = CurDAG->getTargetNode(Alpha::JSR, MVT::Other, MVT::Flag,
426 InFlag = Chain.getValue(1);
428 std::vector<SDOperand> CallResults;
430 switch (N->getValueType(0)) {
431 default: assert(0 && "Unexpected ret value!");
432 case MVT::Other: break;
434 Chain = CurDAG->getCopyFromReg(Chain, Alpha::R0, MVT::i64, InFlag).getValue(1);
435 CallResults.push_back(Chain.getValue(0));
438 Chain = CurDAG->getCopyFromReg(Chain, Alpha::F0, MVT::f32, InFlag).getValue(1);
439 CallResults.push_back(Chain.getValue(0));
442 Chain = CurDAG->getCopyFromReg(Chain, Alpha::F0, MVT::f64, InFlag).getValue(1);
443 CallResults.push_back(Chain.getValue(0));
447 CallResults.push_back(Chain);
448 for (unsigned i = 0, e = CallResults.size(); i != e; ++i)
449 CodeGenMap[Op.getValue(i)] = CallResults[i];
450 return CallResults[Op.ResNo];
454 /// createAlphaISelDag - This pass converts a legalized DAG into a
455 /// Alpha-specific DAG, ready for instruction scheduling.
457 FunctionPass *llvm::createAlphaISelDag(TargetMachine &TM) {
458 return new AlphaDAGToDAGISel(TM);