1 //===-- AlphaISelDAGToDAG.cpp - Alpha pattern matching inst selector ------===//
3 // The LLVM Compiler Infrastructure
5 // This file was developed by Andrew Lenharth and is distributed under
6 // the University of Illinois Open Source License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines a pattern matching instruction selector for Alpha,
11 // converting from a legalized dag to a Alpha dag.
13 //===----------------------------------------------------------------------===//
16 #include "AlphaTargetMachine.h"
17 #include "AlphaISelLowering.h"
18 #include "llvm/CodeGen/MachineInstrBuilder.h"
19 #include "llvm/CodeGen/MachineFrameInfo.h"
20 #include "llvm/CodeGen/MachineFunction.h"
21 #include "llvm/CodeGen/SSARegMap.h"
22 #include "llvm/CodeGen/SelectionDAG.h"
23 #include "llvm/CodeGen/SelectionDAGISel.h"
24 #include "llvm/Target/TargetOptions.h"
25 #include "llvm/ADT/Statistic.h"
26 #include "llvm/Constants.h"
27 #include "llvm/GlobalValue.h"
28 #include "llvm/Support/Debug.h"
29 #include "llvm/Support/MathExtras.h"
35 //===--------------------------------------------------------------------===//
36 /// AlphaDAGToDAGISel - Alpha specific code to select Alpha machine
37 /// instructions for SelectionDAG operations.
39 class AlphaDAGToDAGISel : public SelectionDAGISel {
40 AlphaTargetLowering AlphaLowering;
42 static const int IMM_LOW = -32768;
43 static const int IMM_HIGH = 32767;
44 static const int IMM_MULT = 65536;
47 AlphaDAGToDAGISel(TargetMachine &TM)
48 : SelectionDAGISel(AlphaLowering), AlphaLowering(TM) {}
50 /// getI64Imm - Return a target constant with the specified value, of type
52 inline SDOperand getI64Imm(int64_t Imm) {
53 return CurDAG->getTargetConstant(Imm, MVT::i64);
56 // Select - Convert the specified operand from a target-independent to a
57 // target-specific node if it hasn't already been changed.
58 SDOperand Select(SDOperand Op);
60 /// InstructionSelectBasicBlock - This callback is invoked by
61 /// SelectionDAGISel when it has created a SelectionDAG for us to codegen.
62 virtual void InstructionSelectBasicBlock(SelectionDAG &DAG);
64 virtual const char *getPassName() const {
65 return "Alpha DAG->DAG Pattern Instruction Selection";
68 // Include the pieces autogenerated from the target description.
69 #include "AlphaGenDAGISel.inc"
72 SDOperand getGlobalBaseReg();
73 SDOperand getRASaveReg();
74 SDOperand SelectCALL(SDOperand Op);
79 /// getGlobalBaseReg - Output the instructions required to put the
80 /// GOT address into a register.
82 SDOperand AlphaDAGToDAGISel::getGlobalBaseReg() {
83 return CurDAG->getCopyFromReg(CurDAG->getEntryNode(),
84 AlphaLowering.getVRegGP(),
88 /// getRASaveReg - Grab the return address
90 SDOperand AlphaDAGToDAGISel::getRASaveReg() {
91 return CurDAG->getCopyFromReg(CurDAG->getEntryNode(),
92 AlphaLowering.getVRegRA(),
96 /// InstructionSelectBasicBlock - This callback is invoked by
97 /// SelectionDAGISel when it has created a SelectionDAG for us to codegen.
98 void AlphaDAGToDAGISel::InstructionSelectBasicBlock(SelectionDAG &DAG) {
101 // Select target instructions for the DAG.
102 DAG.setRoot(Select(DAG.getRoot()));
104 DAG.RemoveDeadNodes();
106 // Emit machine code to BB.
107 ScheduleAndEmitDAG(DAG);
110 // Select - Convert the specified operand from a target-independent to a
111 // target-specific node if it hasn't already been changed.
112 SDOperand AlphaDAGToDAGISel::Select(SDOperand Op) {
114 if (N->getOpcode() >= ISD::BUILTIN_OP_END &&
115 N->getOpcode() < AlphaISD::FIRST_NUMBER)
116 return Op; // Already selected.
118 // If this has already been converted, use it.
119 std::map<SDOperand, SDOperand>::iterator CGMI = CodeGenMap.find(Op);
120 if (CGMI != CodeGenMap.end()) return CGMI->second;
122 switch (N->getOpcode()) {
125 case ISD::CALL: return SelectCALL(Op);
127 case ISD::DYNAMIC_STACKALLOC: {
128 if (!isa<ConstantSDNode>(N->getOperand(2)) ||
129 cast<ConstantSDNode>(N->getOperand(2))->getValue() != 0) {
130 std::cerr << "Cannot allocate stack object with greater alignment than"
131 << " the stack alignment yet!";
135 SDOperand Chain = Select(N->getOperand(0));
136 SDOperand Amt = Select(N->getOperand(1));
137 SDOperand Reg = CurDAG->getRegister(Alpha::R30, MVT::i64);
138 SDOperand Val = CurDAG->getCopyFromReg(Chain, Alpha::R30, MVT::i64);
139 Chain = Val.getValue(1);
141 // Subtract the amount (guaranteed to be a multiple of the stack alignment)
142 // from the stack pointer, giving us the result pointer.
143 SDOperand Result = CurDAG->getTargetNode(Alpha::SUBQ, MVT::i64, Val, Amt);
145 // Copy this result back into R30.
146 Chain = CurDAG->getNode(ISD::CopyToReg, MVT::Other, Chain, Reg, Result);
148 // Copy this result back out of R30 to make sure we're not using the stack
149 // space without decrementing the stack pointer.
150 Result = CurDAG->getCopyFromReg(Chain, Alpha::R30, MVT::i64);
152 // Finally, replace the DYNAMIC_STACKALLOC with the copyfromreg.
153 CodeGenMap[Op.getValue(0)] = Result;
154 CodeGenMap[Op.getValue(1)] = Result.getValue(1);
155 return SDOperand(Result.Val, Op.ResNo);
158 if (N->getOperand(1).getOpcode() == ISD::SETCC &&
159 MVT::isFloatingPoint(N->getOperand(1).getOperand(0).getValueType())) {
160 SDOperand Chain = Select(N->getOperand(0));
161 SDOperand CC1 = Select(N->getOperand(1).getOperand(0));
162 SDOperand CC2 = Select(N->getOperand(1).getOperand(1));
163 ISD::CondCode cCode= cast<CondCodeSDNode>(N->getOperand(1).getOperand(2))->get();
167 unsigned Opc = Alpha::WTF;
169 default: N->dump(); assert(0 && "Unknown FP comparison!");
170 case ISD::SETEQ: Opc = Alpha::CMPTEQ; break;
171 case ISD::SETLT: Opc = Alpha::CMPTLT; break;
172 case ISD::SETLE: Opc = Alpha::CMPTLE; break;
173 case ISD::SETGT: Opc = Alpha::CMPTLT; rev = true; break;
174 case ISD::SETGE: Opc = Alpha::CMPTLE; rev = true; break;
175 case ISD::SETNE: Opc = Alpha::CMPTEQ; isNE = true; break;
177 SDOperand cmp = CurDAG->getTargetNode(Opc, MVT::f64,
181 MachineBasicBlock *Dest =
182 cast<BasicBlockSDNode>(N->getOperand(2))->getBasicBlock();
184 return CurDAG->SelectNodeTo(N, Alpha::FBEQ, MVT::Other, cmp,
185 CurDAG->getBasicBlock(Dest), Chain);
187 return CurDAG->SelectNodeTo(N, Alpha::FBNE, MVT::Other, cmp,
188 CurDAG->getBasicBlock(Dest), Chain);
190 SDOperand Chain = Select(N->getOperand(0));
191 SDOperand CC = Select(N->getOperand(1));
192 MachineBasicBlock *Dest =
193 cast<BasicBlockSDNode>(N->getOperand(2))->getBasicBlock();
194 return CurDAG->SelectNodeTo(N, Alpha::BNE, MVT::Other, CC,
195 CurDAG->getBasicBlock(Dest), Chain);
200 case ISD::SEXTLOAD: {
201 SDOperand Chain = Select(N->getOperand(0));
202 SDOperand Address = Select(N->getOperand(1));
203 unsigned opcode = N->getOpcode();
204 unsigned Opc = Alpha::WTF;
205 if (opcode == ISD::LOAD)
206 switch (N->getValueType(0)) {
207 default: N->dump(); assert(0 && "Bad load!");
208 case MVT::i64: Opc = Alpha::LDQ; break;
209 case MVT::f64: Opc = Alpha::LDT; break;
210 case MVT::f32: Opc = Alpha::LDS; break;
213 switch (cast<VTSDNode>(N->getOperand(3))->getVT()) {
214 default: N->dump(); assert(0 && "Bad sign extend!");
215 case MVT::i32: Opc = Alpha::LDL;
216 assert(opcode != ISD::ZEXTLOAD && "Not sext"); break;
217 case MVT::i16: Opc = Alpha::LDWU;
218 assert(opcode != ISD::SEXTLOAD && "Not zext"); break;
219 case MVT::i1: //FIXME: Treat i1 as i8 since there are problems otherwise
220 case MVT::i8: Opc = Alpha::LDBU;
221 assert(opcode != ISD::SEXTLOAD && "Not zext"); break;
224 return CurDAG->SelectNodeTo(N, Opc, N->getValueType(0), MVT::Other,
225 getI64Imm(0), Address,
226 Chain).getValue(Op.ResNo);
229 case ISD::TRUNCSTORE: {
230 SDOperand Chain = Select(N->getOperand(0));
231 SDOperand Value = Select(N->getOperand(1));
232 SDOperand Address = Select(N->getOperand(2));
234 unsigned Opc = Alpha::WTF;
236 if (N->getOpcode() == ISD::STORE) {
237 switch (N->getOperand(1).getValueType()) {
238 case MVT::i64: Opc = Alpha::STQ; break;
239 case MVT::f64: Opc = Alpha::STT; break;
240 case MVT::f32: Opc = Alpha::STS; break;
241 default: assert(0 && "Bad store!");
243 } else { //TRUNCSTORE
244 switch (cast<VTSDNode>(N->getOperand(4))->getVT()) {
245 case MVT::i32: Opc = Alpha::STL; break;
246 case MVT::i16: Opc = Alpha::STW; break;
247 case MVT::i8: Opc = Alpha::STB; break;
248 default: assert(0 && "Bad truncstore!");
251 return CurDAG->SelectNodeTo(N, Opc, MVT::Other, Value, getI64Imm(0),
256 return CurDAG->SelectNodeTo(N, Alpha::BR_DAG, MVT::Other, N->getOperand(1),
257 Select(N->getOperand(0)));
258 case ISD::FrameIndex: {
259 int FI = cast<FrameIndexSDNode>(N)->getIndex();
260 return CurDAG->SelectNodeTo(N, Alpha::LDA, MVT::i64,
261 CurDAG->getTargetFrameIndex(FI, MVT::i32),
264 case ISD::ConstantPool: {
265 Constant *C = cast<ConstantPoolSDNode>(N)->get();
266 SDOperand Tmp, CPI = CurDAG->getTargetConstantPool(C, MVT::i64);
267 Tmp = CurDAG->getTargetNode(Alpha::LDAHr, MVT::i64, CPI, getGlobalBaseReg());
268 return CurDAG->SelectNodeTo(N, Alpha::LDAr, MVT::i64, CPI, Tmp);
270 case ISD::GlobalAddress: {
271 GlobalValue *GV = cast<GlobalAddressSDNode>(N)->getGlobal();
272 SDOperand GA = CurDAG->getTargetGlobalAddress(GV, MVT::i64);
273 return CurDAG->SelectNodeTo(N, Alpha::LDQl, MVT::i64, GA,
276 case ISD::ExternalSymbol:
277 return CurDAG->SelectNodeTo(N, Alpha::LDQl, MVT::i64,
278 CurDAG->getTargetExternalSymbol(cast<ExternalSymbolSDNode>(N)->getSymbol(), MVT::i64),
282 SDOperand Chain = Select(N->getOperand(0)); // Token chain.
285 if (N->getNumOperands() == 2) {
286 SDOperand Val = Select(N->getOperand(1));
287 if (N->getOperand(1).getValueType() == MVT::i64) {
288 Chain = CurDAG->getCopyToReg(Chain, Alpha::R0, Val, InFlag);
289 InFlag = Chain.getValue(1);
290 } else if (N->getOperand(1).getValueType() == MVT::f64 ||
291 N->getOperand(1).getValueType() == MVT::f32) {
292 Chain = CurDAG->getCopyToReg(Chain, Alpha::F0, Val, InFlag);
293 InFlag = Chain.getValue(1);
296 Chain = CurDAG->getCopyToReg(Chain, Alpha::R26, getRASaveReg(), InFlag);
297 InFlag = Chain.getValue(1);
299 // Finally, select this to a ret instruction.
300 return CurDAG->SelectNodeTo(N, Alpha::RETDAG, MVT::Other, Chain, InFlag);
302 case ISD::Constant: {
303 int64_t val = (int64_t)cast<ConstantSDNode>(N)->getValue();
304 if (val > (int64_t)IMM_HIGH +(int64_t)IMM_HIGH* (int64_t)IMM_MULT ||
305 val < (int64_t)IMM_LOW + (int64_t)IMM_LOW * (int64_t)IMM_MULT) {
306 MachineConstantPool *CP = BB->getParent()->getConstantPool();
308 ConstantUInt::get(Type::getPrimitiveType(Type::ULongTyID) , val);
309 SDOperand Tmp, CPI = CurDAG->getTargetConstantPool(C, MVT::i64);
310 Tmp = CurDAG->getTargetNode(Alpha::LDAHr, MVT::i64, CPI, getGlobalBaseReg());
311 return CurDAG->SelectNodeTo(N, Alpha::LDQr, MVT::i64, CPI, Tmp);
315 case ISD::ConstantFP:
316 if (ConstantFPSDNode *CN = dyn_cast<ConstantFPSDNode>(N)) {
317 bool isDouble = N->getValueType(0) == MVT::f64;
318 MVT::ValueType T = isDouble ? MVT::f64 : MVT::f32;
319 if (CN->isExactlyValue(+0.0)) {
320 return CurDAG->SelectNodeTo(N, isDouble ? Alpha::CPYST : Alpha::CPYSS,
321 T, CurDAG->getRegister(Alpha::F31, T),
322 CurDAG->getRegister(Alpha::F31, T));
323 } else if ( CN->isExactlyValue(-0.0)) {
324 return CurDAG->SelectNodeTo(N, isDouble ? Alpha::CPYSNT : Alpha::CPYSNS,
325 T, CurDAG->getRegister(Alpha::F31, T),
326 CurDAG->getRegister(Alpha::F31, T));
336 if (MVT::isInteger(N->getValueType(0))) {
337 const char* opstr = 0;
338 switch(N->getOpcode()) {
339 case ISD::UREM: opstr = "__remqu"; break;
340 case ISD::SREM: opstr = "__remq"; break;
341 case ISD::UDIV: opstr = "__divqu"; break;
342 case ISD::SDIV: opstr = "__divq"; break;
344 SDOperand Tmp1 = Select(N->getOperand(0)),
345 Tmp2 = Select(N->getOperand(1)),
346 Addr = Select(CurDAG->getExternalSymbol(opstr,
347 AlphaLowering.getPointerTy()));
349 Chain = CurDAG->getCopyToReg(CurDAG->getEntryNode(), Alpha::R24, Tmp1,
351 Chain = CurDAG->getCopyToReg(Chain, Alpha::R25, Tmp2, Chain.getValue(1));
352 Chain = CurDAG->getCopyToReg(Chain, Alpha::R27, Addr, Chain.getValue(1));
353 Chain = CurDAG->getTargetNode(Alpha::JSRsDAG, MVT::Other, MVT::Flag,
354 Chain, Chain.getValue(1));
355 return CurDAG->getCopyFromReg(Chain, Alpha::R27, MVT::i64,
361 if (MVT::isFloatingPoint(N->getOperand(0).Val->getValueType(0))) {
362 unsigned Opc = Alpha::WTF;
363 ISD::CondCode CC = cast<CondCodeSDNode>(N->getOperand(2))->get();
367 default: N->dump(); assert(0 && "Unknown FP comparison!");
368 case ISD::SETEQ: Opc = Alpha::CMPTEQ; break;
369 case ISD::SETLT: Opc = Alpha::CMPTLT; break;
370 case ISD::SETLE: Opc = Alpha::CMPTLE; break;
371 case ISD::SETGT: Opc = Alpha::CMPTLT; rev = true; break;
372 case ISD::SETGE: Opc = Alpha::CMPTLE; rev = true; break;
373 case ISD::SETNE: Opc = Alpha::CMPTEQ; isNE = true; break;
375 SDOperand tmp1 = Select(N->getOperand(0)),
376 tmp2 = Select(N->getOperand(1));
377 SDOperand cmp = CurDAG->getTargetNode(Opc, MVT::f64,
381 cmp = CurDAG->getTargetNode(Alpha::CMPTEQ, MVT::f64, cmp,
382 CurDAG->getRegister(Alpha::F31, MVT::f64));
385 if (AlphaLowering.hasITOF()) {
386 LD = CurDAG->getNode(AlphaISD::FTOIT_, MVT::i64, cmp);
389 CurDAG->getMachineFunction().getFrameInfo()->CreateStackObject(8, 8);
390 SDOperand FI = CurDAG->getFrameIndex(FrameIdx, MVT::i64);
391 SDOperand ST = CurDAG->getTargetNode(Alpha::STT, MVT::Other,
392 cmp, FI, CurDAG->getRegister(Alpha::R31, MVT::i64));
393 LD = CurDAG->getTargetNode(Alpha::LDQ, MVT::i64, FI,
394 CurDAG->getRegister(Alpha::R31, MVT::i64),
397 SDOperand FP = CurDAG->getTargetNode(Alpha::CMPULT, MVT::i64,
398 CurDAG->getRegister(Alpha::R31, MVT::i64),
405 if (MVT::isFloatingPoint(N->getValueType(0)) &&
406 (N->getOperand(0).getOpcode() != ISD::SETCC ||
407 !MVT::isFloatingPoint(N->getOperand(0).getOperand(1).getValueType()))) {
408 //This should be the condition not covered by the Patterns
409 //FIXME: Don't have SelectCode die, but rather return something testable
410 // so that things like this can be caught in fall though code
412 bool isDouble = N->getValueType(0) == MVT::f64;
414 cond = Select(N->getOperand(0)),
415 TV = Select(N->getOperand(1)),
416 FV = Select(N->getOperand(2));
418 if (AlphaLowering.hasITOF()) {
419 LD = CurDAG->getNode(AlphaISD::ITOFT_, MVT::f64, cond);
422 CurDAG->getMachineFunction().getFrameInfo()->CreateStackObject(8, 8);
423 SDOperand FI = CurDAG->getFrameIndex(FrameIdx, MVT::i64);
424 SDOperand ST = CurDAG->getTargetNode(Alpha::STQ, MVT::Other,
425 cond, FI, CurDAG->getRegister(Alpha::R31, MVT::i64));
426 LD = CurDAG->getTargetNode(Alpha::LDT, MVT::f64, FI,
427 CurDAG->getRegister(Alpha::R31, MVT::i64),
430 SDOperand FP = CurDAG->getTargetNode(isDouble?Alpha::FCMOVEQT:Alpha::FCMOVEQS,
431 MVT::f64, FV, TV, LD);
438 return SelectCode(Op);
441 SDOperand AlphaDAGToDAGISel::SelectCALL(SDOperand Op) {
442 //TODO: add flag stuff to prevent nondeturministic breakage!
445 SDOperand Chain = Select(N->getOperand(0));
446 SDOperand Addr = Select(N->getOperand(1));
447 SDOperand InFlag; // Null incoming flag value.
449 std::vector<SDOperand> CallOperands;
450 std::vector<MVT::ValueType> TypeOperands;
453 for(int i = 2, e = N->getNumOperands(); i < e; ++i) {
454 TypeOperands.push_back(N->getOperand(i).getValueType());
455 CallOperands.push_back(Select(N->getOperand(i)));
457 int count = N->getNumOperands() - 2;
459 static const unsigned args_int[] = {Alpha::R16, Alpha::R17, Alpha::R18,
460 Alpha::R19, Alpha::R20, Alpha::R21};
461 static const unsigned args_float[] = {Alpha::F16, Alpha::F17, Alpha::F18,
462 Alpha::F19, Alpha::F20, Alpha::F21};
464 for (int i = 6; i < count; ++i) {
465 unsigned Opc = Alpha::WTF;
466 if (MVT::isInteger(TypeOperands[i])) {
468 } else if (TypeOperands[i] == MVT::f32) {
470 } else if (TypeOperands[i] == MVT::f64) {
473 assert(0 && "Unknown operand");
474 Chain = CurDAG->getTargetNode(Opc, MVT::Other, CallOperands[i],
475 getI64Imm((i - 6) * 8),
476 CurDAG->getCopyFromReg(Chain, Alpha::R30, MVT::i64),
479 for (int i = 0; i < std::min(6, count); ++i) {
480 if (MVT::isInteger(TypeOperands[i])) {
481 Chain = CurDAG->getCopyToReg(Chain, args_int[i], CallOperands[i], InFlag);
482 InFlag = Chain.getValue(1);
483 } else if (TypeOperands[i] == MVT::f32 || TypeOperands[i] == MVT::f64) {
484 Chain = CurDAG->getCopyToReg(Chain, args_float[i], CallOperands[i], InFlag);
485 InFlag = Chain.getValue(1);
487 assert(0 && "Unknown operand");
491 Chain = CurDAG->getCopyToReg(Chain, Alpha::R27, Addr, InFlag);
492 InFlag = Chain.getValue(1);
493 // Finally, once everything is in registers to pass to the call, emit the
495 Chain = CurDAG->getTargetNode(Alpha::JSRDAG, MVT::Other, MVT::Flag,
497 InFlag = Chain.getValue(1);
499 std::vector<SDOperand> CallResults;
501 switch (N->getValueType(0)) {
502 default: assert(0 && "Unexpected ret value!");
503 case MVT::Other: break;
505 Chain = CurDAG->getCopyFromReg(Chain, Alpha::R0, MVT::i64, InFlag).getValue(1);
506 CallResults.push_back(Chain.getValue(0));
509 Chain = CurDAG->getCopyFromReg(Chain, Alpha::F0, MVT::f32, InFlag).getValue(1);
510 CallResults.push_back(Chain.getValue(0));
513 Chain = CurDAG->getCopyFromReg(Chain, Alpha::F0, MVT::f64, InFlag).getValue(1);
514 CallResults.push_back(Chain.getValue(0));
518 CallResults.push_back(Chain);
519 for (unsigned i = 0, e = CallResults.size(); i != e; ++i)
520 CodeGenMap[Op.getValue(i)] = CallResults[i];
521 return CallResults[Op.ResNo];
525 /// createAlphaISelDag - This pass converts a legalized DAG into a
526 /// Alpha-specific DAG, ready for instruction scheduling.
528 FunctionPass *llvm::createAlphaISelDag(TargetMachine &TM) {
529 return new AlphaDAGToDAGISel(TM);