1 //===-- AlphaISelDAGToDAG.cpp - Alpha pattern matching inst selector ------===//
3 // The LLVM Compiler Infrastructure
5 // This file was developed by Andrew Lenharth and is distributed under
6 // the University of Illinois Open Source License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines a pattern matching instruction selector for Alpha,
11 // converting from a legalized dag to a Alpha dag.
13 //===----------------------------------------------------------------------===//
16 #include "AlphaTargetMachine.h"
17 #include "AlphaISelLowering.h"
18 #include "llvm/CodeGen/MachineInstrBuilder.h"
19 #include "llvm/CodeGen/MachineFrameInfo.h"
20 #include "llvm/CodeGen/MachineFunction.h"
21 #include "llvm/CodeGen/SSARegMap.h"
22 #include "llvm/CodeGen/SelectionDAG.h"
23 #include "llvm/CodeGen/SelectionDAGISel.h"
24 #include "llvm/Target/TargetOptions.h"
25 #include "llvm/ADT/Statistic.h"
26 #include "llvm/Constants.h"
27 #include "llvm/GlobalValue.h"
28 #include "llvm/Support/Debug.h"
29 #include "llvm/Support/MathExtras.h"
37 //===--------------------------------------------------------------------===//
38 /// AlphaDAGToDAGISel - Alpha specific code to select Alpha machine
39 /// instructions for SelectionDAG operations.
40 class AlphaDAGToDAGISel : public SelectionDAGISel {
41 AlphaTargetLowering AlphaLowering;
43 static const int64_t IMM_LOW = -32768;
44 static const int64_t IMM_HIGH = 32767;
45 static const int64_t IMM_MULT = 65536;
46 static const int64_t IMM_FULLHIGH = IMM_HIGH + IMM_HIGH * IMM_MULT;
47 static const int64_t IMM_FULLLOW = IMM_LOW + IMM_LOW * IMM_MULT;
49 static int64_t get_ldah16(int64_t x) {
50 int64_t y = x / IMM_MULT;
51 if (x % IMM_MULT > IMM_HIGH)
56 static int64_t get_lda16(int64_t x) {
57 return x - get_ldah16(x) * IMM_MULT;
60 static uint64_t get_zapImm(uint64_t x) {
61 unsigned int build = 0;
62 for(int i = 0; i < 8; ++i)
64 if ((x & 0x00FF) == 0x00FF)
66 else if ((x & 0x00FF) != 0)
73 static bool isFPZ(SDOperand N) {
74 ConstantFPSDNode *CN = dyn_cast<ConstantFPSDNode>(N);
75 return (CN && (CN->isExactlyValue(+0.0) || CN->isExactlyValue(-0.0)));
77 static bool isFPZn(SDOperand N) {
78 ConstantFPSDNode *CN = dyn_cast<ConstantFPSDNode>(N);
79 return (CN && CN->isExactlyValue(-0.0));
81 static bool isFPZp(SDOperand N) {
82 ConstantFPSDNode *CN = dyn_cast<ConstantFPSDNode>(N);
83 return (CN && CN->isExactlyValue(+0.0));
87 AlphaDAGToDAGISel(TargetMachine &TM)
88 : SelectionDAGISel(AlphaLowering), AlphaLowering(TM)
91 /// getI64Imm - Return a target constant with the specified value, of type
93 inline SDOperand getI64Imm(int64_t Imm) {
94 return CurDAG->getTargetConstant(Imm, MVT::i64);
97 // Select - Convert the specified operand from a target-independent to a
98 // target-specific node if it hasn't already been changed.
99 void Select(SDOperand &Result, SDOperand Op);
101 /// InstructionSelectBasicBlock - This callback is invoked by
102 /// SelectionDAGISel when it has created a SelectionDAG for us to codegen.
103 virtual void InstructionSelectBasicBlock(SelectionDAG &DAG);
105 virtual const char *getPassName() const {
106 return "Alpha DAG->DAG Pattern Instruction Selection";
109 // Include the pieces autogenerated from the target description.
110 #include "AlphaGenDAGISel.inc"
113 SDOperand getGlobalBaseReg();
114 SDOperand getRASaveReg();
115 SDOperand SelectCALL(SDOperand Op);
120 /// getGlobalBaseReg - Output the instructions required to put the
121 /// GOT address into a register.
123 SDOperand AlphaDAGToDAGISel::getGlobalBaseReg() {
124 return CurDAG->getCopyFromReg(CurDAG->getEntryNode(),
125 AlphaLowering.getVRegGP(),
129 /// getRASaveReg - Grab the return address
131 SDOperand AlphaDAGToDAGISel::getRASaveReg() {
132 return CurDAG->getCopyFromReg(CurDAG->getEntryNode(),
133 AlphaLowering.getVRegRA(),
137 /// InstructionSelectBasicBlock - This callback is invoked by
138 /// SelectionDAGISel when it has created a SelectionDAG for us to codegen.
139 void AlphaDAGToDAGISel::InstructionSelectBasicBlock(SelectionDAG &DAG) {
142 // Select target instructions for the DAG.
143 DAG.setRoot(SelectRoot(DAG.getRoot()));
145 DAG.RemoveDeadNodes();
147 // Emit machine code to BB.
148 ScheduleAndEmitDAG(DAG);
151 // Select - Convert the specified operand from a target-independent to a
152 // target-specific node if it hasn't already been changed.
153 void AlphaDAGToDAGISel::Select(SDOperand &Result, SDOperand Op) {
155 if (N->getOpcode() >= ISD::BUILTIN_OP_END &&
156 N->getOpcode() < AlphaISD::FIRST_NUMBER) {
158 return; // Already selected.
161 // If this has already been converted, use it.
162 std::map<SDOperand, SDOperand>::iterator CGMI = CodeGenMap.find(Op);
163 if (CGMI != CodeGenMap.end()) {
164 Result = CGMI->second;
168 switch (N->getOpcode()) {
171 Result = SelectCALL(Op);
174 case ISD::FrameIndex: {
175 int FI = cast<FrameIndexSDNode>(N)->getIndex();
176 Result = CurDAG->SelectNodeTo(N, Alpha::LDA, MVT::i64,
177 CurDAG->getTargetFrameIndex(FI, MVT::i32),
181 case AlphaISD::GlobalBaseReg:
182 Result = getGlobalBaseReg();
185 case AlphaISD::DivCall: {
186 SDOperand Chain = CurDAG->getEntryNode();
187 SDOperand N0, N1, N2;
188 Select(N0, Op.getOperand(0));
189 Select(N1, Op.getOperand(1));
190 Select(N2, Op.getOperand(2));
191 Chain = CurDAG->getCopyToReg(Chain, Alpha::R24, N1,
193 Chain = CurDAG->getCopyToReg(Chain, Alpha::R25, N2,
195 Chain = CurDAG->getCopyToReg(Chain, Alpha::R27, N0,
198 CurDAG->getTargetNode(Alpha::JSRs, MVT::Other, MVT::Flag,
199 Chain, Chain.getValue(1));
200 Chain = CurDAG->getCopyFromReg(Chain, Alpha::R27, MVT::i64,
201 SDOperand(CNode, 1));
202 Result = CurDAG->SelectNodeTo(N, Alpha::BIS, MVT::i64, Chain, Chain);
206 case ISD::READCYCLECOUNTER: {
208 Select(Chain, N->getOperand(0)); //Select chain
209 Result = CurDAG->SelectNodeTo(N, Alpha::RPCC, MVT::i64, Chain);
215 Select(Chain, N->getOperand(0)); // Token chain.
218 if (N->getNumOperands() == 2) {
220 Select(Val, N->getOperand(1));
221 if (N->getOperand(1).getValueType() == MVT::i64) {
222 Chain = CurDAG->getCopyToReg(Chain, Alpha::R0, Val, InFlag);
223 InFlag = Chain.getValue(1);
224 } else if (N->getOperand(1).getValueType() == MVT::f64 ||
225 N->getOperand(1).getValueType() == MVT::f32) {
226 Chain = CurDAG->getCopyToReg(Chain, Alpha::F0, Val, InFlag);
227 InFlag = Chain.getValue(1);
230 Chain = CurDAG->getCopyToReg(Chain, Alpha::R26, getRASaveReg(), InFlag);
231 InFlag = Chain.getValue(1);
233 // Finally, select this to a ret instruction.
234 Result = CurDAG->SelectNodeTo(N, Alpha::RETDAG, MVT::Other, Chain, InFlag);
237 case ISD::Constant: {
238 uint64_t uval = cast<ConstantSDNode>(N)->getValue();
241 Result = CurDAG->getCopyFromReg(CurDAG->getEntryNode(), Alpha::R31,
246 int64_t val = (int64_t)uval;
247 int32_t val32 = (int32_t)val;
248 if (val <= IMM_HIGH + IMM_HIGH * IMM_MULT &&
249 val >= IMM_LOW + IMM_LOW * IMM_MULT)
250 break; //(LDAH (LDA))
251 if ((uval >> 32) == 0 && //empty upper bits
252 val32 <= IMM_HIGH + IMM_HIGH * IMM_MULT)
253 // val32 >= IMM_LOW + IMM_LOW * IMM_MULT) //always true
254 break; //(zext (LDAH (LDA)))
255 //Else use the constant pool
256 MachineConstantPool *CP = BB->getParent()->getConstantPool();
258 ConstantUInt::get(Type::getPrimitiveType(Type::ULongTyID) , uval);
259 SDOperand CPI = CurDAG->getTargetConstantPool(C, MVT::i64);
260 SDNode *Tmp = CurDAG->getTargetNode(Alpha::LDAHr, MVT::i64, CPI,
262 Result = CurDAG->SelectNodeTo(N, Alpha::LDQr, MVT::i64, MVT::Other,
263 CPI, SDOperand(Tmp, 0), CurDAG->getEntryNode());
266 case ISD::TargetConstantFP: {
267 ConstantFPSDNode *CN = cast<ConstantFPSDNode>(N);
268 bool isDouble = N->getValueType(0) == MVT::f64;
269 MVT::ValueType T = isDouble ? MVT::f64 : MVT::f32;
270 if (CN->isExactlyValue(+0.0)) {
271 Result = CurDAG->SelectNodeTo(N, isDouble ? Alpha::CPYST : Alpha::CPYSS,
272 T, CurDAG->getRegister(Alpha::F31, T),
273 CurDAG->getRegister(Alpha::F31, T));
275 } else if ( CN->isExactlyValue(-0.0)) {
276 Result = CurDAG->SelectNodeTo(N, isDouble ? Alpha::CPYSNT : Alpha::CPYSNS,
277 T, CurDAG->getRegister(Alpha::F31, T),
278 CurDAG->getRegister(Alpha::F31, T));
287 if (MVT::isFloatingPoint(N->getOperand(0).Val->getValueType(0))) {
288 unsigned Opc = Alpha::WTF;
289 ISD::CondCode CC = cast<CondCodeSDNode>(N->getOperand(2))->get();
293 default: N->dump(); assert(0 && "Unknown FP comparison!");
294 case ISD::SETEQ: Opc = Alpha::CMPTEQ; break;
295 case ISD::SETLT: Opc = Alpha::CMPTLT; break;
296 case ISD::SETLE: Opc = Alpha::CMPTLE; break;
297 case ISD::SETGT: Opc = Alpha::CMPTLT; rev = true; break;
298 case ISD::SETGE: Opc = Alpha::CMPTLE; rev = true; break;
299 case ISD::SETNE: Opc = Alpha::CMPTEQ; isNE = true; break;
301 SDOperand tmp1, tmp2;
302 Select(tmp1, N->getOperand(0));
303 Select(tmp2, N->getOperand(1));
304 SDNode *cmp = CurDAG->getTargetNode(Opc, MVT::f64,
308 cmp = CurDAG->getTargetNode(Alpha::CMPTEQ, MVT::f64, SDOperand(cmp, 0),
309 CurDAG->getRegister(Alpha::F31, MVT::f64));
312 if (AlphaLowering.hasITOF()) {
313 LD = CurDAG->getNode(AlphaISD::FTOIT_, MVT::i64, SDOperand(cmp, 0));
316 CurDAG->getMachineFunction().getFrameInfo()->CreateStackObject(8, 8);
317 SDOperand FI = CurDAG->getFrameIndex(FrameIdx, MVT::i64);
319 SDOperand(CurDAG->getTargetNode(Alpha::STT, MVT::Other,
320 SDOperand(cmp, 0), FI,
321 CurDAG->getRegister(Alpha::R31, MVT::i64)), 0);
322 LD = SDOperand(CurDAG->getTargetNode(Alpha::LDQ, MVT::i64, FI,
323 CurDAG->getRegister(Alpha::R31, MVT::i64),
326 Result = SDOperand(CurDAG->getTargetNode(Alpha::CMPULT, MVT::i64,
327 CurDAG->getRegister(Alpha::R31, MVT::i64),
334 if (MVT::isFloatingPoint(N->getValueType(0)) &&
335 (N->getOperand(0).getOpcode() != ISD::SETCC ||
336 !MVT::isFloatingPoint(N->getOperand(0).getOperand(1).getValueType()))) {
337 //This should be the condition not covered by the Patterns
338 //FIXME: Don't have SelectCode die, but rather return something testable
339 // so that things like this can be caught in fall though code
341 bool isDouble = N->getValueType(0) == MVT::f64;
342 SDOperand LD, cond, TV, FV;
343 Select(cond, N->getOperand(0));
344 Select(TV, N->getOperand(1));
345 Select(FV, N->getOperand(2));
347 if (AlphaLowering.hasITOF()) {
348 LD = CurDAG->getNode(AlphaISD::ITOFT_, MVT::f64, cond);
351 CurDAG->getMachineFunction().getFrameInfo()->CreateStackObject(8, 8);
352 SDOperand FI = CurDAG->getFrameIndex(FrameIdx, MVT::i64);
354 SDOperand(CurDAG->getTargetNode(Alpha::STQ, MVT::Other,
355 cond, FI, CurDAG->getRegister(Alpha::R31, MVT::i64)), 0);
356 LD = SDOperand(CurDAG->getTargetNode(Alpha::LDT, MVT::f64, FI,
357 CurDAG->getRegister(Alpha::R31, MVT::i64),
360 Result = SDOperand(CurDAG->getTargetNode(isDouble?Alpha::FCMOVNET:Alpha::FCMOVNES,
361 MVT::f64, FV, TV, LD), 0);
369 if (N->getOperand(0).getOpcode() == ISD::SRL &&
370 (MC = dyn_cast<ConstantSDNode>(N->getOperand(1))) &&
371 (SC = dyn_cast<ConstantSDNode>(N->getOperand(0).getOperand(1))))
373 uint64_t sval = SC->getValue();
374 uint64_t mval = MC->getValue();
375 if (get_zapImm(mval)) //the result is a zap, let the autogened stuff deal
377 // given mask X, and shift S, we want to see if there is any zap in the mask
378 // if we play around with the botton S bits
379 uint64_t dontcare = (~0ULL) >> (64 - sval);
380 uint64_t mask = mval << sval;
382 if (get_zapImm(mask | dontcare))
383 mask = mask | dontcare;
385 if (get_zapImm(mask)) {
387 Select(Src, N->getOperand(0).getOperand(0));
389 SDOperand(CurDAG->getTargetNode(Alpha::ZAPNOTi, MVT::i64, Src,
390 getI64Imm(get_zapImm(mask))), 0);
391 Result = SDOperand(CurDAG->getTargetNode(Alpha::SRL, MVT::i64, Z,
392 getI64Imm(sval)), 0);
401 SelectCode(Result, Op);
404 SDOperand AlphaDAGToDAGISel::SelectCALL(SDOperand Op) {
405 //TODO: add flag stuff to prevent nondeturministic breakage!
409 SDOperand Addr = N->getOperand(1);
410 SDOperand InFlag; // Null incoming flag value.
411 Select(Chain, N->getOperand(0));
413 std::vector<SDOperand> CallOperands;
414 std::vector<MVT::ValueType> TypeOperands;
417 for(int i = 2, e = N->getNumOperands(); i < e; ++i) {
419 TypeOperands.push_back(N->getOperand(i).getValueType());
420 Select(Tmp, N->getOperand(i));
421 CallOperands.push_back(Tmp);
423 int count = N->getNumOperands() - 2;
425 static const unsigned args_int[] = {Alpha::R16, Alpha::R17, Alpha::R18,
426 Alpha::R19, Alpha::R20, Alpha::R21};
427 static const unsigned args_float[] = {Alpha::F16, Alpha::F17, Alpha::F18,
428 Alpha::F19, Alpha::F20, Alpha::F21};
430 for (int i = 6; i < count; ++i) {
431 unsigned Opc = Alpha::WTF;
432 if (MVT::isInteger(TypeOperands[i])) {
434 } else if (TypeOperands[i] == MVT::f32) {
436 } else if (TypeOperands[i] == MVT::f64) {
439 assert(0 && "Unknown operand");
440 Chain = SDOperand(CurDAG->getTargetNode(Opc, MVT::Other, CallOperands[i],
441 getI64Imm((i - 6) * 8),
442 CurDAG->getCopyFromReg(Chain, Alpha::R30, MVT::i64),
445 for (int i = 0; i < std::min(6, count); ++i) {
446 if (MVT::isInteger(TypeOperands[i])) {
447 Chain = CurDAG->getCopyToReg(Chain, args_int[i], CallOperands[i], InFlag);
448 InFlag = Chain.getValue(1);
449 } else if (TypeOperands[i] == MVT::f32 || TypeOperands[i] == MVT::f64) {
450 Chain = CurDAG->getCopyToReg(Chain, args_float[i], CallOperands[i], InFlag);
451 InFlag = Chain.getValue(1);
453 assert(0 && "Unknown operand");
457 // Finally, once everything is in registers to pass to the call, emit the
459 if (Addr.getOpcode() == AlphaISD::GPRelLo) {
460 SDOperand GOT = getGlobalBaseReg();
461 Chain = CurDAG->getCopyToReg(Chain, Alpha::R29, GOT, InFlag);
462 InFlag = Chain.getValue(1);
463 Chain = SDOperand(CurDAG->getTargetNode(Alpha::BSR, MVT::Other, MVT::Flag,
464 Addr.getOperand(0), Chain, InFlag), 0);
467 Chain = CurDAG->getCopyToReg(Chain, Alpha::R27, Addr, InFlag);
468 InFlag = Chain.getValue(1);
469 Chain = SDOperand(CurDAG->getTargetNode(Alpha::JSR, MVT::Other, MVT::Flag,
472 InFlag = Chain.getValue(1);
474 std::vector<SDOperand> CallResults;
476 switch (N->getValueType(0)) {
477 default: assert(0 && "Unexpected ret value!");
478 case MVT::Other: break;
480 Chain = CurDAG->getCopyFromReg(Chain, Alpha::R0, MVT::i64, InFlag).getValue(1);
481 CallResults.push_back(Chain.getValue(0));
484 Chain = CurDAG->getCopyFromReg(Chain, Alpha::F0, MVT::f32, InFlag).getValue(1);
485 CallResults.push_back(Chain.getValue(0));
488 Chain = CurDAG->getCopyFromReg(Chain, Alpha::F0, MVT::f64, InFlag).getValue(1);
489 CallResults.push_back(Chain.getValue(0));
493 CallResults.push_back(Chain);
494 for (unsigned i = 0, e = CallResults.size(); i != e; ++i)
495 CodeGenMap[Op.getValue(i)] = CallResults[i];
496 return CallResults[Op.ResNo];
500 /// createAlphaISelDag - This pass converts a legalized DAG into a
501 /// Alpha-specific DAG, ready for instruction scheduling.
503 FunctionPass *llvm::createAlphaISelDag(TargetMachine &TM) {
504 return new AlphaDAGToDAGISel(TM);