1 //===-- AlphaISelDAGToDAG.cpp - Alpha pattern matching inst selector ------===//
3 // The LLVM Compiler Infrastructure
5 // This file was developed by Andrew Lenharth and is distributed under
6 // the University of Illinois Open Source License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines a pattern matching instruction selector for Alpha,
11 // converting from a legalized dag to a Alpha dag.
13 //===----------------------------------------------------------------------===//
16 #include "AlphaTargetMachine.h"
17 #include "AlphaISelLowering.h"
18 #include "llvm/CodeGen/MachineInstrBuilder.h"
19 #include "llvm/CodeGen/MachineFrameInfo.h"
20 #include "llvm/CodeGen/MachineFunction.h"
21 #include "llvm/CodeGen/SSARegMap.h"
22 #include "llvm/CodeGen/SelectionDAG.h"
23 #include "llvm/CodeGen/SelectionDAGISel.h"
24 #include "llvm/Target/TargetOptions.h"
25 #include "llvm/ADT/Statistic.h"
26 #include "llvm/Constants.h"
27 #include "llvm/GlobalValue.h"
28 #include "llvm/Intrinsics.h"
29 #include "llvm/Support/Debug.h"
30 #include "llvm/Support/MathExtras.h"
38 //===--------------------------------------------------------------------===//
39 /// AlphaDAGToDAGISel - Alpha specific code to select Alpha machine
40 /// instructions for SelectionDAG operations.
41 class AlphaDAGToDAGISel : public SelectionDAGISel {
42 AlphaTargetLowering AlphaLowering;
44 static const int64_t IMM_LOW = -32768;
45 static const int64_t IMM_HIGH = 32767;
46 static const int64_t IMM_MULT = 65536;
47 static const int64_t IMM_FULLHIGH = IMM_HIGH + IMM_HIGH * IMM_MULT;
48 static const int64_t IMM_FULLLOW = IMM_LOW + IMM_LOW * IMM_MULT;
50 static int64_t get_ldah16(int64_t x) {
51 int64_t y = x / IMM_MULT;
52 if (x % IMM_MULT > IMM_HIGH)
57 static int64_t get_lda16(int64_t x) {
58 return x - get_ldah16(x) * IMM_MULT;
61 static uint64_t get_zapImm(uint64_t x) {
62 unsigned int build = 0;
63 for(int i = 0; i < 8; ++i)
65 if ((x & 0x00FF) == 0x00FF)
67 else if ((x & 0x00FF) != 0)
74 static uint64_t getNearPower2(uint64_t x) {
76 unsigned at = CountLeadingZeros_64(x);
77 uint64_t complow = 1 << (63 - at);
78 uint64_t comphigh = 1 << (64 - at);
79 //std::cerr << x << ":" << complow << ":" << comphigh << "\n";
80 if (abs(complow - x) <= abs(comphigh - x))
86 static bool isFPZ(SDOperand N) {
87 ConstantFPSDNode *CN = dyn_cast<ConstantFPSDNode>(N);
88 return (CN && (CN->isExactlyValue(+0.0) || CN->isExactlyValue(-0.0)));
90 static bool isFPZn(SDOperand N) {
91 ConstantFPSDNode *CN = dyn_cast<ConstantFPSDNode>(N);
92 return (CN && CN->isExactlyValue(-0.0));
94 static bool isFPZp(SDOperand N) {
95 ConstantFPSDNode *CN = dyn_cast<ConstantFPSDNode>(N);
96 return (CN && CN->isExactlyValue(+0.0));
100 AlphaDAGToDAGISel(TargetMachine &TM)
101 : SelectionDAGISel(AlphaLowering), AlphaLowering(TM)
104 /// getI64Imm - Return a target constant with the specified value, of type
106 inline SDOperand getI64Imm(int64_t Imm) {
107 return CurDAG->getTargetConstant(Imm, MVT::i64);
110 // Select - Convert the specified operand from a target-independent to a
111 // target-specific node if it hasn't already been changed.
112 void Select(SDOperand &Result, SDOperand Op);
114 /// InstructionSelectBasicBlock - This callback is invoked by
115 /// SelectionDAGISel when it has created a SelectionDAG for us to codegen.
116 virtual void InstructionSelectBasicBlock(SelectionDAG &DAG);
118 virtual const char *getPassName() const {
119 return "Alpha DAG->DAG Pattern Instruction Selection";
122 // Include the pieces autogenerated from the target description.
123 #include "AlphaGenDAGISel.inc"
126 SDOperand getGlobalBaseReg();
127 SDOperand getRASaveReg();
128 SDOperand SelectCALL(SDOperand Op);
133 /// getGlobalBaseReg - Output the instructions required to put the
134 /// GOT address into a register.
136 SDOperand AlphaDAGToDAGISel::getGlobalBaseReg() {
137 return CurDAG->getCopyFromReg(CurDAG->getEntryNode(),
138 AlphaLowering.getVRegGP(),
142 /// getRASaveReg - Grab the return address
144 SDOperand AlphaDAGToDAGISel::getRASaveReg() {
145 return CurDAG->getCopyFromReg(CurDAG->getEntryNode(),
146 AlphaLowering.getVRegRA(),
150 /// InstructionSelectBasicBlock - This callback is invoked by
151 /// SelectionDAGISel when it has created a SelectionDAG for us to codegen.
152 void AlphaDAGToDAGISel::InstructionSelectBasicBlock(SelectionDAG &DAG) {
155 // Select target instructions for the DAG.
156 DAG.setRoot(SelectRoot(DAG.getRoot()));
157 assert(InFlightSet.empty() && "ISel InFlightSet has not been emptied!");
161 DAG.RemoveDeadNodes();
163 // Emit machine code to BB.
164 ScheduleAndEmitDAG(DAG);
167 // Select - Convert the specified operand from a target-independent to a
168 // target-specific node if it hasn't already been changed.
169 void AlphaDAGToDAGISel::Select(SDOperand &Result, SDOperand Op) {
171 if (N->getOpcode() >= ISD::BUILTIN_OP_END &&
172 N->getOpcode() < AlphaISD::FIRST_NUMBER) {
174 return; // Already selected.
177 // If this has already been converted, use it.
178 std::map<SDOperand, SDOperand>::iterator CGMI = CodeGenMap.find(Op);
179 if (CGMI != CodeGenMap.end()) {
180 Result = CGMI->second;
184 switch (N->getOpcode()) {
187 Result = SelectCALL(Op);
190 case ISD::FrameIndex: {
191 int FI = cast<FrameIndexSDNode>(N)->getIndex();
192 Result = CurDAG->SelectNodeTo(N, Alpha::LDA, MVT::i64,
193 CurDAG->getTargetFrameIndex(FI, MVT::i32),
197 case AlphaISD::GlobalBaseReg:
198 Result = getGlobalBaseReg();
201 case AlphaISD::DivCall: {
202 SDOperand Chain = CurDAG->getEntryNode();
203 SDOperand N0, N1, N2;
204 Select(N0, Op.getOperand(0));
205 Select(N1, Op.getOperand(1));
206 Select(N2, Op.getOperand(2));
207 Chain = CurDAG->getCopyToReg(Chain, Alpha::R24, N1,
209 Chain = CurDAG->getCopyToReg(Chain, Alpha::R25, N2,
211 Chain = CurDAG->getCopyToReg(Chain, Alpha::R27, N0,
214 CurDAG->getTargetNode(Alpha::JSRs, MVT::Other, MVT::Flag,
215 Chain, Chain.getValue(1));
216 Chain = CurDAG->getCopyFromReg(Chain, Alpha::R27, MVT::i64,
217 SDOperand(CNode, 1));
218 Result = CurDAG->SelectNodeTo(N, Alpha::BIS, MVT::i64, Chain, Chain);
222 case ISD::READCYCLECOUNTER: {
224 Select(Chain, N->getOperand(0)); //Select chain
225 Result = CurDAG->SelectNodeTo(N, Alpha::RPCC, MVT::i64, Chain);
231 Select(Chain, N->getOperand(0)); // Token chain.
232 SDOperand InFlag(0,0);
234 if (N->getNumOperands() == 3) {
236 Select(Val, N->getOperand(1));
237 if (N->getOperand(1).getValueType() == MVT::i64) {
238 Chain = CurDAG->getCopyToReg(Chain, Alpha::R0, Val, InFlag);
239 InFlag = Chain.getValue(1);
240 } else if (N->getOperand(1).getValueType() == MVT::f64 ||
241 N->getOperand(1).getValueType() == MVT::f32) {
242 Chain = CurDAG->getCopyToReg(Chain, Alpha::F0, Val, InFlag);
243 InFlag = Chain.getValue(1);
246 Chain = CurDAG->getCopyToReg(Chain, Alpha::R26, getRASaveReg(), InFlag);
247 InFlag = Chain.getValue(1);
249 // Finally, select this to a ret instruction.
250 Result = CurDAG->SelectNodeTo(N, Alpha::RETDAG, MVT::Other, Chain, InFlag);
253 case ISD::Constant: {
254 uint64_t uval = cast<ConstantSDNode>(N)->getValue();
257 Result = CurDAG->getCopyFromReg(CurDAG->getEntryNode(), Alpha::R31,
262 int64_t val = (int64_t)uval;
263 int32_t val32 = (int32_t)val;
264 if (val <= IMM_HIGH + IMM_HIGH * IMM_MULT &&
265 val >= IMM_LOW + IMM_LOW * IMM_MULT)
266 break; //(LDAH (LDA))
267 if ((uval >> 32) == 0 && //empty upper bits
268 val32 <= IMM_HIGH + IMM_HIGH * IMM_MULT)
269 // val32 >= IMM_LOW + IMM_LOW * IMM_MULT) //always true
270 break; //(zext (LDAH (LDA)))
271 //Else use the constant pool
272 MachineConstantPool *CP = BB->getParent()->getConstantPool();
274 ConstantUInt::get(Type::getPrimitiveType(Type::ULongTyID) , uval);
275 SDOperand CPI = CurDAG->getTargetConstantPool(C, MVT::i64);
276 SDNode *Tmp = CurDAG->getTargetNode(Alpha::LDAHr, MVT::i64, CPI,
278 Result = CurDAG->SelectNodeTo(N, Alpha::LDQr, MVT::i64, MVT::Other,
279 CPI, SDOperand(Tmp, 0), CurDAG->getEntryNode());
282 case ISD::TargetConstantFP: {
283 ConstantFPSDNode *CN = cast<ConstantFPSDNode>(N);
284 bool isDouble = N->getValueType(0) == MVT::f64;
285 MVT::ValueType T = isDouble ? MVT::f64 : MVT::f32;
286 if (CN->isExactlyValue(+0.0)) {
287 Result = CurDAG->SelectNodeTo(N, isDouble ? Alpha::CPYST : Alpha::CPYSS,
288 T, CurDAG->getRegister(Alpha::F31, T),
289 CurDAG->getRegister(Alpha::F31, T));
291 } else if ( CN->isExactlyValue(-0.0)) {
292 Result = CurDAG->SelectNodeTo(N, isDouble ? Alpha::CPYSNT : Alpha::CPYSNS,
293 T, CurDAG->getRegister(Alpha::F31, T),
294 CurDAG->getRegister(Alpha::F31, T));
303 if (MVT::isFloatingPoint(N->getOperand(0).Val->getValueType(0))) {
304 unsigned Opc = Alpha::WTF;
305 ISD::CondCode CC = cast<CondCodeSDNode>(N->getOperand(2))->get();
309 default: N->dump(); assert(0 && "Unknown FP comparison!");
310 case ISD::SETEQ: Opc = Alpha::CMPTEQ; break;
311 case ISD::SETLT: Opc = Alpha::CMPTLT; break;
312 case ISD::SETLE: Opc = Alpha::CMPTLE; break;
313 case ISD::SETGT: Opc = Alpha::CMPTLT; rev = true; break;
314 case ISD::SETGE: Opc = Alpha::CMPTLE; rev = true; break;
315 case ISD::SETNE: Opc = Alpha::CMPTEQ; isNE = true; break;
317 SDOperand tmp1, tmp2;
318 Select(tmp1, N->getOperand(0));
319 Select(tmp2, N->getOperand(1));
320 SDNode *cmp = CurDAG->getTargetNode(Opc, MVT::f64,
324 cmp = CurDAG->getTargetNode(Alpha::CMPTEQ, MVT::f64, SDOperand(cmp, 0),
325 CurDAG->getRegister(Alpha::F31, MVT::f64));
328 if (AlphaLowering.hasITOF()) {
329 LD = CurDAG->getNode(AlphaISD::FTOIT_, MVT::i64, SDOperand(cmp, 0));
332 CurDAG->getMachineFunction().getFrameInfo()->CreateStackObject(8, 8);
333 SDOperand FI = CurDAG->getFrameIndex(FrameIdx, MVT::i64);
335 SDOperand(CurDAG->getTargetNode(Alpha::STT, MVT::Other,
336 SDOperand(cmp, 0), FI,
337 CurDAG->getRegister(Alpha::R31, MVT::i64)), 0);
338 LD = SDOperand(CurDAG->getTargetNode(Alpha::LDQ, MVT::i64, FI,
339 CurDAG->getRegister(Alpha::R31, MVT::i64),
342 Result = SDOperand(CurDAG->getTargetNode(Alpha::CMPULT, MVT::i64,
343 CurDAG->getRegister(Alpha::R31, MVT::i64),
350 if (MVT::isFloatingPoint(N->getValueType(0)) &&
351 (N->getOperand(0).getOpcode() != ISD::SETCC ||
352 !MVT::isFloatingPoint(N->getOperand(0).getOperand(1).getValueType()))) {
353 //This should be the condition not covered by the Patterns
354 //FIXME: Don't have SelectCode die, but rather return something testable
355 // so that things like this can be caught in fall though code
357 bool isDouble = N->getValueType(0) == MVT::f64;
358 SDOperand LD, cond, TV, FV;
359 Select(cond, N->getOperand(0));
360 Select(TV, N->getOperand(1));
361 Select(FV, N->getOperand(2));
363 if (AlphaLowering.hasITOF()) {
364 LD = CurDAG->getNode(AlphaISD::ITOFT_, MVT::f64, cond);
367 CurDAG->getMachineFunction().getFrameInfo()->CreateStackObject(8, 8);
368 SDOperand FI = CurDAG->getFrameIndex(FrameIdx, MVT::i64);
370 SDOperand(CurDAG->getTargetNode(Alpha::STQ, MVT::Other,
371 cond, FI, CurDAG->getRegister(Alpha::R31, MVT::i64)), 0);
372 LD = SDOperand(CurDAG->getTargetNode(Alpha::LDT, MVT::f64, FI,
373 CurDAG->getRegister(Alpha::R31, MVT::i64),
376 Result = SDOperand(CurDAG->getTargetNode(isDouble?Alpha::FCMOVNET:Alpha::FCMOVNES,
377 MVT::f64, FV, TV, LD), 0);
383 ConstantSDNode* SC = NULL;
384 ConstantSDNode* MC = NULL;
385 if (N->getOperand(0).getOpcode() == ISD::SRL &&
386 (MC = dyn_cast<ConstantSDNode>(N->getOperand(1))) &&
387 (SC = dyn_cast<ConstantSDNode>(N->getOperand(0).getOperand(1))))
389 uint64_t sval = SC->getValue();
390 uint64_t mval = MC->getValue();
391 if (get_zapImm(mval)) //the result is a zap, let the autogened stuff deal
393 // given mask X, and shift S, we want to see if there is any zap in the mask
394 // if we play around with the botton S bits
395 uint64_t dontcare = (~0ULL) >> (64 - sval);
396 uint64_t mask = mval << sval;
398 if (get_zapImm(mask | dontcare))
399 mask = mask | dontcare;
401 if (get_zapImm(mask)) {
403 Select(Src, N->getOperand(0).getOperand(0));
405 SDOperand(CurDAG->getTargetNode(Alpha::ZAPNOTi, MVT::i64, Src,
406 getI64Imm(get_zapImm(mask))), 0);
407 Result = SDOperand(CurDAG->getTargetNode(Alpha::SRL, MVT::i64, Z,
408 getI64Imm(sval)), 0);
417 SelectCode(Result, Op);
420 SDOperand AlphaDAGToDAGISel::SelectCALL(SDOperand Op) {
421 //TODO: add flag stuff to prevent nondeturministic breakage!
425 SDOperand Addr = N->getOperand(1);
426 SDOperand InFlag(0,0); // Null incoming flag value.
427 Select(Chain, N->getOperand(0));
429 std::vector<SDOperand> CallOperands;
430 std::vector<MVT::ValueType> TypeOperands;
433 for(int i = 2, e = N->getNumOperands(); i < e; ++i) {
435 TypeOperands.push_back(N->getOperand(i).getValueType());
436 Select(Tmp, N->getOperand(i));
437 CallOperands.push_back(Tmp);
439 int count = N->getNumOperands() - 2;
441 static const unsigned args_int[] = {Alpha::R16, Alpha::R17, Alpha::R18,
442 Alpha::R19, Alpha::R20, Alpha::R21};
443 static const unsigned args_float[] = {Alpha::F16, Alpha::F17, Alpha::F18,
444 Alpha::F19, Alpha::F20, Alpha::F21};
446 for (int i = 6; i < count; ++i) {
447 unsigned Opc = Alpha::WTF;
448 if (MVT::isInteger(TypeOperands[i])) {
450 } else if (TypeOperands[i] == MVT::f32) {
452 } else if (TypeOperands[i] == MVT::f64) {
455 assert(0 && "Unknown operand");
456 Chain = SDOperand(CurDAG->getTargetNode(Opc, MVT::Other, CallOperands[i],
457 getI64Imm((i - 6) * 8),
458 CurDAG->getCopyFromReg(Chain, Alpha::R30, MVT::i64),
461 for (int i = 0; i < std::min(6, count); ++i) {
462 if (MVT::isInteger(TypeOperands[i])) {
463 Chain = CurDAG->getCopyToReg(Chain, args_int[i], CallOperands[i], InFlag);
464 InFlag = Chain.getValue(1);
465 } else if (TypeOperands[i] == MVT::f32 || TypeOperands[i] == MVT::f64) {
466 Chain = CurDAG->getCopyToReg(Chain, args_float[i], CallOperands[i], InFlag);
467 InFlag = Chain.getValue(1);
469 assert(0 && "Unknown operand");
473 // Finally, once everything is in registers to pass to the call, emit the
475 if (Addr.getOpcode() == AlphaISD::GPRelLo) {
476 SDOperand GOT = getGlobalBaseReg();
477 Chain = CurDAG->getCopyToReg(Chain, Alpha::R29, GOT, InFlag);
478 InFlag = Chain.getValue(1);
479 Chain = SDOperand(CurDAG->getTargetNode(Alpha::BSR, MVT::Other, MVT::Flag,
480 Addr.getOperand(0), Chain, InFlag), 0);
483 Chain = CurDAG->getCopyToReg(Chain, Alpha::R27, Addr, InFlag);
484 InFlag = Chain.getValue(1);
485 Chain = SDOperand(CurDAG->getTargetNode(Alpha::JSR, MVT::Other, MVT::Flag,
488 InFlag = Chain.getValue(1);
490 std::vector<SDOperand> CallResults;
492 switch (N->getValueType(0)) {
493 default: assert(0 && "Unexpected ret value!");
494 case MVT::Other: break;
496 Chain = CurDAG->getCopyFromReg(Chain, Alpha::R0, MVT::i64, InFlag).getValue(1);
497 CallResults.push_back(Chain.getValue(0));
500 Chain = CurDAG->getCopyFromReg(Chain, Alpha::F0, MVT::f32, InFlag).getValue(1);
501 CallResults.push_back(Chain.getValue(0));
504 Chain = CurDAG->getCopyFromReg(Chain, Alpha::F0, MVT::f64, InFlag).getValue(1);
505 CallResults.push_back(Chain.getValue(0));
509 CallResults.push_back(Chain);
510 for (unsigned i = 0, e = CallResults.size(); i != e; ++i)
511 CodeGenMap[Op.getValue(i)] = CallResults[i];
512 return CallResults[Op.ResNo];
516 /// createAlphaISelDag - This pass converts a legalized DAG into a
517 /// Alpha-specific DAG, ready for instruction scheduling.
519 FunctionPass *llvm::createAlphaISelDag(TargetMachine &TM) {
520 return new AlphaDAGToDAGISel(TM);