1 //===-- AlphaISelDAGToDAG.cpp - Alpha pattern matching inst selector ------===//
3 // The LLVM Compiler Infrastructure
5 // This file was developed by Andrew Lenharth and is distributed under
6 // the University of Illinois Open Source License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines a pattern matching instruction selector for Alpha,
11 // converting from a legalized dag to a Alpha dag.
13 //===----------------------------------------------------------------------===//
16 #include "AlphaTargetMachine.h"
17 #include "AlphaISelLowering.h"
18 #include "llvm/CodeGen/MachineInstrBuilder.h"
19 #include "llvm/CodeGen/MachineFrameInfo.h"
20 #include "llvm/CodeGen/MachineFunction.h"
21 #include "llvm/CodeGen/SSARegMap.h"
22 #include "llvm/CodeGen/SelectionDAG.h"
23 #include "llvm/CodeGen/SelectionDAGISel.h"
24 #include "llvm/Target/TargetOptions.h"
25 #include "llvm/ADT/Statistic.h"
26 #include "llvm/Constants.h"
27 #include "llvm/GlobalValue.h"
28 #include "llvm/Intrinsics.h"
29 #include "llvm/Support/Debug.h"
30 #include "llvm/Support/MathExtras.h"
39 //===--------------------------------------------------------------------===//
40 /// AlphaDAGToDAGISel - Alpha specific code to select Alpha machine
41 /// instructions for SelectionDAG operations.
42 class AlphaDAGToDAGISel : public SelectionDAGISel {
43 AlphaTargetLowering AlphaLowering;
45 static const int64_t IMM_LOW = -32768;
46 static const int64_t IMM_HIGH = 32767;
47 static const int64_t IMM_MULT = 65536;
48 static const int64_t IMM_FULLHIGH = IMM_HIGH + IMM_HIGH * IMM_MULT;
49 static const int64_t IMM_FULLLOW = IMM_LOW + IMM_LOW * IMM_MULT;
51 static int64_t get_ldah16(int64_t x) {
52 int64_t y = x / IMM_MULT;
53 if (x % IMM_MULT > IMM_HIGH)
58 static int64_t get_lda16(int64_t x) {
59 return x - get_ldah16(x) * IMM_MULT;
62 static uint64_t get_zapImm(uint64_t x) {
63 unsigned int build = 0;
64 for(int i = 0; i < 8; ++i)
66 if ((x & 0x00FF) == 0x00FF)
68 else if ((x & 0x00FF) != 0)
75 static uint64_t getNearPower2(uint64_t x) {
77 unsigned at = CountLeadingZeros_64(x);
78 uint64_t complow = 1 << (63 - at);
79 uint64_t comphigh = 1 << (64 - at);
80 //std::cerr << x << ":" << complow << ":" << comphigh << "\n";
81 if (abs(complow - x) <= abs(comphigh - x))
87 static bool isFPZ(SDOperand N) {
88 ConstantFPSDNode *CN = dyn_cast<ConstantFPSDNode>(N);
89 return (CN && (CN->isExactlyValue(+0.0) || CN->isExactlyValue(-0.0)));
91 static bool isFPZn(SDOperand N) {
92 ConstantFPSDNode *CN = dyn_cast<ConstantFPSDNode>(N);
93 return (CN && CN->isExactlyValue(-0.0));
95 static bool isFPZp(SDOperand N) {
96 ConstantFPSDNode *CN = dyn_cast<ConstantFPSDNode>(N);
97 return (CN && CN->isExactlyValue(+0.0));
101 AlphaDAGToDAGISel(TargetMachine &TM)
102 : SelectionDAGISel(AlphaLowering),
103 AlphaLowering(*(AlphaTargetLowering*)(TM.getTargetLowering()))
106 /// getI64Imm - Return a target constant with the specified value, of type
108 inline SDOperand getI64Imm(int64_t Imm) {
109 return CurDAG->getTargetConstant(Imm, MVT::i64);
112 // Select - Convert the specified operand from a target-independent to a
113 // target-specific node if it hasn't already been changed.
114 SDNode *Select(SDOperand Op);
116 /// InstructionSelectBasicBlock - This callback is invoked by
117 /// SelectionDAGISel when it has created a SelectionDAG for us to codegen.
118 virtual void InstructionSelectBasicBlock(SelectionDAG &DAG);
120 virtual const char *getPassName() const {
121 return "Alpha DAG->DAG Pattern Instruction Selection";
124 /// SelectInlineAsmMemoryOperand - Implement addressing mode selection for
125 /// inline asm expressions.
126 virtual bool SelectInlineAsmMemoryOperand(const SDOperand &Op,
128 std::vector<SDOperand> &OutOps,
131 switch (ConstraintCode) {
132 default: return true;
139 OutOps.push_back(Op0);
143 // Include the pieces autogenerated from the target description.
144 #include "AlphaGenDAGISel.inc"
147 SDOperand getGlobalBaseReg();
148 SDOperand getGlobalRetAddr();
149 void SelectCALL(SDOperand Op);
154 /// getGlobalBaseReg - Output the instructions required to put the
155 /// GOT address into a register.
157 SDOperand AlphaDAGToDAGISel::getGlobalBaseReg() {
158 return CurDAG->getCopyFromReg(CurDAG->getEntryNode(),
159 AlphaLowering.getVRegGP(),
163 /// getRASaveReg - Grab the return address
165 SDOperand AlphaDAGToDAGISel::getGlobalRetAddr() {
166 return CurDAG->getCopyFromReg(CurDAG->getEntryNode(),
167 AlphaLowering.getVRegRA(),
171 /// InstructionSelectBasicBlock - This callback is invoked by
172 /// SelectionDAGISel when it has created a SelectionDAG for us to codegen.
173 void AlphaDAGToDAGISel::InstructionSelectBasicBlock(SelectionDAG &DAG) {
176 // Select target instructions for the DAG.
177 DAG.setRoot(SelectRoot(DAG.getRoot()));
178 DAG.RemoveDeadNodes();
180 // Emit machine code to BB.
181 ScheduleAndEmitDAG(DAG);
184 // Select - Convert the specified operand from a target-independent to a
185 // target-specific node if it hasn't already been changed.
186 SDNode *AlphaDAGToDAGISel::Select(SDOperand Op) {
188 if (N->getOpcode() >= ISD::BUILTIN_OP_END &&
189 N->getOpcode() < AlphaISD::FIRST_NUMBER) {
190 return NULL; // Already selected.
193 switch (N->getOpcode()) {
199 case ISD::FrameIndex: {
200 int FI = cast<FrameIndexSDNode>(N)->getIndex();
201 return CurDAG->SelectNodeTo(N, Alpha::LDA, MVT::i64,
202 CurDAG->getTargetFrameIndex(FI, MVT::i32),
205 case ISD::GLOBAL_OFFSET_TABLE: {
206 SDOperand Result = getGlobalBaseReg();
207 ReplaceUses(Op, Result);
210 case AlphaISD::GlobalRetAddr: {
211 SDOperand Result = getGlobalRetAddr();
212 ReplaceUses(Op, Result);
216 case AlphaISD::DivCall: {
217 SDOperand Chain = CurDAG->getEntryNode();
218 SDOperand N0 = Op.getOperand(0);
219 SDOperand N1 = Op.getOperand(1);
220 SDOperand N2 = Op.getOperand(2);
224 Chain = CurDAG->getCopyToReg(Chain, Alpha::R24, N1,
226 Chain = CurDAG->getCopyToReg(Chain, Alpha::R25, N2,
228 Chain = CurDAG->getCopyToReg(Chain, Alpha::R27, N0,
231 CurDAG->getTargetNode(Alpha::JSRs, MVT::Other, MVT::Flag,
232 Chain, Chain.getValue(1));
233 Chain = CurDAG->getCopyFromReg(Chain, Alpha::R27, MVT::i64,
234 SDOperand(CNode, 1));
235 return CurDAG->SelectNodeTo(N, Alpha::BIS, MVT::i64, Chain, Chain);
238 case ISD::READCYCLECOUNTER: {
239 SDOperand Chain = N->getOperand(0);
240 AddToISelQueue(Chain); //Select chain
241 return CurDAG->getTargetNode(Alpha::RPCC, MVT::i64, MVT::Other,
245 case ISD::Constant: {
246 uint64_t uval = cast<ConstantSDNode>(N)->getValue();
249 SDOperand Result = CurDAG->getCopyFromReg(CurDAG->getEntryNode(),
250 Alpha::R31, MVT::i64);
251 ReplaceUses(Op, Result);
255 int64_t val = (int64_t)uval;
256 int32_t val32 = (int32_t)val;
257 if (val <= IMM_HIGH + IMM_HIGH * IMM_MULT &&
258 val >= IMM_LOW + IMM_LOW * IMM_MULT)
259 break; //(LDAH (LDA))
260 if ((uval >> 32) == 0 && //empty upper bits
261 val32 <= IMM_HIGH + IMM_HIGH * IMM_MULT)
262 // val32 >= IMM_LOW + IMM_LOW * IMM_MULT) //always true
263 break; //(zext (LDAH (LDA)))
264 //Else use the constant pool
265 MachineConstantPool *CP = BB->getParent()->getConstantPool();
267 ConstantUInt::get(Type::getPrimitiveType(Type::ULongTyID) , uval);
268 SDOperand CPI = CurDAG->getTargetConstantPool(C, MVT::i64);
269 SDNode *Tmp = CurDAG->getTargetNode(Alpha::LDAHr, MVT::i64, CPI,
271 return CurDAG->SelectNodeTo(N, Alpha::LDQr, MVT::i64, MVT::Other,
272 CPI, SDOperand(Tmp, 0), CurDAG->getEntryNode());
274 case ISD::TargetConstantFP: {
275 ConstantFPSDNode *CN = cast<ConstantFPSDNode>(N);
276 bool isDouble = N->getValueType(0) == MVT::f64;
277 MVT::ValueType T = isDouble ? MVT::f64 : MVT::f32;
278 if (CN->isExactlyValue(+0.0)) {
279 return CurDAG->SelectNodeTo(N, isDouble ? Alpha::CPYST : Alpha::CPYSS,
280 T, CurDAG->getRegister(Alpha::F31, T),
281 CurDAG->getRegister(Alpha::F31, T));
282 } else if ( CN->isExactlyValue(-0.0)) {
283 return CurDAG->SelectNodeTo(N, isDouble ? Alpha::CPYSNT : Alpha::CPYSNS,
284 T, CurDAG->getRegister(Alpha::F31, T),
285 CurDAG->getRegister(Alpha::F31, T));
293 if (MVT::isFloatingPoint(N->getOperand(0).Val->getValueType(0))) {
294 unsigned Opc = Alpha::WTF;
295 ISD::CondCode CC = cast<CondCodeSDNode>(N->getOperand(2))->get();
299 default: DEBUG(N->dump()); assert(0 && "Unknown FP comparison!");
300 case ISD::SETEQ: case ISD::SETOEQ: case ISD::SETUEQ: Opc = Alpha::CMPTEQ; break;
301 case ISD::SETLT: case ISD::SETOLT: case ISD::SETULT: Opc = Alpha::CMPTLT; break;
302 case ISD::SETLE: case ISD::SETOLE: case ISD::SETULE: Opc = Alpha::CMPTLE; break;
303 case ISD::SETGT: case ISD::SETOGT: case ISD::SETUGT: Opc = Alpha::CMPTLT; rev = true; break;
304 case ISD::SETGE: case ISD::SETOGE: case ISD::SETUGE: Opc = Alpha::CMPTLE; rev = true; break;
305 case ISD::SETNE: case ISD::SETONE: case ISD::SETUNE: Opc = Alpha::CMPTEQ; isNE = true; break;
307 SDOperand tmp1 = N->getOperand(0);
308 SDOperand tmp2 = N->getOperand(1);
309 AddToISelQueue(tmp1);
310 AddToISelQueue(tmp2);
311 SDNode *cmp = CurDAG->getTargetNode(Opc, MVT::f64,
315 cmp = CurDAG->getTargetNode(Alpha::CMPTEQ, MVT::f64, SDOperand(cmp, 0),
316 CurDAG->getRegister(Alpha::F31, MVT::f64));
319 if (AlphaLowering.hasITOF()) {
320 LD = CurDAG->getNode(AlphaISD::FTOIT_, MVT::i64, SDOperand(cmp, 0));
323 CurDAG->getMachineFunction().getFrameInfo()->CreateStackObject(8, 8);
324 SDOperand FI = CurDAG->getFrameIndex(FrameIdx, MVT::i64);
326 SDOperand(CurDAG->getTargetNode(Alpha::STT, MVT::Other,
327 SDOperand(cmp, 0), FI,
328 CurDAG->getRegister(Alpha::R31, MVT::i64)), 0);
329 LD = SDOperand(CurDAG->getTargetNode(Alpha::LDQ, MVT::i64, FI,
330 CurDAG->getRegister(Alpha::R31, MVT::i64),
333 return CurDAG->getTargetNode(Alpha::CMPULT, MVT::i64,
334 CurDAG->getRegister(Alpha::R31, MVT::i64),
340 if (MVT::isFloatingPoint(N->getValueType(0)) &&
341 (N->getOperand(0).getOpcode() != ISD::SETCC ||
342 !MVT::isFloatingPoint(N->getOperand(0).getOperand(1).getValueType()))) {
343 //This should be the condition not covered by the Patterns
344 //FIXME: Don't have SelectCode die, but rather return something testable
345 // so that things like this can be caught in fall though code
347 bool isDouble = N->getValueType(0) == MVT::f64;
349 SDOperand cond = N->getOperand(0);
350 SDOperand TV = N->getOperand(1);
351 SDOperand FV = N->getOperand(2);
352 AddToISelQueue(cond);
356 if (AlphaLowering.hasITOF()) {
357 LD = CurDAG->getNode(AlphaISD::ITOFT_, MVT::f64, cond);
360 CurDAG->getMachineFunction().getFrameInfo()->CreateStackObject(8, 8);
361 SDOperand FI = CurDAG->getFrameIndex(FrameIdx, MVT::i64);
363 SDOperand(CurDAG->getTargetNode(Alpha::STQ, MVT::Other,
364 cond, FI, CurDAG->getRegister(Alpha::R31, MVT::i64)), 0);
365 LD = SDOperand(CurDAG->getTargetNode(Alpha::LDT, MVT::f64, FI,
366 CurDAG->getRegister(Alpha::R31, MVT::i64),
369 return CurDAG->getTargetNode(isDouble?Alpha::FCMOVNET:Alpha::FCMOVNES,
370 MVT::f64, FV, TV, LD);
375 ConstantSDNode* SC = NULL;
376 ConstantSDNode* MC = NULL;
377 if (N->getOperand(0).getOpcode() == ISD::SRL &&
378 (MC = dyn_cast<ConstantSDNode>(N->getOperand(1))) &&
379 (SC = dyn_cast<ConstantSDNode>(N->getOperand(0).getOperand(1))))
381 uint64_t sval = SC->getValue();
382 uint64_t mval = MC->getValue();
383 if (get_zapImm(mval)) //the result is a zap, let the autogened stuff deal
385 // given mask X, and shift S, we want to see if there is any zap in the mask
386 // if we play around with the botton S bits
387 uint64_t dontcare = (~0ULL) >> (64 - sval);
388 uint64_t mask = mval << sval;
390 if (get_zapImm(mask | dontcare))
391 mask = mask | dontcare;
393 if (get_zapImm(mask)) {
394 AddToISelQueue(N->getOperand(0).getOperand(0));
396 SDOperand(CurDAG->getTargetNode(Alpha::ZAPNOTi, MVT::i64,
397 N->getOperand(0).getOperand(0),
398 getI64Imm(get_zapImm(mask))), 0);
399 return CurDAG->getTargetNode(Alpha::SRL, MVT::i64, Z,
408 return SelectCode(Op);
411 void AlphaDAGToDAGISel::SelectCALL(SDOperand Op) {
412 //TODO: add flag stuff to prevent nondeturministic breakage!
415 SDOperand Chain = N->getOperand(0);
416 SDOperand Addr = N->getOperand(1);
417 SDOperand InFlag(0,0); // Null incoming flag value.
418 AddToISelQueue(Chain);
420 std::vector<SDOperand> CallOperands;
421 std::vector<MVT::ValueType> TypeOperands;
424 for(int i = 2, e = N->getNumOperands(); i < e; ++i) {
425 TypeOperands.push_back(N->getOperand(i).getValueType());
426 AddToISelQueue(N->getOperand(i));
427 CallOperands.push_back(N->getOperand(i));
429 int count = N->getNumOperands() - 2;
431 static const unsigned args_int[] = {Alpha::R16, Alpha::R17, Alpha::R18,
432 Alpha::R19, Alpha::R20, Alpha::R21};
433 static const unsigned args_float[] = {Alpha::F16, Alpha::F17, Alpha::F18,
434 Alpha::F19, Alpha::F20, Alpha::F21};
436 for (int i = 6; i < count; ++i) {
437 unsigned Opc = Alpha::WTF;
438 if (MVT::isInteger(TypeOperands[i])) {
440 } else if (TypeOperands[i] == MVT::f32) {
442 } else if (TypeOperands[i] == MVT::f64) {
445 assert(0 && "Unknown operand");
447 SDOperand Ops[] = { CallOperands[i], getI64Imm((i - 6) * 8),
448 CurDAG->getCopyFromReg(Chain, Alpha::R30, MVT::i64),
450 Chain = SDOperand(CurDAG->getTargetNode(Opc, MVT::Other, Ops, 4), 0);
452 for (int i = 0; i < std::min(6, count); ++i) {
453 if (MVT::isInteger(TypeOperands[i])) {
454 Chain = CurDAG->getCopyToReg(Chain, args_int[i], CallOperands[i], InFlag);
455 InFlag = Chain.getValue(1);
456 } else if (TypeOperands[i] == MVT::f32 || TypeOperands[i] == MVT::f64) {
457 Chain = CurDAG->getCopyToReg(Chain, args_float[i], CallOperands[i], InFlag);
458 InFlag = Chain.getValue(1);
460 assert(0 && "Unknown operand");
463 // Finally, once everything is in registers to pass to the call, emit the
465 if (Addr.getOpcode() == AlphaISD::GPRelLo) {
466 SDOperand GOT = getGlobalBaseReg();
467 Chain = CurDAG->getCopyToReg(Chain, Alpha::R29, GOT, InFlag);
468 InFlag = Chain.getValue(1);
469 Chain = SDOperand(CurDAG->getTargetNode(Alpha::BSR, MVT::Other, MVT::Flag,
470 Addr.getOperand(0), Chain, InFlag), 0);
472 AddToISelQueue(Addr);
473 Chain = CurDAG->getCopyToReg(Chain, Alpha::R27, Addr, InFlag);
474 InFlag = Chain.getValue(1);
475 Chain = SDOperand(CurDAG->getTargetNode(Alpha::JSR, MVT::Other, MVT::Flag,
478 InFlag = Chain.getValue(1);
480 std::vector<SDOperand> CallResults;
482 switch (N->getValueType(0)) {
483 default: assert(0 && "Unexpected ret value!");
484 case MVT::Other: break;
486 Chain = CurDAG->getCopyFromReg(Chain, Alpha::R0, MVT::i64, InFlag).getValue(1);
487 CallResults.push_back(Chain.getValue(0));
490 Chain = CurDAG->getCopyFromReg(Chain, Alpha::F0, MVT::f32, InFlag).getValue(1);
491 CallResults.push_back(Chain.getValue(0));
494 Chain = CurDAG->getCopyFromReg(Chain, Alpha::F0, MVT::f64, InFlag).getValue(1);
495 CallResults.push_back(Chain.getValue(0));
499 CallResults.push_back(Chain);
500 for (unsigned i = 0, e = CallResults.size(); i != e; ++i)
501 ReplaceUses(Op.getValue(i), CallResults[i]);
505 /// createAlphaISelDag - This pass converts a legalized DAG into a
506 /// Alpha-specific DAG, ready for instruction scheduling.
508 FunctionPass *llvm::createAlphaISelDag(TargetMachine &TM) {
509 return new AlphaDAGToDAGISel(TM);