1 //===-- AlphaISelDAGToDAG.cpp - Alpha pattern matching inst selector ------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines a pattern matching instruction selector for Alpha,
11 // converting from a legalized dag to a Alpha dag.
13 //===----------------------------------------------------------------------===//
16 #include "AlphaTargetMachine.h"
17 #include "AlphaISelLowering.h"
18 #include "llvm/CodeGen/MachineInstrBuilder.h"
19 #include "llvm/CodeGen/MachineFrameInfo.h"
20 #include "llvm/CodeGen/MachineFunction.h"
21 #include "llvm/CodeGen/MachineRegisterInfo.h"
22 #include "llvm/CodeGen/SelectionDAG.h"
23 #include "llvm/CodeGen/SelectionDAGISel.h"
24 #include "llvm/Target/TargetOptions.h"
25 #include "llvm/Constants.h"
26 #include "llvm/DerivedTypes.h"
27 #include "llvm/GlobalValue.h"
28 #include "llvm/Intrinsics.h"
29 #include "llvm/Support/Debug.h"
30 #include "llvm/Support/MathExtras.h"
38 //===--------------------------------------------------------------------===//
39 /// AlphaDAGToDAGISel - Alpha specific code to select Alpha machine
40 /// instructions for SelectionDAG operations.
41 class AlphaDAGToDAGISel : public SelectionDAGISel {
42 AlphaTargetLowering AlphaLowering;
44 static const int64_t IMM_LOW = -32768;
45 static const int64_t IMM_HIGH = 32767;
46 static const int64_t IMM_MULT = 65536;
47 static const int64_t IMM_FULLHIGH = IMM_HIGH + IMM_HIGH * IMM_MULT;
48 static const int64_t IMM_FULLLOW = IMM_LOW + IMM_LOW * IMM_MULT;
50 static int64_t get_ldah16(int64_t x) {
51 int64_t y = x / IMM_MULT;
52 if (x % IMM_MULT > IMM_HIGH)
57 static int64_t get_lda16(int64_t x) {
58 return x - get_ldah16(x) * IMM_MULT;
61 /// get_zapImm - Return a zap mask if X is a valid immediate for a zapnot
62 /// instruction (if not, return 0). Note that this code accepts partial
63 /// zap masks. For example (and LHS, 1) is a valid zap, as long we know
64 /// that the bits 1-7 of LHS are already zero. If LHS is non-null, we are
65 /// in checking mode. If LHS is null, we assume that the mask has already
66 /// been validated before.
67 uint64_t get_zapImm(SDOperand LHS, uint64_t Constant) {
68 uint64_t BitsToCheck = 0;
70 for (unsigned i = 0; i != 8; ++i) {
71 if (((Constant >> 8*i) & 0xFF) == 0) {
75 if (((Constant >> 8*i) & 0xFF) == 0xFF) {
76 // If the entire byte is set, zapnot the byte.
77 } else if (LHS.Val == 0) {
78 // Otherwise, if the mask was previously validated, we know its okay
79 // to zapnot this entire byte even though all the bits aren't set.
81 // Otherwise we don't know that the it's okay to zapnot this entire
82 // byte. Only do this iff we can prove that the missing bits are
83 // already null, so the bytezap doesn't need to really null them.
84 BitsToCheck |= ~Constant & (0xFF << 8*i);
89 // If there are missing bits in a byte (for example, X & 0xEF00), check to
90 // see if the missing bits (0x1000) are already known zero if not, the zap
91 // isn't okay to do, as it won't clear all the required bits.
93 !CurDAG->MaskedValueIsZero(LHS, BitsToCheck))
99 static uint64_t get_zapImm(uint64_t x) {
101 for(int i = 0; i != 8; ++i) {
102 if ((x & 0x00FF) == 0x00FF)
104 else if ((x & 0x00FF) != 0)
112 static uint64_t getNearPower2(uint64_t x) {
114 unsigned at = CountLeadingZeros_64(x);
115 uint64_t complow = 1 << (63 - at);
116 uint64_t comphigh = 1 << (64 - at);
117 //cerr << x << ":" << complow << ":" << comphigh << "\n";
118 if (abs(complow - x) <= abs(comphigh - x))
124 static bool chkRemNearPower2(uint64_t x, uint64_t r, bool swap) {
125 uint64_t y = getNearPower2(x);
132 static bool isFPZ(SDOperand N) {
133 ConstantFPSDNode *CN = dyn_cast<ConstantFPSDNode>(N);
134 return (CN && (CN->getValueAPF().isZero()));
136 static bool isFPZn(SDOperand N) {
137 ConstantFPSDNode *CN = dyn_cast<ConstantFPSDNode>(N);
138 return (CN && CN->getValueAPF().isNegZero());
140 static bool isFPZp(SDOperand N) {
141 ConstantFPSDNode *CN = dyn_cast<ConstantFPSDNode>(N);
142 return (CN && CN->getValueAPF().isPosZero());
146 AlphaDAGToDAGISel(TargetMachine &TM)
147 : SelectionDAGISel(AlphaLowering),
148 AlphaLowering(*(AlphaTargetLowering*)(TM.getTargetLowering()))
151 /// getI64Imm - Return a target constant with the specified value, of type
153 inline SDOperand getI64Imm(int64_t Imm) {
154 return CurDAG->getTargetConstant(Imm, MVT::i64);
157 // Select - Convert the specified operand from a target-independent to a
158 // target-specific node if it hasn't already been changed.
159 SDNode *Select(SDOperand Op);
161 /// InstructionSelectBasicBlock - This callback is invoked by
162 /// SelectionDAGISel when it has created a SelectionDAG for us to codegen.
163 virtual void InstructionSelectBasicBlock(SelectionDAG &DAG);
165 virtual const char *getPassName() const {
166 return "Alpha DAG->DAG Pattern Instruction Selection";
169 /// SelectInlineAsmMemoryOperand - Implement addressing mode selection for
170 /// inline asm expressions.
171 virtual bool SelectInlineAsmMemoryOperand(const SDOperand &Op,
173 std::vector<SDOperand> &OutOps,
176 switch (ConstraintCode) {
177 default: return true;
184 OutOps.push_back(Op0);
188 // Include the pieces autogenerated from the target description.
189 #include "AlphaGenDAGISel.inc"
192 SDOperand getGlobalBaseReg();
193 SDOperand getGlobalRetAddr();
194 void SelectCALL(SDOperand Op);
199 /// getGlobalBaseReg - Output the instructions required to put the
200 /// GOT address into a register.
202 SDOperand AlphaDAGToDAGISel::getGlobalBaseReg() {
204 for(MachineRegisterInfo::livein_iterator ii = RegInfo->livein_begin(),
205 ee = RegInfo->livein_end(); ii != ee; ++ii)
206 if (ii->first == Alpha::R29) {
210 assert(GP && "GOT PTR not in liveins");
211 return CurDAG->getCopyFromReg(CurDAG->getEntryNode(),
215 /// getRASaveReg - Grab the return address
217 SDOperand AlphaDAGToDAGISel::getGlobalRetAddr() {
219 for(MachineRegisterInfo::livein_iterator ii = RegInfo->livein_begin(),
220 ee = RegInfo->livein_end(); ii != ee; ++ii)
221 if (ii->first == Alpha::R26) {
225 assert(RA && "RA PTR not in liveins");
226 return CurDAG->getCopyFromReg(CurDAG->getEntryNode(),
230 /// InstructionSelectBasicBlock - This callback is invoked by
231 /// SelectionDAGISel when it has created a SelectionDAG for us to codegen.
232 void AlphaDAGToDAGISel::InstructionSelectBasicBlock(SelectionDAG &DAG) {
235 // Select target instructions for the DAG.
236 DAG.setRoot(SelectRoot(DAG.getRoot()));
237 DAG.RemoveDeadNodes();
239 // Emit machine code to BB.
240 ScheduleAndEmitDAG(DAG);
243 // Select - Convert the specified operand from a target-independent to a
244 // target-specific node if it hasn't already been changed.
245 SDNode *AlphaDAGToDAGISel::Select(SDOperand Op) {
247 if (N->getOpcode() >= ISD::BUILTIN_OP_END &&
248 N->getOpcode() < AlphaISD::FIRST_NUMBER) {
249 return NULL; // Already selected.
252 switch (N->getOpcode()) {
258 case ISD::FrameIndex: {
259 int FI = cast<FrameIndexSDNode>(N)->getIndex();
260 return CurDAG->SelectNodeTo(N, Alpha::LDA, MVT::i64,
261 CurDAG->getTargetFrameIndex(FI, MVT::i32),
264 case ISD::GLOBAL_OFFSET_TABLE: {
265 SDOperand Result = getGlobalBaseReg();
266 ReplaceUses(Op, Result);
269 case AlphaISD::GlobalRetAddr: {
270 SDOperand Result = getGlobalRetAddr();
271 ReplaceUses(Op, Result);
275 case AlphaISD::DivCall: {
276 SDOperand Chain = CurDAG->getEntryNode();
277 SDOperand N0 = Op.getOperand(0);
278 SDOperand N1 = Op.getOperand(1);
279 SDOperand N2 = Op.getOperand(2);
283 Chain = CurDAG->getCopyToReg(Chain, Alpha::R24, N1,
285 Chain = CurDAG->getCopyToReg(Chain, Alpha::R25, N2,
287 Chain = CurDAG->getCopyToReg(Chain, Alpha::R27, N0,
290 CurDAG->getTargetNode(Alpha::JSRs, MVT::Other, MVT::Flag,
291 Chain, Chain.getValue(1));
292 Chain = CurDAG->getCopyFromReg(Chain, Alpha::R27, MVT::i64,
293 SDOperand(CNode, 1));
294 return CurDAG->SelectNodeTo(N, Alpha::BISr, MVT::i64, Chain, Chain);
297 case ISD::READCYCLECOUNTER: {
298 SDOperand Chain = N->getOperand(0);
299 AddToISelQueue(Chain); //Select chain
300 return CurDAG->getTargetNode(Alpha::RPCC, MVT::i64, MVT::Other,
304 case ISD::Constant: {
305 uint64_t uval = cast<ConstantSDNode>(N)->getValue();
308 SDOperand Result = CurDAG->getCopyFromReg(CurDAG->getEntryNode(),
309 Alpha::R31, MVT::i64);
310 ReplaceUses(Op, Result);
314 int64_t val = (int64_t)uval;
315 int32_t val32 = (int32_t)val;
316 if (val <= IMM_HIGH + IMM_HIGH * IMM_MULT &&
317 val >= IMM_LOW + IMM_LOW * IMM_MULT)
318 break; //(LDAH (LDA))
319 if ((uval >> 32) == 0 && //empty upper bits
320 val32 <= IMM_HIGH + IMM_HIGH * IMM_MULT)
321 // val32 >= IMM_LOW + IMM_LOW * IMM_MULT) //always true
322 break; //(zext (LDAH (LDA)))
323 //Else use the constant pool
324 ConstantInt *C = ConstantInt::get(Type::Int64Ty, uval);
325 SDOperand CPI = CurDAG->getTargetConstantPool(C, MVT::i64);
326 SDNode *Tmp = CurDAG->getTargetNode(Alpha::LDAHr, MVT::i64, CPI,
328 return CurDAG->SelectNodeTo(N, Alpha::LDQr, MVT::i64, MVT::Other,
329 CPI, SDOperand(Tmp, 0), CurDAG->getEntryNode());
331 case ISD::TargetConstantFP: {
332 ConstantFPSDNode *CN = cast<ConstantFPSDNode>(N);
333 bool isDouble = N->getValueType(0) == MVT::f64;
334 MVT::ValueType T = isDouble ? MVT::f64 : MVT::f32;
335 if (CN->getValueAPF().isPosZero()) {
336 return CurDAG->SelectNodeTo(N, isDouble ? Alpha::CPYST : Alpha::CPYSS,
337 T, CurDAG->getRegister(Alpha::F31, T),
338 CurDAG->getRegister(Alpha::F31, T));
339 } else if (CN->getValueAPF().isNegZero()) {
340 return CurDAG->SelectNodeTo(N, isDouble ? Alpha::CPYSNT : Alpha::CPYSNS,
341 T, CurDAG->getRegister(Alpha::F31, T),
342 CurDAG->getRegister(Alpha::F31, T));
350 if (MVT::isFloatingPoint(N->getOperand(0).Val->getValueType(0))) {
351 ISD::CondCode CC = cast<CondCodeSDNode>(N->getOperand(2))->get();
353 unsigned Opc = Alpha::WTF;
357 default: DEBUG(N->dump(CurDAG)); assert(0 && "Unknown FP comparison!");
358 case ISD::SETEQ: case ISD::SETOEQ: case ISD::SETUEQ:
359 Opc = Alpha::CMPTEQ; break;
360 case ISD::SETLT: case ISD::SETOLT: case ISD::SETULT:
361 Opc = Alpha::CMPTLT; break;
362 case ISD::SETLE: case ISD::SETOLE: case ISD::SETULE:
363 Opc = Alpha::CMPTLE; break;
364 case ISD::SETGT: case ISD::SETOGT: case ISD::SETUGT:
365 Opc = Alpha::CMPTLT; rev = true; break;
366 case ISD::SETGE: case ISD::SETOGE: case ISD::SETUGE:
367 Opc = Alpha::CMPTLE; rev = true; break;
368 case ISD::SETNE: case ISD::SETONE: case ISD::SETUNE:
369 Opc = Alpha::CMPTEQ; inv = true; break;
371 Opc = Alpha::CMPTUN; inv = true; break;
373 Opc = Alpha::CMPTUN; break;
375 SDOperand tmp1 = N->getOperand(rev?1:0);
376 SDOperand tmp2 = N->getOperand(rev?0:1);
377 AddToISelQueue(tmp1);
378 AddToISelQueue(tmp2);
379 SDNode *cmp = CurDAG->getTargetNode(Opc, MVT::f64, tmp1, tmp2);
381 cmp = CurDAG->getTargetNode(Alpha::CMPTEQ, MVT::f64, SDOperand(cmp, 0),
382 CurDAG->getRegister(Alpha::F31, MVT::f64));
384 case ISD::SETUEQ: case ISD::SETULT: case ISD::SETULE:
385 case ISD::SETUNE: case ISD::SETUGT: case ISD::SETUGE:
387 SDNode* cmp2 = CurDAG->getTargetNode(Alpha::CMPTUN, MVT::f64,
389 cmp = CurDAG->getTargetNode(Alpha::ADDT, MVT::f64,
390 SDOperand(cmp2, 0), SDOperand(cmp, 0));
396 SDNode* LD = CurDAG->getTargetNode(Alpha::FTOIT, MVT::i64, SDOperand(cmp, 0));
397 return CurDAG->getTargetNode(Alpha::CMPULT, MVT::i64,
398 CurDAG->getRegister(Alpha::R31, MVT::i64),
404 if (MVT::isFloatingPoint(N->getValueType(0)) &&
405 (N->getOperand(0).getOpcode() != ISD::SETCC ||
406 !MVT::isFloatingPoint(N->getOperand(0).getOperand(1).getValueType()))) {
407 //This should be the condition not covered by the Patterns
408 //FIXME: Don't have SelectCode die, but rather return something testable
409 // so that things like this can be caught in fall though code
411 bool isDouble = N->getValueType(0) == MVT::f64;
412 SDOperand cond = N->getOperand(0);
413 SDOperand TV = N->getOperand(1);
414 SDOperand FV = N->getOperand(2);
415 AddToISelQueue(cond);
419 SDNode* LD = CurDAG->getTargetNode(Alpha::ITOFT, MVT::f64, cond);
420 return CurDAG->getTargetNode(isDouble?Alpha::FCMOVNET:Alpha::FCMOVNES,
421 MVT::f64, FV, TV, SDOperand(LD,0));
426 ConstantSDNode* SC = NULL;
427 ConstantSDNode* MC = NULL;
428 if (N->getOperand(0).getOpcode() == ISD::SRL &&
429 (MC = dyn_cast<ConstantSDNode>(N->getOperand(1))) &&
430 (SC = dyn_cast<ConstantSDNode>(N->getOperand(0).getOperand(1)))) {
431 uint64_t sval = SC->getValue();
432 uint64_t mval = MC->getValue();
433 // If the result is a zap, let the autogened stuff handle it.
434 if (get_zapImm(N->getOperand(0), mval))
436 // given mask X, and shift S, we want to see if there is any zap in the
437 // mask if we play around with the botton S bits
438 uint64_t dontcare = (~0ULL) >> (64 - sval);
439 uint64_t mask = mval << sval;
441 if (get_zapImm(mask | dontcare))
442 mask = mask | dontcare;
444 if (get_zapImm(mask)) {
445 AddToISelQueue(N->getOperand(0).getOperand(0));
447 SDOperand(CurDAG->getTargetNode(Alpha::ZAPNOTi, MVT::i64,
448 N->getOperand(0).getOperand(0),
449 getI64Imm(get_zapImm(mask))), 0);
450 return CurDAG->getTargetNode(Alpha::SRLr, MVT::i64, Z,
459 return SelectCode(Op);
462 void AlphaDAGToDAGISel::SelectCALL(SDOperand Op) {
463 //TODO: add flag stuff to prevent nondeturministic breakage!
466 SDOperand Chain = N->getOperand(0);
467 SDOperand Addr = N->getOperand(1);
468 SDOperand InFlag(0,0); // Null incoming flag value.
469 AddToISelQueue(Chain);
471 std::vector<SDOperand> CallOperands;
472 std::vector<MVT::ValueType> TypeOperands;
475 for(int i = 2, e = N->getNumOperands(); i < e; ++i) {
476 TypeOperands.push_back(N->getOperand(i).getValueType());
477 AddToISelQueue(N->getOperand(i));
478 CallOperands.push_back(N->getOperand(i));
480 int count = N->getNumOperands() - 2;
482 static const unsigned args_int[] = {Alpha::R16, Alpha::R17, Alpha::R18,
483 Alpha::R19, Alpha::R20, Alpha::R21};
484 static const unsigned args_float[] = {Alpha::F16, Alpha::F17, Alpha::F18,
485 Alpha::F19, Alpha::F20, Alpha::F21};
487 for (int i = 6; i < count; ++i) {
488 unsigned Opc = Alpha::WTF;
489 if (MVT::isInteger(TypeOperands[i])) {
491 } else if (TypeOperands[i] == MVT::f32) {
493 } else if (TypeOperands[i] == MVT::f64) {
496 assert(0 && "Unknown operand");
498 SDOperand Ops[] = { CallOperands[i], getI64Imm((i - 6) * 8),
499 CurDAG->getCopyFromReg(Chain, Alpha::R30, MVT::i64),
501 Chain = SDOperand(CurDAG->getTargetNode(Opc, MVT::Other, Ops, 4), 0);
503 for (int i = 0; i < std::min(6, count); ++i) {
504 if (MVT::isInteger(TypeOperands[i])) {
505 Chain = CurDAG->getCopyToReg(Chain, args_int[i], CallOperands[i], InFlag);
506 InFlag = Chain.getValue(1);
507 } else if (TypeOperands[i] == MVT::f32 || TypeOperands[i] == MVT::f64) {
508 Chain = CurDAG->getCopyToReg(Chain, args_float[i], CallOperands[i], InFlag);
509 InFlag = Chain.getValue(1);
511 assert(0 && "Unknown operand");
514 // Finally, once everything is in registers to pass to the call, emit the
516 if (Addr.getOpcode() == AlphaISD::GPRelLo) {
517 SDOperand GOT = getGlobalBaseReg();
518 Chain = CurDAG->getCopyToReg(Chain, Alpha::R29, GOT, InFlag);
519 InFlag = Chain.getValue(1);
520 Chain = SDOperand(CurDAG->getTargetNode(Alpha::BSR, MVT::Other, MVT::Flag,
521 Addr.getOperand(0), Chain, InFlag), 0);
523 AddToISelQueue(Addr);
524 Chain = CurDAG->getCopyToReg(Chain, Alpha::R27, Addr, InFlag);
525 InFlag = Chain.getValue(1);
526 Chain = SDOperand(CurDAG->getTargetNode(Alpha::JSR, MVT::Other, MVT::Flag,
529 InFlag = Chain.getValue(1);
531 std::vector<SDOperand> CallResults;
533 switch (N->getValueType(0)) {
534 default: assert(0 && "Unexpected ret value!");
535 case MVT::Other: break;
537 Chain = CurDAG->getCopyFromReg(Chain, Alpha::R0, MVT::i64, InFlag).getValue(1);
538 CallResults.push_back(Chain.getValue(0));
541 Chain = CurDAG->getCopyFromReg(Chain, Alpha::F0, MVT::f32, InFlag).getValue(1);
542 CallResults.push_back(Chain.getValue(0));
545 Chain = CurDAG->getCopyFromReg(Chain, Alpha::F0, MVT::f64, InFlag).getValue(1);
546 CallResults.push_back(Chain.getValue(0));
550 CallResults.push_back(Chain);
551 for (unsigned i = 0, e = CallResults.size(); i != e; ++i)
552 ReplaceUses(Op.getValue(i), CallResults[i]);
556 /// createAlphaISelDag - This pass converts a legalized DAG into a
557 /// Alpha-specific DAG, ready for instruction scheduling.
559 FunctionPass *llvm::createAlphaISelDag(TargetMachine &TM) {
560 return new AlphaDAGToDAGISel(TM);