1 //===-- AlphaISelDAGToDAG.cpp - Alpha pattern matching inst selector ------===//
3 // The LLVM Compiler Infrastructure
5 // This file was developed by Andrew Lenharth and is distributed under
6 // the University of Illinois Open Source License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines a pattern matching instruction selector for Alpha,
11 // converting from a legalized dag to a Alpha dag.
13 //===----------------------------------------------------------------------===//
16 #include "AlphaTargetMachine.h"
17 #include "AlphaISelLowering.h"
18 #include "llvm/CodeGen/MachineInstrBuilder.h"
19 #include "llvm/CodeGen/MachineFrameInfo.h"
20 #include "llvm/CodeGen/MachineFunction.h"
21 #include "llvm/CodeGen/SSARegMap.h"
22 #include "llvm/CodeGen/SelectionDAG.h"
23 #include "llvm/CodeGen/SelectionDAGISel.h"
24 #include "llvm/Target/TargetOptions.h"
25 #include "llvm/ADT/Statistic.h"
26 #include "llvm/Constants.h"
27 #include "llvm/GlobalValue.h"
28 #include "llvm/Support/Debug.h"
29 #include "llvm/Support/MathExtras.h"
37 //===--------------------------------------------------------------------===//
38 /// AlphaDAGToDAGISel - Alpha specific code to select Alpha machine
39 /// instructions for SelectionDAG operations.
40 class AlphaDAGToDAGISel : public SelectionDAGISel {
41 AlphaTargetLowering AlphaLowering;
43 static const int64_t IMM_LOW = -32768;
44 static const int64_t IMM_HIGH = 32767;
45 static const int64_t IMM_MULT = 65536;
46 static const int64_t IMM_FULLHIGH = IMM_HIGH + IMM_HIGH * IMM_MULT;
47 static const int64_t IMM_FULLLOW = IMM_LOW + IMM_LOW * IMM_MULT;
49 static int64_t get_ldah16(int64_t x) {
50 int64_t y = x / IMM_MULT;
51 if (x % IMM_MULT > IMM_HIGH)
56 static int64_t get_lda16(int64_t x) {
57 return x - get_ldah16(x) * IMM_MULT;
60 static uint64_t get_zapImm(uint64_t x) {
61 unsigned int build = 0;
62 for(int i = 0; i < 8; ++i)
64 if ((x & 0x00FF) == 0x00FF)
66 else if ((x & 0x00FF) != 0)
73 static bool isFPZ(SDOperand N) {
74 ConstantFPSDNode *CN = dyn_cast<ConstantFPSDNode>(N);
75 return (CN && (CN->isExactlyValue(+0.0) || CN->isExactlyValue(-0.0)));
77 static bool isFPZn(SDOperand N) {
78 ConstantFPSDNode *CN = dyn_cast<ConstantFPSDNode>(N);
79 return (CN && CN->isExactlyValue(-0.0));
81 static bool isFPZp(SDOperand N) {
82 ConstantFPSDNode *CN = dyn_cast<ConstantFPSDNode>(N);
83 return (CN && CN->isExactlyValue(+0.0));
87 AlphaDAGToDAGISel(TargetMachine &TM)
88 : SelectionDAGISel(AlphaLowering), AlphaLowering(TM)
91 /// getI64Imm - Return a target constant with the specified value, of type
93 inline SDOperand getI64Imm(int64_t Imm) {
94 return CurDAG->getTargetConstant(Imm, MVT::i64);
97 // Select - Convert the specified operand from a target-independent to a
98 // target-specific node if it hasn't already been changed.
99 SDOperand Select(SDOperand Op);
101 /// InstructionSelectBasicBlock - This callback is invoked by
102 /// SelectionDAGISel when it has created a SelectionDAG for us to codegen.
103 virtual void InstructionSelectBasicBlock(SelectionDAG &DAG);
105 virtual const char *getPassName() const {
106 return "Alpha DAG->DAG Pattern Instruction Selection";
109 // Include the pieces autogenerated from the target description.
110 #include "AlphaGenDAGISel.inc"
113 SDOperand getGlobalBaseReg();
114 SDOperand getRASaveReg();
115 SDOperand SelectCALL(SDOperand Op);
120 /// getGlobalBaseReg - Output the instructions required to put the
121 /// GOT address into a register.
123 SDOperand AlphaDAGToDAGISel::getGlobalBaseReg() {
124 return CurDAG->getCopyFromReg(CurDAG->getEntryNode(),
125 AlphaLowering.getVRegGP(),
129 /// getRASaveReg - Grab the return address
131 SDOperand AlphaDAGToDAGISel::getRASaveReg() {
132 return CurDAG->getCopyFromReg(CurDAG->getEntryNode(),
133 AlphaLowering.getVRegRA(),
137 /// InstructionSelectBasicBlock - This callback is invoked by
138 /// SelectionDAGISel when it has created a SelectionDAG for us to codegen.
139 void AlphaDAGToDAGISel::InstructionSelectBasicBlock(SelectionDAG &DAG) {
142 // Select target instructions for the DAG.
143 DAG.setRoot(SelectRoot(DAG.getRoot()));
145 DAG.RemoveDeadNodes();
147 // Emit machine code to BB.
148 ScheduleAndEmitDAG(DAG);
151 // Select - Convert the specified operand from a target-independent to a
152 // target-specific node if it hasn't already been changed.
153 SDOperand AlphaDAGToDAGISel::Select(SDOperand Op) {
155 if (N->getOpcode() >= ISD::BUILTIN_OP_END &&
156 N->getOpcode() < AlphaISD::FIRST_NUMBER)
157 return Op; // Already selected.
159 // If this has already been converted, use it.
160 std::map<SDOperand, SDOperand>::iterator CGMI = CodeGenMap.find(Op);
161 if (CGMI != CodeGenMap.end()) return CGMI->second;
163 switch (N->getOpcode()) {
165 case AlphaISD::CALL: return SelectCALL(Op);
167 case ISD::FrameIndex: {
168 int FI = cast<FrameIndexSDNode>(N)->getIndex();
169 return CurDAG->SelectNodeTo(N, Alpha::LDA, MVT::i64,
170 CurDAG->getTargetFrameIndex(FI, MVT::i32),
173 case AlphaISD::GlobalBaseReg:
174 return getGlobalBaseReg();
176 case AlphaISD::DivCall: {
177 SDOperand Chain = CurDAG->getEntryNode();
178 Chain = CurDAG->getCopyToReg(Chain, Alpha::R24, Select(Op.getOperand(1)),
180 Chain = CurDAG->getCopyToReg(Chain, Alpha::R25, Select(Op.getOperand(2)),
182 Chain = CurDAG->getCopyToReg(Chain, Alpha::R27, Select(Op.getOperand(0)),
184 Chain = CurDAG->getTargetNode(Alpha::JSRs, MVT::Other, MVT::Flag,
185 Chain, Chain.getValue(1));
186 Chain = CurDAG->getCopyFromReg(Chain, Alpha::R27, MVT::i64,
188 return CurDAG->SelectNodeTo(N, Alpha::BIS, MVT::i64, Chain, Chain);
191 case ISD::READCYCLECOUNTER: {
192 SDOperand Chain = Select(N->getOperand(0)); //Select chain
193 return CurDAG->SelectNodeTo(N, Alpha::RPCC, MVT::i64, Chain);
197 SDOperand Chain = Select(N->getOperand(0)); // Token chain.
200 if (N->getNumOperands() == 2) {
201 SDOperand Val = Select(N->getOperand(1));
202 if (N->getOperand(1).getValueType() == MVT::i64) {
203 Chain = CurDAG->getCopyToReg(Chain, Alpha::R0, Val, InFlag);
204 InFlag = Chain.getValue(1);
205 } else if (N->getOperand(1).getValueType() == MVT::f64 ||
206 N->getOperand(1).getValueType() == MVT::f32) {
207 Chain = CurDAG->getCopyToReg(Chain, Alpha::F0, Val, InFlag);
208 InFlag = Chain.getValue(1);
211 Chain = CurDAG->getCopyToReg(Chain, Alpha::R26, getRASaveReg(), InFlag);
212 InFlag = Chain.getValue(1);
214 // Finally, select this to a ret instruction.
215 return CurDAG->SelectNodeTo(N, Alpha::RETDAG, MVT::Other, Chain, InFlag);
217 case ISD::Constant: {
218 uint64_t uval = cast<ConstantSDNode>(N)->getValue();
221 return CurDAG->getCopyFromReg(CurDAG->getEntryNode(), Alpha::R31, MVT::i64);
223 int64_t val = (int64_t)uval;
224 int32_t val32 = (int32_t)val;
225 if (val <= IMM_HIGH + IMM_HIGH * IMM_MULT &&
226 val >= IMM_LOW + IMM_LOW * IMM_MULT)
227 break; //(LDAH (LDA))
228 if ((uval >> 32) == 0 && //empty upper bits
229 val32 <= IMM_HIGH + IMM_HIGH * IMM_MULT)
230 // val32 >= IMM_LOW + IMM_LOW * IMM_MULT) //always true
231 break; //(zext (LDAH (LDA)))
232 //Else use the constant pool
233 MachineConstantPool *CP = BB->getParent()->getConstantPool();
235 ConstantUInt::get(Type::getPrimitiveType(Type::ULongTyID) , uval);
236 SDOperand Tmp, CPI = CurDAG->getTargetConstantPool(C, MVT::i64);
237 Tmp = CurDAG->getTargetNode(Alpha::LDAHr, MVT::i64, CPI, getGlobalBaseReg());
238 return CurDAG->SelectNodeTo(N, Alpha::LDQr, MVT::i64, MVT::Other,
239 CPI, Tmp, CurDAG->getEntryNode());
241 case ISD::TargetConstantFP: {
242 ConstantFPSDNode *CN = cast<ConstantFPSDNode>(N);
243 bool isDouble = N->getValueType(0) == MVT::f64;
244 MVT::ValueType T = isDouble ? MVT::f64 : MVT::f32;
245 if (CN->isExactlyValue(+0.0)) {
246 return CurDAG->SelectNodeTo(N, isDouble ? Alpha::CPYST : Alpha::CPYSS,
247 T, CurDAG->getRegister(Alpha::F31, T),
248 CurDAG->getRegister(Alpha::F31, T));
249 } else if ( CN->isExactlyValue(-0.0)) {
250 return CurDAG->SelectNodeTo(N, isDouble ? Alpha::CPYSNT : Alpha::CPYSNS,
251 T, CurDAG->getRegister(Alpha::F31, T),
252 CurDAG->getRegister(Alpha::F31, T));
260 if (MVT::isFloatingPoint(N->getOperand(0).Val->getValueType(0))) {
261 unsigned Opc = Alpha::WTF;
262 ISD::CondCode CC = cast<CondCodeSDNode>(N->getOperand(2))->get();
266 default: N->dump(); assert(0 && "Unknown FP comparison!");
267 case ISD::SETEQ: Opc = Alpha::CMPTEQ; break;
268 case ISD::SETLT: Opc = Alpha::CMPTLT; break;
269 case ISD::SETLE: Opc = Alpha::CMPTLE; break;
270 case ISD::SETGT: Opc = Alpha::CMPTLT; rev = true; break;
271 case ISD::SETGE: Opc = Alpha::CMPTLE; rev = true; break;
272 case ISD::SETNE: Opc = Alpha::CMPTEQ; isNE = true; break;
274 SDOperand tmp1 = Select(N->getOperand(0)),
275 tmp2 = Select(N->getOperand(1));
276 SDOperand cmp = CurDAG->getTargetNode(Opc, MVT::f64,
280 cmp = CurDAG->getTargetNode(Alpha::CMPTEQ, MVT::f64, cmp,
281 CurDAG->getRegister(Alpha::F31, MVT::f64));
284 if (AlphaLowering.hasITOF()) {
285 LD = CurDAG->getNode(AlphaISD::FTOIT_, MVT::i64, cmp);
288 CurDAG->getMachineFunction().getFrameInfo()->CreateStackObject(8, 8);
289 SDOperand FI = CurDAG->getFrameIndex(FrameIdx, MVT::i64);
290 SDOperand ST = CurDAG->getTargetNode(Alpha::STT, MVT::Other,
291 cmp, FI, CurDAG->getRegister(Alpha::R31, MVT::i64));
292 LD = CurDAG->getTargetNode(Alpha::LDQ, MVT::i64, FI,
293 CurDAG->getRegister(Alpha::R31, MVT::i64),
296 SDOperand FP = CurDAG->getTargetNode(Alpha::CMPULT, MVT::i64,
297 CurDAG->getRegister(Alpha::R31, MVT::i64),
304 if (MVT::isFloatingPoint(N->getValueType(0)) &&
305 (N->getOperand(0).getOpcode() != ISD::SETCC ||
306 !MVT::isFloatingPoint(N->getOperand(0).getOperand(1).getValueType()))) {
307 //This should be the condition not covered by the Patterns
308 //FIXME: Don't have SelectCode die, but rather return something testable
309 // so that things like this can be caught in fall though code
311 bool isDouble = N->getValueType(0) == MVT::f64;
313 cond = Select(N->getOperand(0)),
314 TV = Select(N->getOperand(1)),
315 FV = Select(N->getOperand(2));
317 if (AlphaLowering.hasITOF()) {
318 LD = CurDAG->getNode(AlphaISD::ITOFT_, MVT::f64, cond);
321 CurDAG->getMachineFunction().getFrameInfo()->CreateStackObject(8, 8);
322 SDOperand FI = CurDAG->getFrameIndex(FrameIdx, MVT::i64);
323 SDOperand ST = CurDAG->getTargetNode(Alpha::STQ, MVT::Other,
324 cond, FI, CurDAG->getRegister(Alpha::R31, MVT::i64));
325 LD = CurDAG->getTargetNode(Alpha::LDT, MVT::f64, FI,
326 CurDAG->getRegister(Alpha::R31, MVT::i64),
329 SDOperand FP = CurDAG->getTargetNode(isDouble?Alpha::FCMOVNET:Alpha::FCMOVNES,
330 MVT::f64, FV, TV, LD);
337 return SelectCode(Op);
340 SDOperand AlphaDAGToDAGISel::SelectCALL(SDOperand Op) {
341 //TODO: add flag stuff to prevent nondeturministic breakage!
344 SDOperand Chain = Select(N->getOperand(0));
345 SDOperand Addr = N->getOperand(1);
346 SDOperand InFlag; // Null incoming flag value.
348 std::vector<SDOperand> CallOperands;
349 std::vector<MVT::ValueType> TypeOperands;
352 for(int i = 2, e = N->getNumOperands(); i < e; ++i) {
353 TypeOperands.push_back(N->getOperand(i).getValueType());
354 CallOperands.push_back(Select(N->getOperand(i)));
356 int count = N->getNumOperands() - 2;
358 static const unsigned args_int[] = {Alpha::R16, Alpha::R17, Alpha::R18,
359 Alpha::R19, Alpha::R20, Alpha::R21};
360 static const unsigned args_float[] = {Alpha::F16, Alpha::F17, Alpha::F18,
361 Alpha::F19, Alpha::F20, Alpha::F21};
363 for (int i = 6; i < count; ++i) {
364 unsigned Opc = Alpha::WTF;
365 if (MVT::isInteger(TypeOperands[i])) {
367 } else if (TypeOperands[i] == MVT::f32) {
369 } else if (TypeOperands[i] == MVT::f64) {
372 assert(0 && "Unknown operand");
373 Chain = CurDAG->getTargetNode(Opc, MVT::Other, CallOperands[i],
374 getI64Imm((i - 6) * 8),
375 CurDAG->getCopyFromReg(Chain, Alpha::R30, MVT::i64),
378 for (int i = 0; i < std::min(6, count); ++i) {
379 if (MVT::isInteger(TypeOperands[i])) {
380 Chain = CurDAG->getCopyToReg(Chain, args_int[i], CallOperands[i], InFlag);
381 InFlag = Chain.getValue(1);
382 } else if (TypeOperands[i] == MVT::f32 || TypeOperands[i] == MVT::f64) {
383 Chain = CurDAG->getCopyToReg(Chain, args_float[i], CallOperands[i], InFlag);
384 InFlag = Chain.getValue(1);
386 assert(0 && "Unknown operand");
390 // Finally, once everything is in registers to pass to the call, emit the
392 if (Addr.getOpcode() == AlphaISD::GPRelLo) {
393 SDOperand GOT = getGlobalBaseReg();
394 Chain = CurDAG->getCopyToReg(Chain, Alpha::R29, GOT, InFlag);
395 InFlag = Chain.getValue(1);
396 Chain = CurDAG->getTargetNode(Alpha::BSR, MVT::Other, MVT::Flag,
397 Addr.getOperand(0), Chain, InFlag);
399 Chain = CurDAG->getCopyToReg(Chain, Alpha::R27, Select(Addr), InFlag);
400 InFlag = Chain.getValue(1);
401 Chain = CurDAG->getTargetNode(Alpha::JSR, MVT::Other, MVT::Flag,
404 InFlag = Chain.getValue(1);
406 std::vector<SDOperand> CallResults;
408 switch (N->getValueType(0)) {
409 default: assert(0 && "Unexpected ret value!");
410 case MVT::Other: break;
412 Chain = CurDAG->getCopyFromReg(Chain, Alpha::R0, MVT::i64, InFlag).getValue(1);
413 CallResults.push_back(Chain.getValue(0));
416 Chain = CurDAG->getCopyFromReg(Chain, Alpha::F0, MVT::f32, InFlag).getValue(1);
417 CallResults.push_back(Chain.getValue(0));
420 Chain = CurDAG->getCopyFromReg(Chain, Alpha::F0, MVT::f64, InFlag).getValue(1);
421 CallResults.push_back(Chain.getValue(0));
425 CallResults.push_back(Chain);
426 for (unsigned i = 0, e = CallResults.size(); i != e; ++i)
427 CodeGenMap[Op.getValue(i)] = CallResults[i];
428 return CallResults[Op.ResNo];
432 /// createAlphaISelDag - This pass converts a legalized DAG into a
433 /// Alpha-specific DAG, ready for instruction scheduling.
435 FunctionPass *llvm::createAlphaISelDag(TargetMachine &TM) {
436 return new AlphaDAGToDAGISel(TM);