1 //===-- AlphaISelDAGToDAG.cpp - Alpha pattern matching inst selector ------===//
3 // The LLVM Compiler Infrastructure
5 // This file was developed by Andrew Lenharth and is distributed under
6 // the University of Illinois Open Source License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines a pattern matching instruction selector for Alpha,
11 // converting from a legalized dag to a Alpha dag.
13 //===----------------------------------------------------------------------===//
16 #include "AlphaTargetMachine.h"
17 #include "AlphaISelLowering.h"
18 #include "llvm/CodeGen/MachineInstrBuilder.h"
19 #include "llvm/CodeGen/MachineFrameInfo.h"
20 #include "llvm/CodeGen/MachineFunction.h"
21 #include "llvm/CodeGen/SSARegMap.h"
22 #include "llvm/CodeGen/SelectionDAG.h"
23 #include "llvm/CodeGen/SelectionDAGISel.h"
24 #include "llvm/Target/TargetOptions.h"
25 #include "llvm/ADT/Statistic.h"
26 #include "llvm/Constants.h"
27 #include "llvm/GlobalValue.h"
28 #include "llvm/Intrinsics.h"
29 #include "llvm/Support/Debug.h"
30 #include "llvm/Support/MathExtras.h"
39 //===--------------------------------------------------------------------===//
40 /// AlphaDAGToDAGISel - Alpha specific code to select Alpha machine
41 /// instructions for SelectionDAG operations.
42 class AlphaDAGToDAGISel : public SelectionDAGISel {
43 AlphaTargetLowering AlphaLowering;
45 static const int64_t IMM_LOW = -32768;
46 static const int64_t IMM_HIGH = 32767;
47 static const int64_t IMM_MULT = 65536;
48 static const int64_t IMM_FULLHIGH = IMM_HIGH + IMM_HIGH * IMM_MULT;
49 static const int64_t IMM_FULLLOW = IMM_LOW + IMM_LOW * IMM_MULT;
51 static int64_t get_ldah16(int64_t x) {
52 int64_t y = x / IMM_MULT;
53 if (x % IMM_MULT > IMM_HIGH)
58 static int64_t get_lda16(int64_t x) {
59 return x - get_ldah16(x) * IMM_MULT;
62 /// get_zapImm - Return a zap mask if X is a valid immediate for a zapnot
63 /// instruction (if not, return 0). Note that this code accepts partial
64 /// zap masks. For example (and LHS, 1) is a valid zap, as long we know
65 /// that the bits 1-7 of LHS are already zero. If LHS is non-null, we are
66 /// in checking mode. If LHS is null, we assume that the mask has already
67 /// been validated before.
68 uint64_t get_zapImm(SDOperand LHS, uint64_t Constant) {
69 uint64_t BitsToCheck = 0;
71 for (unsigned i = 0; i != 8; ++i) {
72 if (((Constant >> 8*i) & 0xFF) == 0) {
76 if (((Constant >> 8*i) & 0xFF) == 0xFF) {
77 // If the entire byte is set, zapnot the byte.
78 } else if (LHS.Val == 0) {
79 // Otherwise, if the mask was previously validated, we know its okay
80 // to zapnot this entire byte even though all the bits aren't set.
82 // Otherwise we don't know that the it's okay to zapnot this entire
83 // byte. Only do this iff we can prove that the missing bits are
84 // already null, so the bytezap doesn't need to really null them.
85 BitsToCheck |= ~Constant & (0xFF << 8*i);
90 // If there are missing bits in a byte (for example, X & 0xEF00), check to
91 // see if the missing bits (0x1000) are already known zero if not, the zap
92 // isn't okay to do, as it won't clear all the required bits.
94 !getTargetLowering().MaskedValueIsZero(LHS, BitsToCheck))
100 static uint64_t get_zapImm(uint64_t x) {
102 for(int i = 0; i != 8; ++i) {
103 if ((x & 0x00FF) == 0x00FF)
105 else if ((x & 0x00FF) != 0)
113 static uint64_t getNearPower2(uint64_t x) {
115 unsigned at = CountLeadingZeros_64(x);
116 uint64_t complow = 1 << (63 - at);
117 uint64_t comphigh = 1 << (64 - at);
118 //std::cerr << x << ":" << complow << ":" << comphigh << "\n";
119 if (abs(complow - x) <= abs(comphigh - x))
125 static bool isFPZ(SDOperand N) {
126 ConstantFPSDNode *CN = dyn_cast<ConstantFPSDNode>(N);
127 return (CN && (CN->isExactlyValue(+0.0) || CN->isExactlyValue(-0.0)));
129 static bool isFPZn(SDOperand N) {
130 ConstantFPSDNode *CN = dyn_cast<ConstantFPSDNode>(N);
131 return (CN && CN->isExactlyValue(-0.0));
133 static bool isFPZp(SDOperand N) {
134 ConstantFPSDNode *CN = dyn_cast<ConstantFPSDNode>(N);
135 return (CN && CN->isExactlyValue(+0.0));
139 AlphaDAGToDAGISel(TargetMachine &TM)
140 : SelectionDAGISel(AlphaLowering),
141 AlphaLowering(*(AlphaTargetLowering*)(TM.getTargetLowering()))
144 /// getI64Imm - Return a target constant with the specified value, of type
146 inline SDOperand getI64Imm(int64_t Imm) {
147 return CurDAG->getTargetConstant(Imm, MVT::i64);
150 // Select - Convert the specified operand from a target-independent to a
151 // target-specific node if it hasn't already been changed.
152 SDNode *Select(SDOperand Op);
154 /// InstructionSelectBasicBlock - This callback is invoked by
155 /// SelectionDAGISel when it has created a SelectionDAG for us to codegen.
156 virtual void InstructionSelectBasicBlock(SelectionDAG &DAG);
158 virtual const char *getPassName() const {
159 return "Alpha DAG->DAG Pattern Instruction Selection";
162 /// SelectInlineAsmMemoryOperand - Implement addressing mode selection for
163 /// inline asm expressions.
164 virtual bool SelectInlineAsmMemoryOperand(const SDOperand &Op,
166 std::vector<SDOperand> &OutOps,
169 switch (ConstraintCode) {
170 default: return true;
177 OutOps.push_back(Op0);
181 // Include the pieces autogenerated from the target description.
182 #include "AlphaGenDAGISel.inc"
185 SDOperand getGlobalBaseReg();
186 SDOperand getGlobalRetAddr();
187 void SelectCALL(SDOperand Op);
192 /// getGlobalBaseReg - Output the instructions required to put the
193 /// GOT address into a register.
195 SDOperand AlphaDAGToDAGISel::getGlobalBaseReg() {
196 return CurDAG->getCopyFromReg(CurDAG->getEntryNode(),
197 AlphaLowering.getVRegGP(),
201 /// getRASaveReg - Grab the return address
203 SDOperand AlphaDAGToDAGISel::getGlobalRetAddr() {
204 return CurDAG->getCopyFromReg(CurDAG->getEntryNode(),
205 AlphaLowering.getVRegRA(),
209 /// InstructionSelectBasicBlock - This callback is invoked by
210 /// SelectionDAGISel when it has created a SelectionDAG for us to codegen.
211 void AlphaDAGToDAGISel::InstructionSelectBasicBlock(SelectionDAG &DAG) {
214 // Select target instructions for the DAG.
215 DAG.setRoot(SelectRoot(DAG.getRoot()));
216 DAG.RemoveDeadNodes();
218 // Emit machine code to BB.
219 ScheduleAndEmitDAG(DAG);
222 // Select - Convert the specified operand from a target-independent to a
223 // target-specific node if it hasn't already been changed.
224 SDNode *AlphaDAGToDAGISel::Select(SDOperand Op) {
226 if (N->getOpcode() >= ISD::BUILTIN_OP_END &&
227 N->getOpcode() < AlphaISD::FIRST_NUMBER) {
228 return NULL; // Already selected.
231 switch (N->getOpcode()) {
237 case ISD::FrameIndex: {
238 int FI = cast<FrameIndexSDNode>(N)->getIndex();
239 return CurDAG->SelectNodeTo(N, Alpha::LDA, MVT::i64,
240 CurDAG->getTargetFrameIndex(FI, MVT::i32),
243 case ISD::GLOBAL_OFFSET_TABLE: {
244 SDOperand Result = getGlobalBaseReg();
245 ReplaceUses(Op, Result);
248 case AlphaISD::GlobalRetAddr: {
249 SDOperand Result = getGlobalRetAddr();
250 ReplaceUses(Op, Result);
254 case AlphaISD::DivCall: {
255 SDOperand Chain = CurDAG->getEntryNode();
256 SDOperand N0 = Op.getOperand(0);
257 SDOperand N1 = Op.getOperand(1);
258 SDOperand N2 = Op.getOperand(2);
262 Chain = CurDAG->getCopyToReg(Chain, Alpha::R24, N1,
264 Chain = CurDAG->getCopyToReg(Chain, Alpha::R25, N2,
266 Chain = CurDAG->getCopyToReg(Chain, Alpha::R27, N0,
269 CurDAG->getTargetNode(Alpha::JSRs, MVT::Other, MVT::Flag,
270 Chain, Chain.getValue(1));
271 Chain = CurDAG->getCopyFromReg(Chain, Alpha::R27, MVT::i64,
272 SDOperand(CNode, 1));
273 return CurDAG->SelectNodeTo(N, Alpha::BIS, MVT::i64, Chain, Chain);
276 case ISD::READCYCLECOUNTER: {
277 SDOperand Chain = N->getOperand(0);
278 AddToISelQueue(Chain); //Select chain
279 return CurDAG->getTargetNode(Alpha::RPCC, MVT::i64, MVT::Other,
283 case ISD::Constant: {
284 uint64_t uval = cast<ConstantSDNode>(N)->getValue();
287 SDOperand Result = CurDAG->getCopyFromReg(CurDAG->getEntryNode(),
288 Alpha::R31, MVT::i64);
289 ReplaceUses(Op, Result);
293 int64_t val = (int64_t)uval;
294 int32_t val32 = (int32_t)val;
295 if (val <= IMM_HIGH + IMM_HIGH * IMM_MULT &&
296 val >= IMM_LOW + IMM_LOW * IMM_MULT)
297 break; //(LDAH (LDA))
298 if ((uval >> 32) == 0 && //empty upper bits
299 val32 <= IMM_HIGH + IMM_HIGH * IMM_MULT)
300 // val32 >= IMM_LOW + IMM_LOW * IMM_MULT) //always true
301 break; //(zext (LDAH (LDA)))
302 //Else use the constant pool
303 MachineConstantPool *CP = BB->getParent()->getConstantPool();
305 ConstantUInt::get(Type::getPrimitiveType(Type::ULongTyID) , uval);
306 SDOperand CPI = CurDAG->getTargetConstantPool(C, MVT::i64);
307 SDNode *Tmp = CurDAG->getTargetNode(Alpha::LDAHr, MVT::i64, CPI,
309 return CurDAG->SelectNodeTo(N, Alpha::LDQr, MVT::i64, MVT::Other,
310 CPI, SDOperand(Tmp, 0), CurDAG->getEntryNode());
312 case ISD::TargetConstantFP: {
313 ConstantFPSDNode *CN = cast<ConstantFPSDNode>(N);
314 bool isDouble = N->getValueType(0) == MVT::f64;
315 MVT::ValueType T = isDouble ? MVT::f64 : MVT::f32;
316 if (CN->isExactlyValue(+0.0)) {
317 return CurDAG->SelectNodeTo(N, isDouble ? Alpha::CPYST : Alpha::CPYSS,
318 T, CurDAG->getRegister(Alpha::F31, T),
319 CurDAG->getRegister(Alpha::F31, T));
320 } else if ( CN->isExactlyValue(-0.0)) {
321 return CurDAG->SelectNodeTo(N, isDouble ? Alpha::CPYSNT : Alpha::CPYSNS,
322 T, CurDAG->getRegister(Alpha::F31, T),
323 CurDAG->getRegister(Alpha::F31, T));
331 if (MVT::isFloatingPoint(N->getOperand(0).Val->getValueType(0))) {
332 unsigned Opc = Alpha::WTF;
333 ISD::CondCode CC = cast<CondCodeSDNode>(N->getOperand(2))->get();
337 default: DEBUG(N->dump()); assert(0 && "Unknown FP comparison!");
338 case ISD::SETEQ: case ISD::SETOEQ: case ISD::SETUEQ: Opc = Alpha::CMPTEQ; break;
339 case ISD::SETLT: case ISD::SETOLT: case ISD::SETULT: Opc = Alpha::CMPTLT; break;
340 case ISD::SETLE: case ISD::SETOLE: case ISD::SETULE: Opc = Alpha::CMPTLE; break;
341 case ISD::SETGT: case ISD::SETOGT: case ISD::SETUGT: Opc = Alpha::CMPTLT; rev = true; break;
342 case ISD::SETGE: case ISD::SETOGE: case ISD::SETUGE: Opc = Alpha::CMPTLE; rev = true; break;
343 case ISD::SETNE: case ISD::SETONE: case ISD::SETUNE: Opc = Alpha::CMPTEQ; isNE = true; break;
345 SDOperand tmp1 = N->getOperand(0);
346 SDOperand tmp2 = N->getOperand(1);
347 AddToISelQueue(tmp1);
348 AddToISelQueue(tmp2);
349 SDNode *cmp = CurDAG->getTargetNode(Opc, MVT::f64,
353 cmp = CurDAG->getTargetNode(Alpha::CMPTEQ, MVT::f64, SDOperand(cmp, 0),
354 CurDAG->getRegister(Alpha::F31, MVT::f64));
357 if (AlphaLowering.hasITOF()) {
358 LD = CurDAG->getNode(AlphaISD::FTOIT_, MVT::i64, SDOperand(cmp, 0));
361 CurDAG->getMachineFunction().getFrameInfo()->CreateStackObject(8, 8);
362 SDOperand FI = CurDAG->getFrameIndex(FrameIdx, MVT::i64);
364 SDOperand(CurDAG->getTargetNode(Alpha::STT, MVT::Other,
365 SDOperand(cmp, 0), FI,
366 CurDAG->getRegister(Alpha::R31, MVT::i64)), 0);
367 LD = SDOperand(CurDAG->getTargetNode(Alpha::LDQ, MVT::i64, FI,
368 CurDAG->getRegister(Alpha::R31, MVT::i64),
371 return CurDAG->getTargetNode(Alpha::CMPULT, MVT::i64,
372 CurDAG->getRegister(Alpha::R31, MVT::i64),
378 if (MVT::isFloatingPoint(N->getValueType(0)) &&
379 (N->getOperand(0).getOpcode() != ISD::SETCC ||
380 !MVT::isFloatingPoint(N->getOperand(0).getOperand(1).getValueType()))) {
381 //This should be the condition not covered by the Patterns
382 //FIXME: Don't have SelectCode die, but rather return something testable
383 // so that things like this can be caught in fall though code
385 bool isDouble = N->getValueType(0) == MVT::f64;
387 SDOperand cond = N->getOperand(0);
388 SDOperand TV = N->getOperand(1);
389 SDOperand FV = N->getOperand(2);
390 AddToISelQueue(cond);
394 if (AlphaLowering.hasITOF()) {
395 LD = CurDAG->getNode(AlphaISD::ITOFT_, MVT::f64, cond);
398 CurDAG->getMachineFunction().getFrameInfo()->CreateStackObject(8, 8);
399 SDOperand FI = CurDAG->getFrameIndex(FrameIdx, MVT::i64);
401 SDOperand(CurDAG->getTargetNode(Alpha::STQ, MVT::Other,
402 cond, FI, CurDAG->getRegister(Alpha::R31, MVT::i64)), 0);
403 LD = SDOperand(CurDAG->getTargetNode(Alpha::LDT, MVT::f64, FI,
404 CurDAG->getRegister(Alpha::R31, MVT::i64),
407 return CurDAG->getTargetNode(isDouble?Alpha::FCMOVNET:Alpha::FCMOVNES,
408 MVT::f64, FV, TV, LD);
413 ConstantSDNode* SC = NULL;
414 ConstantSDNode* MC = NULL;
415 if (N->getOperand(0).getOpcode() == ISD::SRL &&
416 (MC = dyn_cast<ConstantSDNode>(N->getOperand(1))) &&
417 (SC = dyn_cast<ConstantSDNode>(N->getOperand(0).getOperand(1))))
419 uint64_t sval = SC->getValue();
420 uint64_t mval = MC->getValue();
421 // If the result is a zap, let the autogened stuff handle it.
422 if (get_zapImm(N->getOperand(0), mval))
424 // given mask X, and shift S, we want to see if there is any zap in the
425 // mask if we play around with the botton S bits
426 uint64_t dontcare = (~0ULL) >> (64 - sval);
427 uint64_t mask = mval << sval;
429 if (get_zapImm(mask | dontcare))
430 mask = mask | dontcare;
432 if (get_zapImm(mask)) {
433 AddToISelQueue(N->getOperand(0).getOperand(0));
435 SDOperand(CurDAG->getTargetNode(Alpha::ZAPNOTi, MVT::i64,
436 N->getOperand(0).getOperand(0),
437 getI64Imm(get_zapImm(mask))), 0);
438 return CurDAG->getTargetNode(Alpha::SRL, MVT::i64, Z,
447 return SelectCode(Op);
450 void AlphaDAGToDAGISel::SelectCALL(SDOperand Op) {
451 //TODO: add flag stuff to prevent nondeturministic breakage!
454 SDOperand Chain = N->getOperand(0);
455 SDOperand Addr = N->getOperand(1);
456 SDOperand InFlag(0,0); // Null incoming flag value.
457 AddToISelQueue(Chain);
459 std::vector<SDOperand> CallOperands;
460 std::vector<MVT::ValueType> TypeOperands;
463 for(int i = 2, e = N->getNumOperands(); i < e; ++i) {
464 TypeOperands.push_back(N->getOperand(i).getValueType());
465 AddToISelQueue(N->getOperand(i));
466 CallOperands.push_back(N->getOperand(i));
468 int count = N->getNumOperands() - 2;
470 static const unsigned args_int[] = {Alpha::R16, Alpha::R17, Alpha::R18,
471 Alpha::R19, Alpha::R20, Alpha::R21};
472 static const unsigned args_float[] = {Alpha::F16, Alpha::F17, Alpha::F18,
473 Alpha::F19, Alpha::F20, Alpha::F21};
475 for (int i = 6; i < count; ++i) {
476 unsigned Opc = Alpha::WTF;
477 if (MVT::isInteger(TypeOperands[i])) {
479 } else if (TypeOperands[i] == MVT::f32) {
481 } else if (TypeOperands[i] == MVT::f64) {
484 assert(0 && "Unknown operand");
486 SDOperand Ops[] = { CallOperands[i], getI64Imm((i - 6) * 8),
487 CurDAG->getCopyFromReg(Chain, Alpha::R30, MVT::i64),
489 Chain = SDOperand(CurDAG->getTargetNode(Opc, MVT::Other, Ops, 4), 0);
491 for (int i = 0; i < std::min(6, count); ++i) {
492 if (MVT::isInteger(TypeOperands[i])) {
493 Chain = CurDAG->getCopyToReg(Chain, args_int[i], CallOperands[i], InFlag);
494 InFlag = Chain.getValue(1);
495 } else if (TypeOperands[i] == MVT::f32 || TypeOperands[i] == MVT::f64) {
496 Chain = CurDAG->getCopyToReg(Chain, args_float[i], CallOperands[i], InFlag);
497 InFlag = Chain.getValue(1);
499 assert(0 && "Unknown operand");
502 // Finally, once everything is in registers to pass to the call, emit the
504 if (Addr.getOpcode() == AlphaISD::GPRelLo) {
505 SDOperand GOT = getGlobalBaseReg();
506 Chain = CurDAG->getCopyToReg(Chain, Alpha::R29, GOT, InFlag);
507 InFlag = Chain.getValue(1);
508 Chain = SDOperand(CurDAG->getTargetNode(Alpha::BSR, MVT::Other, MVT::Flag,
509 Addr.getOperand(0), Chain, InFlag), 0);
511 AddToISelQueue(Addr);
512 Chain = CurDAG->getCopyToReg(Chain, Alpha::R27, Addr, InFlag);
513 InFlag = Chain.getValue(1);
514 Chain = SDOperand(CurDAG->getTargetNode(Alpha::JSR, MVT::Other, MVT::Flag,
517 InFlag = Chain.getValue(1);
519 std::vector<SDOperand> CallResults;
521 switch (N->getValueType(0)) {
522 default: assert(0 && "Unexpected ret value!");
523 case MVT::Other: break;
525 Chain = CurDAG->getCopyFromReg(Chain, Alpha::R0, MVT::i64, InFlag).getValue(1);
526 CallResults.push_back(Chain.getValue(0));
529 Chain = CurDAG->getCopyFromReg(Chain, Alpha::F0, MVT::f32, InFlag).getValue(1);
530 CallResults.push_back(Chain.getValue(0));
533 Chain = CurDAG->getCopyFromReg(Chain, Alpha::F0, MVT::f64, InFlag).getValue(1);
534 CallResults.push_back(Chain.getValue(0));
538 CallResults.push_back(Chain);
539 for (unsigned i = 0, e = CallResults.size(); i != e; ++i)
540 ReplaceUses(Op.getValue(i), CallResults[i]);
544 /// createAlphaISelDag - This pass converts a legalized DAG into a
545 /// Alpha-specific DAG, ready for instruction scheduling.
547 FunctionPass *llvm::createAlphaISelDag(TargetMachine &TM) {
548 return new AlphaDAGToDAGISel(TM);