1 //===-- AlphaISelLowering.cpp - Alpha DAG Lowering Implementation ---------===//
3 // The LLVM Compiler Infrastructure
5 // This file was developed by Andrew Lenharth and is distributed under
6 // the University of Illinois Open Source License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file implements the AlphaISelLowering class.
12 //===----------------------------------------------------------------------===//
14 #include "AlphaISelLowering.h"
15 #include "AlphaTargetMachine.h"
16 #include "llvm/CodeGen/MachineFrameInfo.h"
17 #include "llvm/CodeGen/MachineFunction.h"
18 #include "llvm/CodeGen/MachineInstrBuilder.h"
19 #include "llvm/CodeGen/SelectionDAG.h"
20 #include "llvm/CodeGen/SSARegMap.h"
21 #include "llvm/Constants.h"
22 #include "llvm/Function.h"
23 #include "llvm/Module.h"
24 #include "llvm/Support/CommandLine.h"
30 extern cl::opt<bool> EnableAlphaIDIV;
31 extern cl::opt<bool> EnableAlphaCount;
32 extern cl::opt<bool> EnableAlphaLSMark;
35 /// AddLiveIn - This helper function adds the specified physical register to the
36 /// MachineFunction as a live in value. It also creates a corresponding virtual
38 static unsigned AddLiveIn(MachineFunction &MF, unsigned PReg,
39 TargetRegisterClass *RC) {
40 assert(RC->contains(PReg) && "Not the correct regclass!");
41 unsigned VReg = MF.getSSARegMap()->createVirtualRegister(RC);
42 MF.addLiveIn(PReg, VReg);
46 AlphaTargetLowering::AlphaTargetLowering(TargetMachine &TM) : TargetLowering(TM) {
47 // Set up the TargetLowering object.
48 //I am having problems with shr n ubyte 1
49 setShiftAmountType(MVT::i64);
50 setSetCCResultType(MVT::i64);
51 setSetCCResultContents(ZeroOrOneSetCCResult);
53 addRegisterClass(MVT::i64, Alpha::GPRCRegisterClass);
54 addRegisterClass(MVT::f64, Alpha::F8RCRegisterClass);
55 addRegisterClass(MVT::f32, Alpha::F4RCRegisterClass);
57 setOperationAction(ISD::BRCONDTWOWAY, MVT::Other, Expand);
58 setOperationAction(ISD::BRTWOWAY_CC, MVT::Other, Expand);
60 setOperationAction(ISD::EXTLOAD, MVT::i1, Promote);
61 setOperationAction(ISD::EXTLOAD, MVT::f32, Expand);
63 setOperationAction(ISD::ZEXTLOAD, MVT::i1, Promote);
64 setOperationAction(ISD::ZEXTLOAD, MVT::i32, Expand);
66 setOperationAction(ISD::SEXTLOAD, MVT::i1, Promote);
67 setOperationAction(ISD::SEXTLOAD, MVT::i8, Expand);
68 setOperationAction(ISD::SEXTLOAD, MVT::i16, Expand);
70 setOperationAction(ISD::TRUNCSTORE, MVT::i1, Promote);
72 if (EnableAlphaLSMark) {
73 setOperationAction(ISD::LOAD, MVT::i64, Custom);
74 setOperationAction(ISD::LOAD, MVT::f64, Custom);
75 setOperationAction(ISD::LOAD, MVT::f32, Custom);
77 setOperationAction(ISD::ZEXTLOAD, MVT::i8, Custom);
78 setOperationAction(ISD::ZEXTLOAD, MVT::i16, Custom);
79 setOperationAction(ISD::SEXTLOAD, MVT::i32, Custom);
81 setOperationAction(ISD::EXTLOAD, MVT::i8, Custom);
82 setOperationAction(ISD::EXTLOAD, MVT::i16, Custom);
83 setOperationAction(ISD::EXTLOAD, MVT::i32, Custom);
86 setOperationAction(ISD::FREM, MVT::f32, Expand);
87 setOperationAction(ISD::FREM, MVT::f64, Expand);
89 setOperationAction(ISD::UINT_TO_FP, MVT::i64, Expand);
90 setOperationAction(ISD::SINT_TO_FP, MVT::i64, Custom);
91 setOperationAction(ISD::FP_TO_UINT, MVT::i64, Expand);
92 setOperationAction(ISD::FP_TO_SINT, MVT::i64, Custom);
94 if (!TM.getSubtarget<AlphaSubtarget>().hasCT()) {
95 setOperationAction(ISD::CTPOP , MVT::i64 , Expand);
96 setOperationAction(ISD::CTTZ , MVT::i64 , Expand);
97 setOperationAction(ISD::CTLZ , MVT::i64 , Expand);
99 setOperationAction(ISD::BSWAP , MVT::i64, Expand);
100 setOperationAction(ISD::ROTL , MVT::i64, Expand);
101 setOperationAction(ISD::ROTR , MVT::i64, Expand);
103 setOperationAction(ISD::SREM , MVT::i64, Custom);
104 setOperationAction(ISD::UREM , MVT::i64, Custom);
105 setOperationAction(ISD::SDIV , MVT::i64, Custom);
106 setOperationAction(ISD::UDIV , MVT::i64, Custom);
108 setOperationAction(ISD::MEMMOVE , MVT::Other, Expand);
109 setOperationAction(ISD::MEMSET , MVT::Other, Expand);
110 setOperationAction(ISD::MEMCPY , MVT::Other, Expand);
112 // We don't support sin/cos/sqrt
113 setOperationAction(ISD::FSIN , MVT::f64, Expand);
114 setOperationAction(ISD::FCOS , MVT::f64, Expand);
115 setOperationAction(ISD::FSIN , MVT::f32, Expand);
116 setOperationAction(ISD::FCOS , MVT::f32, Expand);
118 setOperationAction(ISD::FSQRT, MVT::f64, Expand);
119 setOperationAction(ISD::FSQRT, MVT::f32, Expand);
121 setOperationAction(ISD::SETCC, MVT::f32, Promote);
123 // We don't have line number support yet.
124 setOperationAction(ISD::LOCATION, MVT::Other, Expand);
125 setOperationAction(ISD::DEBUG_LOC, MVT::Other, Expand);
126 setOperationAction(ISD::DEBUG_LABEL, MVT::Other, Expand);
128 // Not implemented yet.
129 setOperationAction(ISD::STACKSAVE, MVT::Other, Expand);
130 setOperationAction(ISD::STACKRESTORE, MVT::Other, Expand);
131 setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i64, Expand);
133 // We want to legalize GlobalAddress and ConstantPool and
134 // ExternalSymbols nodes into the appropriate instructions to
135 // materialize the address.
136 setOperationAction(ISD::GlobalAddress, MVT::i64, Custom);
137 setOperationAction(ISD::ConstantPool, MVT::i64, Custom);
138 setOperationAction(ISD::ExternalSymbol, MVT::i64, Custom);
140 setStackPointerRegisterToSaveRestore(Alpha::R30);
142 addLegalFPImmediate(+0.0); //F31
143 addLegalFPImmediate(-0.0); //-F31
145 computeRegisterProperties();
147 useITOF = TM.getSubtarget<AlphaSubtarget>().hasF2I();
150 const char *AlphaTargetLowering::getTargetNodeName(unsigned Opcode) const {
153 case AlphaISD::ITOFT_: return "Alpha::ITOFT_";
154 case AlphaISD::FTOIT_: return "Alpha::FTOIT_";
155 case AlphaISD::CVTQT_: return "Alpha::CVTQT_";
156 case AlphaISD::CVTQS_: return "Alpha::CVTQS_";
157 case AlphaISD::CVTTQ_: return "Alpha::CVTTQ_";
158 case AlphaISD::GPRelHi: return "Alpha::GPRelHi";
159 case AlphaISD::GPRelLo: return "Alpha::GPRelLo";
160 case AlphaISD::RelLit: return "Alpha::RelLit";
161 case AlphaISD::GlobalBaseReg: return "Alpha::GlobalBaseReg";
162 case AlphaISD::DivCall: return "Alpha::DivCall";
163 case AlphaISD::LDQ_: return "Alpha::LDQ_";
164 case AlphaISD::LDT_: return "Alpha::LDT_";
165 case AlphaISD::LDS_: return "Alpha::LDS_";
166 case AlphaISD::LDL_: return "Alpha::LDL_";
167 case AlphaISD::LDWU_: return "Alpha::LDWU_";
168 case AlphaISD::LDBU_: return "Alpha::LDBU_";
169 case AlphaISD::STQ_: return "Alpha::STQ_";
170 case AlphaISD::STT_: return "Alpha::STT_";
171 case AlphaISD::STS_: return "Alpha::STS_";
172 case AlphaISD::STL_: return "Alpha::STL_";
173 case AlphaISD::STW_: return "Alpha::STW_";
174 case AlphaISD::STB_: return "Alpha::STB_";
178 //http://www.cs.arizona.edu/computer.help/policy/DIGITAL_unix/AA-PY8AC-TET1_html/callCH3.html#BLOCK21
180 //For now, just use variable size stack frame format
182 //In a standard call, the first six items are passed in registers $16
183 //- $21 and/or registers $f16 - $f21. (See Section 4.1.2 for details
184 //of argument-to-register correspondence.) The remaining items are
185 //collected in a memory argument list that is a naturally aligned
186 //array of quadwords. In a standard call, this list, if present, must
187 //be passed at 0(SP).
188 //7 ... n 0(SP) ... (n-7)*8(SP)
196 std::vector<SDOperand>
197 AlphaTargetLowering::LowerArguments(Function &F, SelectionDAG &DAG)
199 MachineFunction &MF = DAG.getMachineFunction();
200 MachineFrameInfo *MFI = MF.getFrameInfo();
201 MachineBasicBlock& BB = MF.front();
202 std::vector<SDOperand> ArgValues;
204 unsigned args_int[] = {
205 Alpha::R16, Alpha::R17, Alpha::R18, Alpha::R19, Alpha::R20, Alpha::R21};
206 unsigned args_float[] = {
207 Alpha::F16, Alpha::F17, Alpha::F18, Alpha::F19, Alpha::F20, Alpha::F21};
211 GP = AddLiveIn(MF, Alpha::R29, getRegClassFor(MVT::i64));
212 RA = AddLiveIn(MF, Alpha::R26, getRegClassFor(MVT::i64));
214 for (Function::arg_iterator I = F.arg_begin(), E = F.arg_end(); I != E; ++I)
219 MVT::ValueType VT = getValueType(I->getType());
222 std::cerr << "Unknown Type " << VT << "\n";
226 args_float[count] = AddLiveIn(MF, args_float[count], getRegClassFor(VT));
227 argt = DAG.getCopyFromReg(DAG.getRoot(), args_float[count], VT);
228 DAG.setRoot(argt.getValue(1));
235 args_int[count] = AddLiveIn(MF, args_int[count], getRegClassFor(MVT::i64));
236 argt = DAG.getCopyFromReg(DAG.getRoot(), args_int[count], MVT::i64);
237 DAG.setRoot(argt.getValue(1));
238 if (VT != MVT::i64) {
240 I->getType()->isSigned() ? ISD::AssertSext : ISD::AssertZext;
241 argt = DAG.getNode(AssertOp, MVT::i64, argt,
242 DAG.getValueType(VT));
243 argt = DAG.getNode(ISD::TRUNCATE, VT, argt);
248 // Create the frame index object for this incoming parameter...
249 int FI = MFI->CreateFixedObject(8, 8 * (count - 6));
251 // Create the SelectionDAG nodes corresponding to a load
252 //from this parameter
253 SDOperand FIN = DAG.getFrameIndex(FI, MVT::i64);
254 argt = DAG.getLoad(getValueType(I->getType()),
255 DAG.getEntryNode(), FIN, DAG.getSrcValue(NULL));
258 ArgValues.push_back(argt);
261 // If the functions takes variable number of arguments, copy all regs to stack
263 VarArgsOffset = count * 8;
264 std::vector<SDOperand> LS;
265 for (int i = 0; i < 6; ++i) {
266 if (MRegisterInfo::isPhysicalRegister(args_int[i]))
267 args_int[i] = AddLiveIn(MF, args_int[i], getRegClassFor(MVT::i64));
268 SDOperand argt = DAG.getCopyFromReg(DAG.getRoot(), args_int[i], MVT::i64);
269 int FI = MFI->CreateFixedObject(8, -8 * (6 - i));
270 if (i == 0) VarArgsBase = FI;
271 SDOperand SDFI = DAG.getFrameIndex(FI, MVT::i64);
272 LS.push_back(DAG.getNode(ISD::STORE, MVT::Other, DAG.getRoot(), argt,
273 SDFI, DAG.getSrcValue(NULL)));
275 if (MRegisterInfo::isPhysicalRegister(args_float[i]))
276 args_float[i] = AddLiveIn(MF, args_float[i], getRegClassFor(MVT::f64));
277 argt = DAG.getCopyFromReg(DAG.getRoot(), args_float[i], MVT::f64);
278 FI = MFI->CreateFixedObject(8, - 8 * (12 - i));
279 SDFI = DAG.getFrameIndex(FI, MVT::i64);
280 LS.push_back(DAG.getNode(ISD::STORE, MVT::Other, DAG.getRoot(), argt,
281 SDFI, DAG.getSrcValue(NULL)));
284 //Set up a token factor with all the stack traffic
285 DAG.setRoot(DAG.getNode(ISD::TokenFactor, MVT::Other, LS));
288 // Finally, inform the code generator which regs we return values in.
289 switch (getValueType(F.getReturnType())) {
290 default: assert(0 && "Unknown type!");
291 case MVT::isVoid: break;
297 MF.addLiveOut(Alpha::R0);
301 MF.addLiveOut(Alpha::F0);
305 //return the arguments
309 std::pair<SDOperand, SDOperand>
310 AlphaTargetLowering::LowerCallTo(SDOperand Chain,
311 const Type *RetTy, bool isVarArg,
312 unsigned CallingConv, bool isTailCall,
313 SDOperand Callee, ArgListTy &Args,
317 NumBytes = (Args.size() - 6) * 8;
319 Chain = DAG.getNode(ISD::CALLSEQ_START, MVT::Other, Chain,
320 DAG.getConstant(NumBytes, getPointerTy()));
321 std::vector<SDOperand> args_to_use;
322 for (unsigned i = 0, e = Args.size(); i != e; ++i)
324 switch (getValueType(Args[i].second)) {
325 default: assert(0 && "Unexpected ValueType for argument!");
330 // Promote the integer to 64 bits. If the input type is signed use a
331 // sign extend, otherwise use a zero extend.
332 if (Args[i].second->isSigned())
333 Args[i].first = DAG.getNode(ISD::SIGN_EXTEND, MVT::i64, Args[i].first);
335 Args[i].first = DAG.getNode(ISD::ZERO_EXTEND, MVT::i64, Args[i].first);
342 args_to_use.push_back(Args[i].first);
345 std::vector<MVT::ValueType> RetVals;
346 MVT::ValueType RetTyVT = getValueType(RetTy);
347 MVT::ValueType ActualRetTyVT = RetTyVT;
348 if (RetTyVT >= MVT::i1 && RetTyVT <= MVT::i32)
349 ActualRetTyVT = MVT::i64;
351 if (RetTyVT != MVT::isVoid)
352 RetVals.push_back(ActualRetTyVT);
353 RetVals.push_back(MVT::Other);
355 SDOperand TheCall = SDOperand(DAG.getCall(RetVals,
356 Chain, Callee, args_to_use), 0);
357 Chain = TheCall.getValue(RetTyVT != MVT::isVoid);
358 Chain = DAG.getNode(ISD::CALLSEQ_END, MVT::Other, Chain,
359 DAG.getConstant(NumBytes, getPointerTy()));
360 SDOperand RetVal = TheCall;
362 if (RetTyVT != ActualRetTyVT) {
363 RetVal = DAG.getNode(RetTy->isSigned() ? ISD::AssertSext : ISD::AssertZext,
364 MVT::i64, RetVal, DAG.getValueType(RetTyVT));
365 RetVal = DAG.getNode(ISD::TRUNCATE, RetTyVT, RetVal);
368 return std::make_pair(RetVal, Chain);
371 SDOperand AlphaTargetLowering::LowerVAStart(SDOperand Chain, SDOperand VAListP,
372 Value *VAListV, SelectionDAG &DAG) {
373 // vastart stores the address of the VarArgsBase and VarArgsOffset
374 SDOperand FR = DAG.getFrameIndex(VarArgsBase, MVT::i64);
375 SDOperand S1 = DAG.getNode(ISD::STORE, MVT::Other, Chain, FR, VAListP,
376 DAG.getSrcValue(VAListV));
377 SDOperand SA2 = DAG.getNode(ISD::ADD, MVT::i64, VAListP,
378 DAG.getConstant(8, MVT::i64));
379 return DAG.getNode(ISD::TRUNCSTORE, MVT::Other, S1,
380 DAG.getConstant(VarArgsOffset, MVT::i64), SA2,
381 DAG.getSrcValue(VAListV, 8), DAG.getValueType(MVT::i32));
384 std::pair<SDOperand,SDOperand> AlphaTargetLowering::
385 LowerVAArg(SDOperand Chain, SDOperand VAListP, Value *VAListV,
386 const Type *ArgTy, SelectionDAG &DAG) {
387 SDOperand Base = DAG.getLoad(MVT::i64, Chain, VAListP,
388 DAG.getSrcValue(VAListV));
389 SDOperand Tmp = DAG.getNode(ISD::ADD, MVT::i64, VAListP,
390 DAG.getConstant(8, MVT::i64));
391 SDOperand Offset = DAG.getExtLoad(ISD::SEXTLOAD, MVT::i64, Base.getValue(1),
392 Tmp, DAG.getSrcValue(VAListV, 8), MVT::i32);
393 SDOperand DataPtr = DAG.getNode(ISD::ADD, MVT::i64, Base, Offset);
394 if (ArgTy->isFloatingPoint())
396 //if fp && Offset < 6*8, then subtract 6*8 from DataPtr
397 SDOperand FPDataPtr = DAG.getNode(ISD::SUB, MVT::i64, DataPtr,
398 DAG.getConstant(8*6, MVT::i64));
399 SDOperand CC = DAG.getSetCC(MVT::i64, Offset,
400 DAG.getConstant(8*6, MVT::i64), ISD::SETLT);
401 DataPtr = DAG.getNode(ISD::SELECT, MVT::i64, CC, FPDataPtr, DataPtr);
405 if (ArgTy == Type::IntTy)
406 Result = DAG.getExtLoad(ISD::SEXTLOAD, MVT::i64, Offset.getValue(1),
407 DataPtr, DAG.getSrcValue(NULL), MVT::i32);
408 else if (ArgTy == Type::UIntTy)
409 Result = DAG.getExtLoad(ISD::ZEXTLOAD, MVT::i64, Offset.getValue(1),
410 DataPtr, DAG.getSrcValue(NULL), MVT::i32);
412 Result = DAG.getLoad(getValueType(ArgTy), Offset.getValue(1), DataPtr,
413 DAG.getSrcValue(NULL));
415 SDOperand NewOffset = DAG.getNode(ISD::ADD, MVT::i64, Offset,
416 DAG.getConstant(8, MVT::i64));
417 SDOperand Update = DAG.getNode(ISD::TRUNCSTORE, MVT::Other,
418 Result.getValue(1), NewOffset,
419 Tmp, DAG.getSrcValue(VAListV, 8),
420 DAG.getValueType(MVT::i32));
421 Result = DAG.getNode(ISD::TRUNCATE, getValueType(ArgTy), Result);
423 return std::make_pair(Result, Update);
426 SDOperand AlphaTargetLowering::
427 LowerVACopy(SDOperand Chain, SDOperand SrcP, Value *SrcV, SDOperand DestP,
428 Value *DestV, SelectionDAG &DAG) {
429 SDOperand Val = DAG.getLoad(getPointerTy(), Chain, SrcP,
430 DAG.getSrcValue(SrcV));
431 SDOperand Result = DAG.getNode(ISD::STORE, MVT::Other, Val.getValue(1),
432 Val, DestP, DAG.getSrcValue(DestV));
433 SDOperand NP = DAG.getNode(ISD::ADD, MVT::i64, SrcP,
434 DAG.getConstant(8, MVT::i64));
435 Val = DAG.getExtLoad(ISD::SEXTLOAD, MVT::i64, Result, NP,
436 DAG.getSrcValue(SrcV, 8), MVT::i32);
437 SDOperand NPD = DAG.getNode(ISD::ADD, MVT::i64, DestP,
438 DAG.getConstant(8, MVT::i64));
439 return DAG.getNode(ISD::TRUNCSTORE, MVT::Other, Val.getValue(1),
440 Val, NPD, DAG.getSrcValue(DestV, 8),
441 DAG.getValueType(MVT::i32));
444 void AlphaTargetLowering::restoreGP(MachineBasicBlock* BB)
446 BuildMI(BB, Alpha::BIS, 2, Alpha::R29).addReg(GP).addReg(GP);
448 void AlphaTargetLowering::restoreRA(MachineBasicBlock* BB)
450 BuildMI(BB, Alpha::BIS, 2, Alpha::R26).addReg(RA).addReg(RA);
455 static void getValueInfo(const Value* v, int& type, int& fun, int& offset)
457 fun = type = offset = 0;
460 } else if (const GlobalValue* GV = dyn_cast<GlobalValue>(v)) {
462 const Module* M = GV->getParent();
463 for(Module::const_global_iterator ii = M->global_begin(); &*ii != GV; ++ii)
465 } else if (const Argument* Arg = dyn_cast<Argument>(v)) {
467 const Function* F = Arg->getParent();
468 const Module* M = F->getParent();
469 for(Module::const_iterator ii = M->begin(); &*ii != F; ++ii)
471 for(Function::const_arg_iterator ii = F->arg_begin(); &*ii != Arg; ++ii)
473 } else if (const Instruction* I = dyn_cast<Instruction>(v)) {
474 assert(dyn_cast<PointerType>(I->getType()));
476 const BasicBlock* bb = I->getParent();
477 const Function* F = bb->getParent();
478 const Module* M = F->getParent();
479 for(Module::const_iterator ii = M->begin(); &*ii != F; ++ii)
481 for(Function::const_iterator ii = F->begin(); &*ii != bb; ++ii)
482 offset += ii->size();
483 for(BasicBlock::const_iterator ii = bb->begin(); &*ii != I; ++ii)
485 } else if (const Constant* C = dyn_cast<Constant>(v)) {
486 //Don't know how to look these up yet
489 assert(0 && "Error in value marking");
491 //type = 4: register spilling
492 //type = 5: global address loading or constant loading
501 /// LowerOperation - Provide custom lowering hooks for some operations.
503 SDOperand AlphaTargetLowering::LowerOperation(SDOperand Op, SelectionDAG &DAG) {
504 switch (Op.getOpcode()) {
505 default: assert(0 && "Wasn't expecting to be able to lower this!");
506 case ISD::SINT_TO_FP: {
507 assert(MVT::i64 == Op.getOperand(0).getValueType() &&
508 "Unhandled SINT_TO_FP type in custom expander!");
510 bool isDouble = MVT::f64 == Op.getValueType();
512 LD = DAG.getNode(AlphaISD::ITOFT_, MVT::f64, Op.getOperand(0));
515 DAG.getMachineFunction().getFrameInfo()->CreateStackObject(8, 8);
516 SDOperand FI = DAG.getFrameIndex(FrameIdx, MVT::i64);
517 SDOperand ST = DAG.getNode(ISD::STORE, MVT::Other, DAG.getEntryNode(),
518 Op.getOperand(0), FI, DAG.getSrcValue(0));
519 LD = DAG.getLoad(MVT::f64, ST, FI, DAG.getSrcValue(0));
521 SDOperand FP = DAG.getNode(isDouble?AlphaISD::CVTQT_:AlphaISD::CVTQS_,
522 isDouble?MVT::f64:MVT::f32, LD);
525 case ISD::FP_TO_SINT: {
526 bool isDouble = MVT::f64 == Op.getOperand(0).getValueType();
527 SDOperand src = Op.getOperand(0);
529 if (!isDouble) //Promote
530 src = DAG.getNode(ISD::FP_EXTEND, MVT::f64, src);
532 src = DAG.getNode(AlphaISD::CVTTQ_, MVT::f64, src);
535 return DAG.getNode(AlphaISD::FTOIT_, MVT::i64, src);
538 DAG.getMachineFunction().getFrameInfo()->CreateStackObject(8, 8);
539 SDOperand FI = DAG.getFrameIndex(FrameIdx, MVT::i64);
540 SDOperand ST = DAG.getNode(ISD::STORE, MVT::Other, DAG.getEntryNode(),
541 src, FI, DAG.getSrcValue(0));
542 return DAG.getLoad(MVT::i64, ST, FI, DAG.getSrcValue(0));
545 case ISD::ConstantPool: {
546 Constant *C = cast<ConstantPoolSDNode>(Op)->get();
547 SDOperand CPI = DAG.getTargetConstantPool(C, MVT::i64);
549 SDOperand Hi = DAG.getNode(AlphaISD::GPRelHi, MVT::i64, CPI,
550 DAG.getNode(AlphaISD::GlobalBaseReg, MVT::i64));
551 SDOperand Lo = DAG.getNode(AlphaISD::GPRelLo, MVT::i64, CPI, Hi);
554 case ISD::GlobalAddress: {
555 GlobalAddressSDNode *GSDN = cast<GlobalAddressSDNode>(Op);
556 GlobalValue *GV = GSDN->getGlobal();
557 SDOperand GA = DAG.getTargetGlobalAddress(GV, MVT::i64, GSDN->getOffset());
559 if (!GV->hasWeakLinkage() && !GV->isExternal()) {
560 SDOperand Hi = DAG.getNode(AlphaISD::GPRelHi, MVT::i64, GA,
561 DAG.getNode(AlphaISD::GlobalBaseReg, MVT::i64));
562 SDOperand Lo = DAG.getNode(AlphaISD::GPRelLo, MVT::i64, GA, Hi);
565 return DAG.getNode(AlphaISD::RelLit, MVT::i64, GA, DAG.getNode(AlphaISD::GlobalBaseReg, MVT::i64));
567 case ISD::ExternalSymbol: {
568 return DAG.getNode(AlphaISD::RelLit, MVT::i64,
569 DAG.getTargetExternalSymbol(cast<ExternalSymbolSDNode>(Op)->getSymbol(), MVT::i64),
570 DAG.getNode(AlphaISD::GlobalBaseReg, MVT::i64));
577 if (MVT::isInteger(Op.getValueType())) {
578 const char* opstr = 0;
579 switch(Op.getOpcode()) {
580 case ISD::UREM: opstr = "__remqu"; break;
581 case ISD::SREM: opstr = "__remq"; break;
582 case ISD::UDIV: opstr = "__divqu"; break;
583 case ISD::SDIV: opstr = "__divq"; break;
585 SDOperand Tmp1 = Op.getOperand(0),
586 Tmp2 = Op.getOperand(1),
587 Addr = DAG.getExternalSymbol(opstr, MVT::i64);
588 return DAG.getNode(AlphaISD::DivCall, MVT::i64, Addr, Tmp1, Tmp2);
597 SDOperand Chain = Op.getOperand(0);
598 SDOperand Address = Op.getOperand(1);
601 unsigned opcode = Op.getOpcode();
603 if (opcode == ISD::LOAD)
604 switch (Op.Val->getValueType(0)) {
605 default: Op.Val->dump(); assert(0 && "Bad load!");
606 case MVT::i64: Opc = AlphaISD::LDQ_; break;
607 case MVT::f64: Opc = AlphaISD::LDT_; break;
608 case MVT::f32: Opc = AlphaISD::LDS_; break;
611 switch (cast<VTSDNode>(Op.getOperand(3))->getVT()) {
612 default: Op.Val->dump(); assert(0 && "Bad sign extend!");
613 case MVT::i32: Opc = AlphaISD::LDL_;
614 assert(opcode != ISD::ZEXTLOAD && "Not sext"); break;
615 case MVT::i16: Opc = AlphaISD::LDWU_;
616 assert(opcode != ISD::SEXTLOAD && "Not zext"); break;
617 case MVT::i1: //FIXME: Treat i1 as i8 since there are problems otherwise
618 case MVT::i8: Opc = AlphaISD::LDBU_;
619 assert(opcode != ISD::SEXTLOAD && "Not zext"); break;
623 getValueInfo(dyn_cast<SrcValueSDNode>(Op.getOperand(2))->getValue(), i, j, k);
625 SDOperand Zero = DAG.getConstant(0, MVT::i64);
626 std::vector<MVT::ValueType> VTS;
627 VTS.push_back(Op.Val->getValueType(0));
628 VTS.push_back(MVT::Other);
629 std::vector<SDOperand> ARGS;
630 ARGS.push_back(Chain);
631 ARGS.push_back(Zero);
632 ARGS.push_back(Address);
633 ARGS.push_back(DAG.getConstant(i, MVT::i64));
634 ARGS.push_back(DAG.getConstant(j, MVT::i64));
635 ARGS.push_back(DAG.getConstant(k, MVT::i64));
636 ARGS.push_back(DAG.getConstant(getUID(), MVT::i64));
637 return DAG.getNode(Opc, VTS, ARGS);
640 case ISD::TRUNCSTORE:
643 SDOperand Chain = Op.getOperand(0);
644 SDOperand Value = Op.getOperand(1);
645 SDOperand Address = Op.getOperand(2);
648 unsigned opcode = Op.getOpcode();
650 if (opcode == ISD::STORE) {
651 switch(Value.getValueType()) {
652 default: assert(0 && "unknown Type in store");
653 case MVT::i64: Opc = AlphaISD::STQ_; break;
654 case MVT::f64: Opc = AlphaISD::STT_; break;
655 case MVT::f32: Opc = AlphaISD::STS_; break;
657 } else { //ISD::TRUNCSTORE
658 switch(cast<VTSDNode>(Op.getOperand(4))->getVT()) {
659 default: assert(0 && "unknown Type in store");
660 case MVT::i8: Opc = AlphaISD::STB_; break;
661 case MVT::i16: Opc = AlphaISD::STW_; break;
662 case MVT::i32: Opc = AlphaISD::STL_; break;
667 getValueInfo(cast<SrcValueSDNode>(Op.getOperand(3))->getValue(), i, j, k);
669 SDOperand Zero = DAG.getConstant(0, MVT::i64);
670 std::vector<MVT::ValueType> VTS;
671 VTS.push_back(MVT::Other);
672 std::vector<SDOperand> ARGS;
673 ARGS.push_back(Chain);
674 ARGS.push_back(Value);
675 ARGS.push_back(Zero);
676 ARGS.push_back(Address);
677 ARGS.push_back(DAG.getConstant(i, MVT::i64));
678 ARGS.push_back(DAG.getConstant(j, MVT::i64));
679 ARGS.push_back(DAG.getConstant(k, MVT::i64));
680 ARGS.push_back(DAG.getConstant(getUID(), MVT::i64));
681 return DAG.getNode(Opc, VTS, ARGS);