1 //===-- AlphaISelLowering.cpp - Alpha DAG Lowering Implementation ---------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file implements the AlphaISelLowering class.
12 //===----------------------------------------------------------------------===//
14 #include "AlphaISelLowering.h"
15 #include "AlphaTargetMachine.h"
16 #include "llvm/CodeGen/MachineFrameInfo.h"
17 #include "llvm/CodeGen/MachineFunction.h"
18 #include "llvm/CodeGen/MachineInstrBuilder.h"
19 #include "llvm/CodeGen/MachineRegisterInfo.h"
20 #include "llvm/CodeGen/SelectionDAG.h"
21 #include "llvm/CodeGen/MachineRegisterInfo.h"
22 #include "llvm/Constants.h"
23 #include "llvm/Function.h"
24 #include "llvm/Module.h"
25 #include "llvm/Support/CommandLine.h"
28 /// AddLiveIn - This helper function adds the specified physical register to the
29 /// MachineFunction as a live in value. It also creates a corresponding virtual
31 static unsigned AddLiveIn(MachineFunction &MF, unsigned PReg,
32 TargetRegisterClass *RC) {
33 assert(RC->contains(PReg) && "Not the correct regclass!");
34 unsigned VReg = MF.getRegInfo().createVirtualRegister(RC);
35 MF.getRegInfo().addLiveIn(PReg, VReg);
39 AlphaTargetLowering::AlphaTargetLowering(TargetMachine &TM) : TargetLowering(TM) {
40 // Set up the TargetLowering object.
41 //I am having problems with shr n ubyte 1
42 setShiftAmountType(MVT::i64);
43 setSetCCResultContents(ZeroOrOneSetCCResult);
45 setUsesGlobalOffsetTable(true);
47 addRegisterClass(MVT::i64, Alpha::GPRCRegisterClass);
48 addRegisterClass(MVT::f64, Alpha::F8RCRegisterClass);
49 addRegisterClass(MVT::f32, Alpha::F4RCRegisterClass);
51 setLoadXAction(ISD::EXTLOAD, MVT::i1, Promote);
52 setLoadXAction(ISD::EXTLOAD, MVT::f32, Expand);
54 setLoadXAction(ISD::ZEXTLOAD, MVT::i1, Promote);
55 setLoadXAction(ISD::ZEXTLOAD, MVT::i32, Expand);
57 setLoadXAction(ISD::SEXTLOAD, MVT::i1, Promote);
58 setLoadXAction(ISD::SEXTLOAD, MVT::i8, Expand);
59 setLoadXAction(ISD::SEXTLOAD, MVT::i16, Expand);
61 // setOperationAction(ISD::BRIND, MVT::Other, Expand);
62 setOperationAction(ISD::BR_JT, MVT::Other, Expand);
63 setOperationAction(ISD::BR_CC, MVT::Other, Expand);
64 setOperationAction(ISD::SELECT_CC, MVT::Other, Expand);
66 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1, Expand);
68 setOperationAction(ISD::FREM, MVT::f32, Expand);
69 setOperationAction(ISD::FREM, MVT::f64, Expand);
71 setOperationAction(ISD::UINT_TO_FP, MVT::i64, Expand);
72 setOperationAction(ISD::SINT_TO_FP, MVT::i64, Custom);
73 setOperationAction(ISD::FP_TO_UINT, MVT::i64, Expand);
74 setOperationAction(ISD::FP_TO_SINT, MVT::i64, Custom);
76 if (!TM.getSubtarget<AlphaSubtarget>().hasCT()) {
77 setOperationAction(ISD::CTPOP , MVT::i64 , Expand);
78 setOperationAction(ISD::CTTZ , MVT::i64 , Expand);
79 setOperationAction(ISD::CTLZ , MVT::i64 , Expand);
81 setOperationAction(ISD::BSWAP , MVT::i64, Expand);
82 setOperationAction(ISD::ROTL , MVT::i64, Expand);
83 setOperationAction(ISD::ROTR , MVT::i64, Expand);
85 setOperationAction(ISD::SREM , MVT::i64, Custom);
86 setOperationAction(ISD::UREM , MVT::i64, Custom);
87 setOperationAction(ISD::SDIV , MVT::i64, Custom);
88 setOperationAction(ISD::UDIV , MVT::i64, Custom);
90 // We don't support sin/cos/sqrt/pow
91 setOperationAction(ISD::FSIN , MVT::f64, Expand);
92 setOperationAction(ISD::FCOS , MVT::f64, Expand);
93 setOperationAction(ISD::FSIN , MVT::f32, Expand);
94 setOperationAction(ISD::FCOS , MVT::f32, Expand);
96 setOperationAction(ISD::FSQRT, MVT::f64, Expand);
97 setOperationAction(ISD::FSQRT, MVT::f32, Expand);
99 setOperationAction(ISD::FPOW , MVT::f32, Expand);
100 setOperationAction(ISD::FPOW , MVT::f64, Expand);
102 setOperationAction(ISD::FLOG, MVT::f32, Expand);
103 setOperationAction(ISD::FLOG, MVT::f64, Expand);
104 setOperationAction(ISD::FLOG2, MVT::f32, Expand);
105 setOperationAction(ISD::FLOG2, MVT::f64, Expand);
106 setOperationAction(ISD::FLOG10, MVT::f32, Expand);
107 setOperationAction(ISD::FLOG10, MVT::f64, Expand);
108 setOperationAction(ISD::FEXP, MVT::f32, Expand);
109 setOperationAction(ISD::FEXP, MVT::f64, Expand);
110 setOperationAction(ISD::FEXP2, MVT::f32, Expand);
111 setOperationAction(ISD::FEXP2, MVT::f64, Expand);
113 setOperationAction(ISD::SETCC, MVT::f32, Promote);
115 setOperationAction(ISD::BIT_CONVERT, MVT::f32, Promote);
117 // We don't have line number support yet.
118 setOperationAction(ISD::DBG_STOPPOINT, MVT::Other, Expand);
119 setOperationAction(ISD::DEBUG_LOC, MVT::Other, Expand);
120 setOperationAction(ISD::DBG_LABEL, MVT::Other, Expand);
121 setOperationAction(ISD::EH_LABEL, MVT::Other, Expand);
123 // Not implemented yet.
124 setOperationAction(ISD::STACKSAVE, MVT::Other, Expand);
125 setOperationAction(ISD::STACKRESTORE, MVT::Other, Expand);
126 setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i64, Expand);
128 // We want to legalize GlobalAddress and ConstantPool and
129 // ExternalSymbols nodes into the appropriate instructions to
130 // materialize the address.
131 setOperationAction(ISD::GlobalAddress, MVT::i64, Custom);
132 setOperationAction(ISD::ConstantPool, MVT::i64, Custom);
133 setOperationAction(ISD::ExternalSymbol, MVT::i64, Custom);
134 setOperationAction(ISD::GlobalTLSAddress, MVT::i64, Custom);
136 setOperationAction(ISD::VASTART, MVT::Other, Custom);
137 setOperationAction(ISD::VAEND, MVT::Other, Expand);
138 setOperationAction(ISD::VACOPY, MVT::Other, Custom);
139 setOperationAction(ISD::VAARG, MVT::Other, Custom);
140 setOperationAction(ISD::VAARG, MVT::i32, Custom);
142 setOperationAction(ISD::RET, MVT::Other, Custom);
144 setOperationAction(ISD::JumpTable, MVT::i64, Custom);
145 setOperationAction(ISD::JumpTable, MVT::i32, Custom);
147 setStackPointerRegisterToSaveRestore(Alpha::R30);
149 addLegalFPImmediate(APFloat(+0.0)); //F31
150 addLegalFPImmediate(APFloat(+0.0f)); //F31
151 addLegalFPImmediate(APFloat(-0.0)); //-F31
152 addLegalFPImmediate(APFloat(-0.0f)); //-F31
155 setJumpBufAlignment(16);
157 computeRegisterProperties();
160 MVT AlphaTargetLowering::getSetCCResultType(const SDValue &) const {
164 const char *AlphaTargetLowering::getTargetNodeName(unsigned Opcode) const {
167 case AlphaISD::CVTQT_: return "Alpha::CVTQT_";
168 case AlphaISD::CVTQS_: return "Alpha::CVTQS_";
169 case AlphaISD::CVTTQ_: return "Alpha::CVTTQ_";
170 case AlphaISD::GPRelHi: return "Alpha::GPRelHi";
171 case AlphaISD::GPRelLo: return "Alpha::GPRelLo";
172 case AlphaISD::RelLit: return "Alpha::RelLit";
173 case AlphaISD::GlobalRetAddr: return "Alpha::GlobalRetAddr";
174 case AlphaISD::CALL: return "Alpha::CALL";
175 case AlphaISD::DivCall: return "Alpha::DivCall";
176 case AlphaISD::RET_FLAG: return "Alpha::RET_FLAG";
177 case AlphaISD::COND_BRANCH_I: return "Alpha::COND_BRANCH_I";
178 case AlphaISD::COND_BRANCH_F: return "Alpha::COND_BRANCH_F";
182 static SDValue LowerJumpTable(SDValue Op, SelectionDAG &DAG) {
183 MVT PtrVT = Op.getValueType();
184 JumpTableSDNode *JT = cast<JumpTableSDNode>(Op);
185 SDValue JTI = DAG.getTargetJumpTable(JT->getIndex(), PtrVT);
186 SDValue Zero = DAG.getConstant(0, PtrVT);
188 SDValue Hi = DAG.getNode(AlphaISD::GPRelHi, MVT::i64, JTI,
189 DAG.getNode(ISD::GLOBAL_OFFSET_TABLE, MVT::i64));
190 SDValue Lo = DAG.getNode(AlphaISD::GPRelLo, MVT::i64, JTI, Hi);
194 //http://www.cs.arizona.edu/computer.help/policy/DIGITAL_unix/
195 //AA-PY8AC-TET1_html/callCH3.html#BLOCK21
197 //For now, just use variable size stack frame format
199 //In a standard call, the first six items are passed in registers $16
200 //- $21 and/or registers $f16 - $f21. (See Section 4.1.2 for details
201 //of argument-to-register correspondence.) The remaining items are
202 //collected in a memory argument list that is a naturally aligned
203 //array of quadwords. In a standard call, this list, if present, must
204 //be passed at 0(SP).
205 //7 ... n 0(SP) ... (n-7)*8(SP)
213 static SDValue LowerFORMAL_ARGUMENTS(SDValue Op, SelectionDAG &DAG,
215 int &VarArgsOffset) {
216 MachineFunction &MF = DAG.getMachineFunction();
217 MachineFrameInfo *MFI = MF.getFrameInfo();
218 std::vector<SDValue> ArgValues;
219 SDValue Root = Op.getOperand(0);
221 AddLiveIn(MF, Alpha::R29, &Alpha::GPRCRegClass); //GP
222 AddLiveIn(MF, Alpha::R26, &Alpha::GPRCRegClass); //RA
224 unsigned args_int[] = {
225 Alpha::R16, Alpha::R17, Alpha::R18, Alpha::R19, Alpha::R20, Alpha::R21};
226 unsigned args_float[] = {
227 Alpha::F16, Alpha::F17, Alpha::F18, Alpha::F19, Alpha::F20, Alpha::F21};
229 for (unsigned ArgNo = 0, e = Op.getNode()->getNumValues()-1; ArgNo != e; ++ArgNo) {
231 MVT ObjectVT = Op.getValue(ArgNo).getValueType();
235 switch (ObjectVT.getSimpleVT()) {
237 assert(false && "Invalid value type!");
239 args_float[ArgNo] = AddLiveIn(MF, args_float[ArgNo],
240 &Alpha::F8RCRegClass);
241 ArgVal = DAG.getCopyFromReg(Root, args_float[ArgNo], ObjectVT);
244 args_float[ArgNo] = AddLiveIn(MF, args_float[ArgNo],
245 &Alpha::F4RCRegClass);
246 ArgVal = DAG.getCopyFromReg(Root, args_float[ArgNo], ObjectVT);
249 args_int[ArgNo] = AddLiveIn(MF, args_int[ArgNo],
250 &Alpha::GPRCRegClass);
251 ArgVal = DAG.getCopyFromReg(Root, args_int[ArgNo], MVT::i64);
255 // Create the frame index object for this incoming parameter...
256 int FI = MFI->CreateFixedObject(8, 8 * (ArgNo - 6));
258 // Create the SelectionDAG nodes corresponding to a load
259 //from this parameter
260 SDValue FIN = DAG.getFrameIndex(FI, MVT::i64);
261 ArgVal = DAG.getLoad(ObjectVT, Root, FIN, NULL, 0);
263 ArgValues.push_back(ArgVal);
266 // If the functions takes variable number of arguments, copy all regs to stack
267 bool isVarArg = cast<ConstantSDNode>(Op.getOperand(2))->getZExtValue() != 0;
269 VarArgsOffset = (Op.getNode()->getNumValues()-1) * 8;
270 std::vector<SDValue> LS;
271 for (int i = 0; i < 6; ++i) {
272 if (TargetRegisterInfo::isPhysicalRegister(args_int[i]))
273 args_int[i] = AddLiveIn(MF, args_int[i], &Alpha::GPRCRegClass);
274 SDValue argt = DAG.getCopyFromReg(Root, args_int[i], MVT::i64);
275 int FI = MFI->CreateFixedObject(8, -8 * (6 - i));
276 if (i == 0) VarArgsBase = FI;
277 SDValue SDFI = DAG.getFrameIndex(FI, MVT::i64);
278 LS.push_back(DAG.getStore(Root, argt, SDFI, NULL, 0));
280 if (TargetRegisterInfo::isPhysicalRegister(args_float[i]))
281 args_float[i] = AddLiveIn(MF, args_float[i], &Alpha::F8RCRegClass);
282 argt = DAG.getCopyFromReg(Root, args_float[i], MVT::f64);
283 FI = MFI->CreateFixedObject(8, - 8 * (12 - i));
284 SDFI = DAG.getFrameIndex(FI, MVT::i64);
285 LS.push_back(DAG.getStore(Root, argt, SDFI, NULL, 0));
288 //Set up a token factor with all the stack traffic
289 Root = DAG.getNode(ISD::TokenFactor, MVT::Other, &LS[0], LS.size());
292 ArgValues.push_back(Root);
294 // Return the new list of results.
295 return DAG.getMergeValues(Op.getNode()->getVTList(), &ArgValues[0],
299 static SDValue LowerRET(SDValue Op, SelectionDAG &DAG) {
300 SDValue Copy = DAG.getCopyToReg(Op.getOperand(0), Alpha::R26,
301 DAG.getNode(AlphaISD::GlobalRetAddr,
304 switch (Op.getNumOperands()) {
306 assert(0 && "Do not know how to return this many arguments!");
310 //return SDValue(); // ret void is legal
312 MVT ArgVT = Op.getOperand(1).getValueType();
314 if (ArgVT.isInteger())
317 assert(ArgVT.isFloatingPoint());
320 Copy = DAG.getCopyToReg(Copy, ArgReg, Op.getOperand(1), Copy.getValue(1));
321 if (DAG.getMachineFunction().getRegInfo().liveout_empty())
322 DAG.getMachineFunction().getRegInfo().addLiveOut(ArgReg);
326 return DAG.getNode(AlphaISD::RET_FLAG, MVT::Other, Copy, Copy.getValue(1));
329 std::pair<SDValue, SDValue>
330 AlphaTargetLowering::LowerCallTo(SDValue Chain, const Type *RetTy,
331 bool RetSExt, bool RetZExt, bool isVarArg,
332 unsigned CallingConv, bool isTailCall,
333 SDValue Callee, ArgListTy &Args,
337 NumBytes = (Args.size() - 6) * 8;
339 Chain = DAG.getCALLSEQ_START(Chain,
340 DAG.getConstant(NumBytes, getPointerTy()));
341 std::vector<SDValue> args_to_use;
342 for (unsigned i = 0, e = Args.size(); i != e; ++i)
344 switch (getValueType(Args[i].Ty).getSimpleVT()) {
345 default: assert(0 && "Unexpected ValueType for argument!");
350 // Promote the integer to 64 bits. If the input type is signed use a
351 // sign extend, otherwise use a zero extend.
353 Args[i].Node = DAG.getNode(ISD::SIGN_EXTEND, MVT::i64, Args[i].Node);
354 else if (Args[i].isZExt)
355 Args[i].Node = DAG.getNode(ISD::ZERO_EXTEND, MVT::i64, Args[i].Node);
357 Args[i].Node = DAG.getNode(ISD::ANY_EXTEND, MVT::i64, Args[i].Node);
364 args_to_use.push_back(Args[i].Node);
367 std::vector<MVT> RetVals;
368 MVT RetTyVT = getValueType(RetTy);
369 MVT ActualRetTyVT = RetTyVT;
370 if (RetTyVT.getSimpleVT() >= MVT::i1 && RetTyVT.getSimpleVT() <= MVT::i32)
371 ActualRetTyVT = MVT::i64;
373 if (RetTyVT != MVT::isVoid)
374 RetVals.push_back(ActualRetTyVT);
375 RetVals.push_back(MVT::Other);
377 std::vector<SDValue> Ops;
378 Ops.push_back(Chain);
379 Ops.push_back(Callee);
380 Ops.insert(Ops.end(), args_to_use.begin(), args_to_use.end());
381 SDValue TheCall = DAG.getNode(AlphaISD::CALL, RetVals, &Ops[0], Ops.size());
382 Chain = TheCall.getValue(RetTyVT != MVT::isVoid);
383 Chain = DAG.getCALLSEQ_END(Chain,
384 DAG.getConstant(NumBytes, getPointerTy()),
385 DAG.getConstant(0, getPointerTy()),
387 SDValue RetVal = TheCall;
389 if (RetTyVT != ActualRetTyVT) {
390 ISD::NodeType AssertKind = ISD::DELETED_NODE;
392 AssertKind = ISD::AssertSext;
394 AssertKind = ISD::AssertZext;
396 if (AssertKind != ISD::DELETED_NODE)
397 RetVal = DAG.getNode(AssertKind, MVT::i64, RetVal,
398 DAG.getValueType(RetTyVT));
400 RetVal = DAG.getNode(ISD::TRUNCATE, RetTyVT, RetVal);
403 return std::make_pair(RetVal, Chain);
406 void AlphaTargetLowering::LowerVAARG(SDNode *N, SDValue &Chain,
407 SDValue &DataPtr, SelectionDAG &DAG) {
408 Chain = N->getOperand(0);
409 SDValue VAListP = N->getOperand(1);
410 const Value *VAListS = cast<SrcValueSDNode>(N->getOperand(2))->getValue();
412 SDValue Base = DAG.getLoad(MVT::i64, Chain, VAListP, VAListS, 0);
413 SDValue Tmp = DAG.getNode(ISD::ADD, MVT::i64, VAListP,
414 DAG.getConstant(8, MVT::i64));
415 SDValue Offset = DAG.getExtLoad(ISD::SEXTLOAD, MVT::i64, Base.getValue(1),
416 Tmp, NULL, 0, MVT::i32);
417 DataPtr = DAG.getNode(ISD::ADD, MVT::i64, Base, Offset);
418 if (N->getValueType(0).isFloatingPoint())
420 //if fp && Offset < 6*8, then subtract 6*8 from DataPtr
421 SDValue FPDataPtr = DAG.getNode(ISD::SUB, MVT::i64, DataPtr,
422 DAG.getConstant(8*6, MVT::i64));
423 SDValue CC = DAG.getSetCC(MVT::i64, Offset,
424 DAG.getConstant(8*6, MVT::i64), ISD::SETLT);
425 DataPtr = DAG.getNode(ISD::SELECT, MVT::i64, CC, FPDataPtr, DataPtr);
428 SDValue NewOffset = DAG.getNode(ISD::ADD, MVT::i64, Offset,
429 DAG.getConstant(8, MVT::i64));
430 Chain = DAG.getTruncStore(Offset.getValue(1), NewOffset, Tmp, NULL, 0,
434 /// LowerOperation - Provide custom lowering hooks for some operations.
436 SDValue AlphaTargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) {
437 switch (Op.getOpcode()) {
438 default: assert(0 && "Wasn't expecting to be able to lower this!");
439 case ISD::FORMAL_ARGUMENTS: return LowerFORMAL_ARGUMENTS(Op, DAG,
443 case ISD::RET: return LowerRET(Op,DAG);
444 case ISD::JumpTable: return LowerJumpTable(Op, DAG);
446 case ISD::SINT_TO_FP: {
447 assert(Op.getOperand(0).getValueType() == MVT::i64 &&
448 "Unhandled SINT_TO_FP type in custom expander!");
450 bool isDouble = Op.getValueType() == MVT::f64;
451 LD = DAG.getNode(ISD::BIT_CONVERT, MVT::f64, Op.getOperand(0));
452 SDValue FP = DAG.getNode(isDouble?AlphaISD::CVTQT_:AlphaISD::CVTQS_,
453 isDouble?MVT::f64:MVT::f32, LD);
456 case ISD::FP_TO_SINT: {
457 bool isDouble = Op.getOperand(0).getValueType() == MVT::f64;
458 SDValue src = Op.getOperand(0);
460 if (!isDouble) //Promote
461 src = DAG.getNode(ISD::FP_EXTEND, MVT::f64, src);
463 src = DAG.getNode(AlphaISD::CVTTQ_, MVT::f64, src);
465 return DAG.getNode(ISD::BIT_CONVERT, MVT::i64, src);
467 case ISD::ConstantPool: {
468 ConstantPoolSDNode *CP = cast<ConstantPoolSDNode>(Op);
469 Constant *C = CP->getConstVal();
470 SDValue CPI = DAG.getTargetConstantPool(C, MVT::i64, CP->getAlignment());
472 SDValue Hi = DAG.getNode(AlphaISD::GPRelHi, MVT::i64, CPI,
473 DAG.getNode(ISD::GLOBAL_OFFSET_TABLE, MVT::i64));
474 SDValue Lo = DAG.getNode(AlphaISD::GPRelLo, MVT::i64, CPI, Hi);
477 case ISD::GlobalTLSAddress:
478 assert(0 && "TLS not implemented for Alpha.");
479 case ISD::GlobalAddress: {
480 GlobalAddressSDNode *GSDN = cast<GlobalAddressSDNode>(Op);
481 GlobalValue *GV = GSDN->getGlobal();
482 SDValue GA = DAG.getTargetGlobalAddress(GV, MVT::i64, GSDN->getOffset());
484 // if (!GV->hasWeakLinkage() && !GV->isDeclaration() && !GV->hasLinkOnceLinkage()) {
485 if (GV->hasInternalLinkage()) {
486 SDValue Hi = DAG.getNode(AlphaISD::GPRelHi, MVT::i64, GA,
487 DAG.getNode(ISD::GLOBAL_OFFSET_TABLE, MVT::i64));
488 SDValue Lo = DAG.getNode(AlphaISD::GPRelLo, MVT::i64, GA, Hi);
491 return DAG.getNode(AlphaISD::RelLit, MVT::i64, GA,
492 DAG.getNode(ISD::GLOBAL_OFFSET_TABLE, MVT::i64));
494 case ISD::ExternalSymbol: {
495 return DAG.getNode(AlphaISD::RelLit, MVT::i64,
496 DAG.getTargetExternalSymbol(cast<ExternalSymbolSDNode>(Op)
497 ->getSymbol(), MVT::i64),
498 DAG.getNode(ISD::GLOBAL_OFFSET_TABLE, MVT::i64));
503 //Expand only on constant case
504 if (Op.getOperand(1).getOpcode() == ISD::Constant) {
505 MVT VT = Op.getNode()->getValueType(0);
506 SDValue Tmp1 = Op.getNode()->getOpcode() == ISD::UREM ?
507 BuildUDIV(Op.getNode(), DAG, NULL) :
508 BuildSDIV(Op.getNode(), DAG, NULL);
509 Tmp1 = DAG.getNode(ISD::MUL, VT, Tmp1, Op.getOperand(1));
510 Tmp1 = DAG.getNode(ISD::SUB, VT, Op.getOperand(0), Tmp1);
516 if (Op.getValueType().isInteger()) {
517 if (Op.getOperand(1).getOpcode() == ISD::Constant)
518 return Op.getOpcode() == ISD::SDIV ? BuildSDIV(Op.getNode(), DAG, NULL)
519 : BuildUDIV(Op.getNode(), DAG, NULL);
520 const char* opstr = 0;
521 switch (Op.getOpcode()) {
522 case ISD::UREM: opstr = "__remqu"; break;
523 case ISD::SREM: opstr = "__remq"; break;
524 case ISD::UDIV: opstr = "__divqu"; break;
525 case ISD::SDIV: opstr = "__divq"; break;
527 SDValue Tmp1 = Op.getOperand(0),
528 Tmp2 = Op.getOperand(1),
529 Addr = DAG.getExternalSymbol(opstr, MVT::i64);
530 return DAG.getNode(AlphaISD::DivCall, MVT::i64, Addr, Tmp1, Tmp2);
535 SDValue Chain, DataPtr;
536 LowerVAARG(Op.getNode(), Chain, DataPtr, DAG);
539 if (Op.getValueType() == MVT::i32)
540 Result = DAG.getExtLoad(ISD::SEXTLOAD, MVT::i64, Chain, DataPtr,
543 Result = DAG.getLoad(Op.getValueType(), Chain, DataPtr, NULL, 0);
547 SDValue Chain = Op.getOperand(0);
548 SDValue DestP = Op.getOperand(1);
549 SDValue SrcP = Op.getOperand(2);
550 const Value *DestS = cast<SrcValueSDNode>(Op.getOperand(3))->getValue();
551 const Value *SrcS = cast<SrcValueSDNode>(Op.getOperand(4))->getValue();
553 SDValue Val = DAG.getLoad(getPointerTy(), Chain, SrcP, SrcS, 0);
554 SDValue Result = DAG.getStore(Val.getValue(1), Val, DestP, DestS, 0);
555 SDValue NP = DAG.getNode(ISD::ADD, MVT::i64, SrcP,
556 DAG.getConstant(8, MVT::i64));
557 Val = DAG.getExtLoad(ISD::SEXTLOAD, MVT::i64, Result, NP, NULL,0, MVT::i32);
558 SDValue NPD = DAG.getNode(ISD::ADD, MVT::i64, DestP,
559 DAG.getConstant(8, MVT::i64));
560 return DAG.getTruncStore(Val.getValue(1), Val, NPD, NULL, 0, MVT::i32);
563 SDValue Chain = Op.getOperand(0);
564 SDValue VAListP = Op.getOperand(1);
565 const Value *VAListS = cast<SrcValueSDNode>(Op.getOperand(2))->getValue();
567 // vastart stores the address of the VarArgsBase and VarArgsOffset
568 SDValue FR = DAG.getFrameIndex(VarArgsBase, MVT::i64);
569 SDValue S1 = DAG.getStore(Chain, FR, VAListP, VAListS, 0);
570 SDValue SA2 = DAG.getNode(ISD::ADD, MVT::i64, VAListP,
571 DAG.getConstant(8, MVT::i64));
572 return DAG.getTruncStore(S1, DAG.getConstant(VarArgsOffset, MVT::i64),
573 SA2, NULL, 0, MVT::i32);
575 case ISD::RETURNADDR:
576 return DAG.getNode(AlphaISD::GlobalRetAddr, MVT::i64);
578 case ISD::FRAMEADDR: break;
584 SDNode *AlphaTargetLowering::ReplaceNodeResults(SDNode *N,
586 assert(N->getValueType(0) == MVT::i32 &&
587 N->getOpcode() == ISD::VAARG &&
588 "Unknown node to custom promote!");
590 SDValue Chain, DataPtr;
591 LowerVAARG(N, Chain, DataPtr, DAG);
592 return DAG.getLoad(N->getValueType(0), Chain, DataPtr, NULL, 0).getNode();
598 /// getConstraintType - Given a constraint letter, return the type of
599 /// constraint it is for this target.
600 AlphaTargetLowering::ConstraintType
601 AlphaTargetLowering::getConstraintType(const std::string &Constraint) const {
602 if (Constraint.size() == 1) {
603 switch (Constraint[0]) {
607 return C_RegisterClass;
610 return TargetLowering::getConstraintType(Constraint);
613 std::vector<unsigned> AlphaTargetLowering::
614 getRegClassForInlineAsmConstraint(const std::string &Constraint,
616 if (Constraint.size() == 1) {
617 switch (Constraint[0]) {
618 default: break; // Unknown constriant letter
620 return make_vector<unsigned>(Alpha::F0 , Alpha::F1 , Alpha::F2 ,
621 Alpha::F3 , Alpha::F4 , Alpha::F5 ,
622 Alpha::F6 , Alpha::F7 , Alpha::F8 ,
623 Alpha::F9 , Alpha::F10, Alpha::F11,
624 Alpha::F12, Alpha::F13, Alpha::F14,
625 Alpha::F15, Alpha::F16, Alpha::F17,
626 Alpha::F18, Alpha::F19, Alpha::F20,
627 Alpha::F21, Alpha::F22, Alpha::F23,
628 Alpha::F24, Alpha::F25, Alpha::F26,
629 Alpha::F27, Alpha::F28, Alpha::F29,
630 Alpha::F30, Alpha::F31, 0);
632 return make_vector<unsigned>(Alpha::R0 , Alpha::R1 , Alpha::R2 ,
633 Alpha::R3 , Alpha::R4 , Alpha::R5 ,
634 Alpha::R6 , Alpha::R7 , Alpha::R8 ,
635 Alpha::R9 , Alpha::R10, Alpha::R11,
636 Alpha::R12, Alpha::R13, Alpha::R14,
637 Alpha::R15, Alpha::R16, Alpha::R17,
638 Alpha::R18, Alpha::R19, Alpha::R20,
639 Alpha::R21, Alpha::R22, Alpha::R23,
640 Alpha::R24, Alpha::R25, Alpha::R26,
641 Alpha::R27, Alpha::R28, Alpha::R29,
642 Alpha::R30, Alpha::R31, 0);
646 return std::vector<unsigned>();
648 //===----------------------------------------------------------------------===//
649 // Other Lowering Code
650 //===----------------------------------------------------------------------===//
653 AlphaTargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI,
654 MachineBasicBlock *BB) {
655 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
656 assert((MI->getOpcode() == Alpha::CAS32 ||
657 MI->getOpcode() == Alpha::CAS64 ||
658 MI->getOpcode() == Alpha::LAS32 ||
659 MI->getOpcode() == Alpha::LAS64 ||
660 MI->getOpcode() == Alpha::SWAP32 ||
661 MI->getOpcode() == Alpha::SWAP64) &&
662 "Unexpected instr type to insert");
664 bool is32 = MI->getOpcode() == Alpha::CAS32 ||
665 MI->getOpcode() == Alpha::LAS32 ||
666 MI->getOpcode() == Alpha::SWAP32;
668 //Load locked store conditional for atomic ops take on the same form
671 //do stuff (maybe branch to exit)
673 //test sc and maybe branck to start
675 const BasicBlock *LLVM_BB = BB->getBasicBlock();
676 MachineFunction::iterator It = BB;
679 MachineBasicBlock *thisMBB = BB;
680 MachineFunction *F = BB->getParent();
681 MachineBasicBlock *llscMBB = F->CreateMachineBasicBlock(LLVM_BB);
682 MachineBasicBlock *sinkMBB = F->CreateMachineBasicBlock(LLVM_BB);
684 sinkMBB->transferSuccessors(thisMBB);
686 F->insert(It, llscMBB);
687 F->insert(It, sinkMBB);
689 BuildMI(thisMBB, TII->get(Alpha::BR)).addMBB(llscMBB);
691 unsigned reg_res = MI->getOperand(0).getReg(),
692 reg_ptr = MI->getOperand(1).getReg(),
693 reg_v2 = MI->getOperand(2).getReg(),
694 reg_store = F->getRegInfo().createVirtualRegister(&Alpha::GPRCRegClass);
696 BuildMI(llscMBB, TII->get(is32 ? Alpha::LDL_L : Alpha::LDQ_L),
697 reg_res).addImm(0).addReg(reg_ptr);
698 switch (MI->getOpcode()) {
702 = F->getRegInfo().createVirtualRegister(&Alpha::GPRCRegClass);
703 BuildMI(llscMBB, TII->get(Alpha::CMPEQ), reg_cmp)
704 .addReg(reg_v2).addReg(reg_res);
705 BuildMI(llscMBB, TII->get(Alpha::BEQ))
706 .addImm(0).addReg(reg_cmp).addMBB(sinkMBB);
707 BuildMI(llscMBB, TII->get(Alpha::BISr), reg_store)
708 .addReg(Alpha::R31).addReg(MI->getOperand(3).getReg());
713 BuildMI(llscMBB, TII->get(is32 ? Alpha::ADDLr : Alpha::ADDQr), reg_store)
714 .addReg(reg_res).addReg(reg_v2);
718 case Alpha::SWAP64: {
719 BuildMI(llscMBB, TII->get(Alpha::BISr), reg_store)
720 .addReg(reg_v2).addReg(reg_v2);
724 BuildMI(llscMBB, TII->get(is32 ? Alpha::STL_C : Alpha::STQ_C), reg_store)
725 .addReg(reg_store).addImm(0).addReg(reg_ptr);
726 BuildMI(llscMBB, TII->get(Alpha::BEQ))
727 .addImm(0).addReg(reg_store).addMBB(llscMBB);
728 BuildMI(llscMBB, TII->get(Alpha::BR)).addMBB(sinkMBB);
730 thisMBB->addSuccessor(llscMBB);
731 llscMBB->addSuccessor(llscMBB);
732 llscMBB->addSuccessor(sinkMBB);
733 F->DeleteMachineInstr(MI); // The pseudo instruction is gone now.