1 //===-- AlphaISelLowering.cpp - Alpha DAG Lowering Implementation ---------===//
3 // The LLVM Compiler Infrastructure
5 // This file was developed by Andrew Lenharth and is distributed under
6 // the University of Illinois Open Source License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file implements the AlphaISelLowering class.
12 //===----------------------------------------------------------------------===//
14 #include "AlphaISelLowering.h"
15 #include "AlphaTargetMachine.h"
16 #include "llvm/CodeGen/MachineFrameInfo.h"
17 #include "llvm/CodeGen/MachineFunction.h"
18 #include "llvm/CodeGen/MachineInstrBuilder.h"
19 #include "llvm/CodeGen/SelectionDAG.h"
20 #include "llvm/CodeGen/SSARegMap.h"
21 #include "llvm/Constants.h"
22 #include "llvm/Function.h"
23 #include "llvm/Module.h"
24 #include "llvm/Support/CommandLine.h"
30 extern cl::opt<bool> EnableAlphaIDIV;
31 extern cl::opt<bool> EnableAlphaCount;
32 extern cl::opt<bool> EnableAlphaLSMark;
35 /// AddLiveIn - This helper function adds the specified physical register to the
36 /// MachineFunction as a live in value. It also creates a corresponding virtual
38 static unsigned AddLiveIn(MachineFunction &MF, unsigned PReg,
39 TargetRegisterClass *RC) {
40 assert(RC->contains(PReg) && "Not the correct regclass!");
41 unsigned VReg = MF.getSSARegMap()->createVirtualRegister(RC);
42 MF.addLiveIn(PReg, VReg);
46 AlphaTargetLowering::AlphaTargetLowering(TargetMachine &TM) : TargetLowering(TM) {
47 // Set up the TargetLowering object.
48 //I am having problems with shr n ubyte 1
49 setShiftAmountType(MVT::i64);
50 setSetCCResultType(MVT::i64);
51 setSetCCResultContents(ZeroOrOneSetCCResult);
53 addRegisterClass(MVT::i64, Alpha::GPRCRegisterClass);
54 addRegisterClass(MVT::f64, Alpha::F8RCRegisterClass);
55 addRegisterClass(MVT::f32, Alpha::F4RCRegisterClass);
57 setOperationAction(ISD::BRCONDTWOWAY, MVT::Other, Expand);
58 setOperationAction(ISD::BRTWOWAY_CC, MVT::Other, Expand);
60 setOperationAction(ISD::EXTLOAD, MVT::i1, Promote);
61 setOperationAction(ISD::EXTLOAD, MVT::f32, Expand);
63 setOperationAction(ISD::ZEXTLOAD, MVT::i1, Promote);
64 setOperationAction(ISD::ZEXTLOAD, MVT::i32, Expand);
66 setOperationAction(ISD::SEXTLOAD, MVT::i1, Promote);
67 setOperationAction(ISD::SEXTLOAD, MVT::i8, Expand);
68 setOperationAction(ISD::SEXTLOAD, MVT::i16, Expand);
70 setOperationAction(ISD::TRUNCSTORE, MVT::i1, Promote);
72 if (EnableAlphaLSMark) {
73 setOperationAction(ISD::LOAD, MVT::i64, Custom);
74 setOperationAction(ISD::LOAD, MVT::f64, Custom);
75 setOperationAction(ISD::LOAD, MVT::f32, Custom);
77 setOperationAction(ISD::ZEXTLOAD, MVT::i8, Custom);
78 setOperationAction(ISD::ZEXTLOAD, MVT::i16, Custom);
79 setOperationAction(ISD::SEXTLOAD, MVT::i32, Custom);
81 setOperationAction(ISD::EXTLOAD, MVT::i8, Custom);
82 setOperationAction(ISD::EXTLOAD, MVT::i16, Custom);
83 setOperationAction(ISD::EXTLOAD, MVT::i32, Custom);
86 setOperationAction(ISD::FREM, MVT::f32, Expand);
87 setOperationAction(ISD::FREM, MVT::f64, Expand);
89 setOperationAction(ISD::UINT_TO_FP, MVT::i64, Expand);
90 setOperationAction(ISD::SINT_TO_FP, MVT::i64, Custom);
91 setOperationAction(ISD::FP_TO_UINT, MVT::i64, Expand);
92 setOperationAction(ISD::FP_TO_SINT, MVT::i64, Custom);
94 if (!TM.getSubtarget<AlphaSubtarget>().hasCT()) {
95 setOperationAction(ISD::CTPOP , MVT::i64 , Expand);
96 setOperationAction(ISD::CTTZ , MVT::i64 , Expand);
97 setOperationAction(ISD::CTLZ , MVT::i64 , Expand);
99 setOperationAction(ISD::BSWAP , MVT::i64, Expand);
100 setOperationAction(ISD::ROTL , MVT::i64, Expand);
101 setOperationAction(ISD::ROTR , MVT::i64, Expand);
103 setOperationAction(ISD::SREM , MVT::i64, Custom);
104 setOperationAction(ISD::UREM , MVT::i64, Custom);
105 setOperationAction(ISD::SDIV , MVT::i64, Custom);
106 setOperationAction(ISD::UDIV , MVT::i64, Custom);
108 setOperationAction(ISD::MEMMOVE , MVT::Other, Expand);
109 setOperationAction(ISD::MEMSET , MVT::Other, Expand);
110 setOperationAction(ISD::MEMCPY , MVT::Other, Expand);
112 // We don't support sin/cos/sqrt
113 setOperationAction(ISD::FSIN , MVT::f64, Expand);
114 setOperationAction(ISD::FCOS , MVT::f64, Expand);
115 setOperationAction(ISD::FSIN , MVT::f32, Expand);
116 setOperationAction(ISD::FCOS , MVT::f32, Expand);
118 setOperationAction(ISD::FSQRT, MVT::f64, Expand);
119 setOperationAction(ISD::FSQRT, MVT::f32, Expand);
121 setOperationAction(ISD::SETCC, MVT::f32, Promote);
123 // We don't have line number support yet.
124 setOperationAction(ISD::LOCATION, MVT::Other, Expand);
125 setOperationAction(ISD::DEBUG_LOC, MVT::Other, Expand);
126 setOperationAction(ISD::DEBUG_LABEL, MVT::Other, Expand);
128 // Not implemented yet.
129 setOperationAction(ISD::STACKSAVE, MVT::Other, Expand);
130 setOperationAction(ISD::STACKRESTORE, MVT::Other, Expand);
131 setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i64, Expand);
133 // We want to legalize GlobalAddress and ConstantPool and
134 // ExternalSymbols nodes into the appropriate instructions to
135 // materialize the address.
136 setOperationAction(ISD::GlobalAddress, MVT::i64, Custom);
137 setOperationAction(ISD::ConstantPool, MVT::i64, Custom);
138 setOperationAction(ISD::ExternalSymbol, MVT::i64, Custom);
140 setStackPointerRegisterToSaveRestore(Alpha::R30);
142 addLegalFPImmediate(+0.0); //F31
143 addLegalFPImmediate(-0.0); //-F31
145 computeRegisterProperties();
147 useITOF = TM.getSubtarget<AlphaSubtarget>().hasF2I();
150 const char *AlphaTargetLowering::getTargetNodeName(unsigned Opcode) const {
153 case AlphaISD::ITOFT_: return "Alpha::ITOFT_";
154 case AlphaISD::FTOIT_: return "Alpha::FTOIT_";
155 case AlphaISD::CVTQT_: return "Alpha::CVTQT_";
156 case AlphaISD::CVTQS_: return "Alpha::CVTQS_";
157 case AlphaISD::CVTTQ_: return "Alpha::CVTTQ_";
158 case AlphaISD::GPRelHi: return "Alpha::GPRelHi";
159 case AlphaISD::GPRelLo: return "Alpha::GPRelLo";
160 case AlphaISD::RelLit: return "Alpha::RelLit";
161 case AlphaISD::GlobalBaseReg: return "Alpha::GlobalBaseReg";
162 case AlphaISD::DivCall: return "Alpha::DivCall";
163 case AlphaISD::LDQ_: return "Alpha::LDQ_";
164 case AlphaISD::LDT_: return "Alpha::LDT_";
165 case AlphaISD::LDS_: return "Alpha::LDS_";
166 case AlphaISD::LDL_: return "Alpha::LDL_";
167 case AlphaISD::LDWU_: return "Alpha::LDWU_";
168 case AlphaISD::LDBU_: return "Alpha::LDBU_";
172 //http://www.cs.arizona.edu/computer.help/policy/DIGITAL_unix/AA-PY8AC-TET1_html/callCH3.html#BLOCK21
174 //For now, just use variable size stack frame format
176 //In a standard call, the first six items are passed in registers $16
177 //- $21 and/or registers $f16 - $f21. (See Section 4.1.2 for details
178 //of argument-to-register correspondence.) The remaining items are
179 //collected in a memory argument list that is a naturally aligned
180 //array of quadwords. In a standard call, this list, if present, must
181 //be passed at 0(SP).
182 //7 ... n 0(SP) ... (n-7)*8(SP)
190 std::vector<SDOperand>
191 AlphaTargetLowering::LowerArguments(Function &F, SelectionDAG &DAG)
193 MachineFunction &MF = DAG.getMachineFunction();
194 MachineFrameInfo *MFI = MF.getFrameInfo();
195 MachineBasicBlock& BB = MF.front();
196 std::vector<SDOperand> ArgValues;
198 unsigned args_int[] = {
199 Alpha::R16, Alpha::R17, Alpha::R18, Alpha::R19, Alpha::R20, Alpha::R21};
200 unsigned args_float[] = {
201 Alpha::F16, Alpha::F17, Alpha::F18, Alpha::F19, Alpha::F20, Alpha::F21};
205 GP = AddLiveIn(MF, Alpha::R29, getRegClassFor(MVT::i64));
206 RA = AddLiveIn(MF, Alpha::R26, getRegClassFor(MVT::i64));
208 for (Function::arg_iterator I = F.arg_begin(), E = F.arg_end(); I != E; ++I)
213 MVT::ValueType VT = getValueType(I->getType());
216 std::cerr << "Unknown Type " << VT << "\n";
220 args_float[count] = AddLiveIn(MF, args_float[count], getRegClassFor(VT));
221 argt = DAG.getCopyFromReg(DAG.getRoot(), args_float[count], VT);
222 DAG.setRoot(argt.getValue(1));
229 args_int[count] = AddLiveIn(MF, args_int[count], getRegClassFor(MVT::i64));
230 argt = DAG.getCopyFromReg(DAG.getRoot(), args_int[count], MVT::i64);
231 DAG.setRoot(argt.getValue(1));
232 if (VT != MVT::i64) {
234 I->getType()->isSigned() ? ISD::AssertSext : ISD::AssertZext;
235 argt = DAG.getNode(AssertOp, MVT::i64, argt,
236 DAG.getValueType(VT));
237 argt = DAG.getNode(ISD::TRUNCATE, VT, argt);
242 // Create the frame index object for this incoming parameter...
243 int FI = MFI->CreateFixedObject(8, 8 * (count - 6));
245 // Create the SelectionDAG nodes corresponding to a load
246 //from this parameter
247 SDOperand FIN = DAG.getFrameIndex(FI, MVT::i64);
248 argt = DAG.getLoad(getValueType(I->getType()),
249 DAG.getEntryNode(), FIN, DAG.getSrcValue(NULL));
252 ArgValues.push_back(argt);
255 // If the functions takes variable number of arguments, copy all regs to stack
257 VarArgsOffset = count * 8;
258 std::vector<SDOperand> LS;
259 for (int i = 0; i < 6; ++i) {
260 if (MRegisterInfo::isPhysicalRegister(args_int[i]))
261 args_int[i] = AddLiveIn(MF, args_int[i], getRegClassFor(MVT::i64));
262 SDOperand argt = DAG.getCopyFromReg(DAG.getRoot(), args_int[i], MVT::i64);
263 int FI = MFI->CreateFixedObject(8, -8 * (6 - i));
264 if (i == 0) VarArgsBase = FI;
265 SDOperand SDFI = DAG.getFrameIndex(FI, MVT::i64);
266 LS.push_back(DAG.getNode(ISD::STORE, MVT::Other, DAG.getRoot(), argt,
267 SDFI, DAG.getSrcValue(NULL)));
269 if (MRegisterInfo::isPhysicalRegister(args_float[i]))
270 args_float[i] = AddLiveIn(MF, args_float[i], getRegClassFor(MVT::f64));
271 argt = DAG.getCopyFromReg(DAG.getRoot(), args_float[i], MVT::f64);
272 FI = MFI->CreateFixedObject(8, - 8 * (12 - i));
273 SDFI = DAG.getFrameIndex(FI, MVT::i64);
274 LS.push_back(DAG.getNode(ISD::STORE, MVT::Other, DAG.getRoot(), argt,
275 SDFI, DAG.getSrcValue(NULL)));
278 //Set up a token factor with all the stack traffic
279 DAG.setRoot(DAG.getNode(ISD::TokenFactor, MVT::Other, LS));
282 // Finally, inform the code generator which regs we return values in.
283 switch (getValueType(F.getReturnType())) {
284 default: assert(0 && "Unknown type!");
285 case MVT::isVoid: break;
291 MF.addLiveOut(Alpha::R0);
295 MF.addLiveOut(Alpha::F0);
299 //return the arguments
303 std::pair<SDOperand, SDOperand>
304 AlphaTargetLowering::LowerCallTo(SDOperand Chain,
305 const Type *RetTy, bool isVarArg,
306 unsigned CallingConv, bool isTailCall,
307 SDOperand Callee, ArgListTy &Args,
311 NumBytes = (Args.size() - 6) * 8;
313 Chain = DAG.getNode(ISD::CALLSEQ_START, MVT::Other, Chain,
314 DAG.getConstant(NumBytes, getPointerTy()));
315 std::vector<SDOperand> args_to_use;
316 for (unsigned i = 0, e = Args.size(); i != e; ++i)
318 switch (getValueType(Args[i].second)) {
319 default: assert(0 && "Unexpected ValueType for argument!");
324 // Promote the integer to 64 bits. If the input type is signed use a
325 // sign extend, otherwise use a zero extend.
326 if (Args[i].second->isSigned())
327 Args[i].first = DAG.getNode(ISD::SIGN_EXTEND, MVT::i64, Args[i].first);
329 Args[i].first = DAG.getNode(ISD::ZERO_EXTEND, MVT::i64, Args[i].first);
336 args_to_use.push_back(Args[i].first);
339 std::vector<MVT::ValueType> RetVals;
340 MVT::ValueType RetTyVT = getValueType(RetTy);
341 MVT::ValueType ActualRetTyVT = RetTyVT;
342 if (RetTyVT >= MVT::i1 && RetTyVT <= MVT::i32)
343 ActualRetTyVT = MVT::i64;
345 if (RetTyVT != MVT::isVoid)
346 RetVals.push_back(ActualRetTyVT);
347 RetVals.push_back(MVT::Other);
349 SDOperand TheCall = SDOperand(DAG.getCall(RetVals,
350 Chain, Callee, args_to_use), 0);
351 Chain = TheCall.getValue(RetTyVT != MVT::isVoid);
352 Chain = DAG.getNode(ISD::CALLSEQ_END, MVT::Other, Chain,
353 DAG.getConstant(NumBytes, getPointerTy()));
354 SDOperand RetVal = TheCall;
356 if (RetTyVT != ActualRetTyVT) {
357 RetVal = DAG.getNode(RetTy->isSigned() ? ISD::AssertSext : ISD::AssertZext,
358 MVT::i64, RetVal, DAG.getValueType(RetTyVT));
359 RetVal = DAG.getNode(ISD::TRUNCATE, RetTyVT, RetVal);
362 return std::make_pair(RetVal, Chain);
365 SDOperand AlphaTargetLowering::LowerVAStart(SDOperand Chain, SDOperand VAListP,
366 Value *VAListV, SelectionDAG &DAG) {
367 // vastart stores the address of the VarArgsBase and VarArgsOffset
368 SDOperand FR = DAG.getFrameIndex(VarArgsBase, MVT::i64);
369 SDOperand S1 = DAG.getNode(ISD::STORE, MVT::Other, Chain, FR, VAListP,
370 DAG.getSrcValue(VAListV));
371 SDOperand SA2 = DAG.getNode(ISD::ADD, MVT::i64, VAListP,
372 DAG.getConstant(8, MVT::i64));
373 return DAG.getNode(ISD::TRUNCSTORE, MVT::Other, S1,
374 DAG.getConstant(VarArgsOffset, MVT::i64), SA2,
375 DAG.getSrcValue(VAListV, 8), DAG.getValueType(MVT::i32));
378 std::pair<SDOperand,SDOperand> AlphaTargetLowering::
379 LowerVAArg(SDOperand Chain, SDOperand VAListP, Value *VAListV,
380 const Type *ArgTy, SelectionDAG &DAG) {
381 SDOperand Base = DAG.getLoad(MVT::i64, Chain, VAListP,
382 DAG.getSrcValue(VAListV));
383 SDOperand Tmp = DAG.getNode(ISD::ADD, MVT::i64, VAListP,
384 DAG.getConstant(8, MVT::i64));
385 SDOperand Offset = DAG.getExtLoad(ISD::SEXTLOAD, MVT::i64, Base.getValue(1),
386 Tmp, DAG.getSrcValue(VAListV, 8), MVT::i32);
387 SDOperand DataPtr = DAG.getNode(ISD::ADD, MVT::i64, Base, Offset);
388 if (ArgTy->isFloatingPoint())
390 //if fp && Offset < 6*8, then subtract 6*8 from DataPtr
391 SDOperand FPDataPtr = DAG.getNode(ISD::SUB, MVT::i64, DataPtr,
392 DAG.getConstant(8*6, MVT::i64));
393 SDOperand CC = DAG.getSetCC(MVT::i64, Offset,
394 DAG.getConstant(8*6, MVT::i64), ISD::SETLT);
395 DataPtr = DAG.getNode(ISD::SELECT, MVT::i64, CC, FPDataPtr, DataPtr);
399 if (ArgTy == Type::IntTy)
400 Result = DAG.getExtLoad(ISD::SEXTLOAD, MVT::i64, Offset.getValue(1),
401 DataPtr, DAG.getSrcValue(NULL), MVT::i32);
402 else if (ArgTy == Type::UIntTy)
403 Result = DAG.getExtLoad(ISD::ZEXTLOAD, MVT::i64, Offset.getValue(1),
404 DataPtr, DAG.getSrcValue(NULL), MVT::i32);
406 Result = DAG.getLoad(getValueType(ArgTy), Offset.getValue(1), DataPtr,
407 DAG.getSrcValue(NULL));
409 SDOperand NewOffset = DAG.getNode(ISD::ADD, MVT::i64, Offset,
410 DAG.getConstant(8, MVT::i64));
411 SDOperand Update = DAG.getNode(ISD::TRUNCSTORE, MVT::Other,
412 Result.getValue(1), NewOffset,
413 Tmp, DAG.getSrcValue(VAListV, 8),
414 DAG.getValueType(MVT::i32));
415 Result = DAG.getNode(ISD::TRUNCATE, getValueType(ArgTy), Result);
417 return std::make_pair(Result, Update);
420 SDOperand AlphaTargetLowering::
421 LowerVACopy(SDOperand Chain, SDOperand SrcP, Value *SrcV, SDOperand DestP,
422 Value *DestV, SelectionDAG &DAG) {
423 SDOperand Val = DAG.getLoad(getPointerTy(), Chain, SrcP,
424 DAG.getSrcValue(SrcV));
425 SDOperand Result = DAG.getNode(ISD::STORE, MVT::Other, Val.getValue(1),
426 Val, DestP, DAG.getSrcValue(DestV));
427 SDOperand NP = DAG.getNode(ISD::ADD, MVT::i64, SrcP,
428 DAG.getConstant(8, MVT::i64));
429 Val = DAG.getExtLoad(ISD::SEXTLOAD, MVT::i64, Result, NP,
430 DAG.getSrcValue(SrcV, 8), MVT::i32);
431 SDOperand NPD = DAG.getNode(ISD::ADD, MVT::i64, DestP,
432 DAG.getConstant(8, MVT::i64));
433 return DAG.getNode(ISD::TRUNCSTORE, MVT::Other, Val.getValue(1),
434 Val, NPD, DAG.getSrcValue(DestV, 8),
435 DAG.getValueType(MVT::i32));
438 void AlphaTargetLowering::restoreGP(MachineBasicBlock* BB)
440 BuildMI(BB, Alpha::BIS, 2, Alpha::R29).addReg(GP).addReg(GP);
442 void AlphaTargetLowering::restoreRA(MachineBasicBlock* BB)
444 BuildMI(BB, Alpha::BIS, 2, Alpha::R26).addReg(RA).addReg(RA);
449 static void getValueInfo(const Value* v, int& type, int& fun, int& offset)
451 fun = type = offset = 0;
454 } else if (const GlobalValue* GV = dyn_cast<GlobalValue>(v)) {
456 const Module* M = GV->getParent();
457 for(Module::const_global_iterator ii = M->global_begin(); &*ii != GV; ++ii)
459 } else if (const Argument* Arg = dyn_cast<Argument>(v)) {
461 const Function* F = Arg->getParent();
462 const Module* M = F->getParent();
463 for(Module::const_iterator ii = M->begin(); &*ii != F; ++ii)
465 for(Function::const_arg_iterator ii = F->arg_begin(); &*ii != Arg; ++ii)
467 } else if (const Instruction* I = dyn_cast<Instruction>(v)) {
468 assert(dyn_cast<PointerType>(I->getType()));
470 const BasicBlock* bb = I->getParent();
471 const Function* F = bb->getParent();
472 const Module* M = F->getParent();
473 for(Module::const_iterator ii = M->begin(); &*ii != F; ++ii)
475 for(Function::const_iterator ii = F->begin(); &*ii != bb; ++ii)
476 offset += ii->size();
477 for(BasicBlock::const_iterator ii = bb->begin(); &*ii != I; ++ii)
479 } else if (const Constant* C = dyn_cast<Constant>(v)) {
480 //Don't know how to look these up yet
483 assert(0 && "Error in value marking");
485 //type = 4: register spilling
486 //type = 5: global address loading or constant loading
495 /// LowerOperation - Provide custom lowering hooks for some operations.
497 SDOperand AlphaTargetLowering::LowerOperation(SDOperand Op, SelectionDAG &DAG) {
498 switch (Op.getOpcode()) {
499 default: assert(0 && "Wasn't expecting to be able to lower this!");
500 case ISD::SINT_TO_FP: {
501 assert(MVT::i64 == Op.getOperand(0).getValueType() &&
502 "Unhandled SINT_TO_FP type in custom expander!");
504 bool isDouble = MVT::f64 == Op.getValueType();
506 LD = DAG.getNode(AlphaISD::ITOFT_, MVT::f64, Op.getOperand(0));
509 DAG.getMachineFunction().getFrameInfo()->CreateStackObject(8, 8);
510 SDOperand FI = DAG.getFrameIndex(FrameIdx, MVT::i64);
511 SDOperand ST = DAG.getNode(ISD::STORE, MVT::Other, DAG.getEntryNode(),
512 Op.getOperand(0), FI, DAG.getSrcValue(0));
513 LD = DAG.getLoad(MVT::f64, ST, FI, DAG.getSrcValue(0));
515 SDOperand FP = DAG.getNode(isDouble?AlphaISD::CVTQT_:AlphaISD::CVTQS_,
516 isDouble?MVT::f64:MVT::f32, LD);
519 case ISD::FP_TO_SINT: {
520 bool isDouble = MVT::f64 == Op.getOperand(0).getValueType();
521 SDOperand src = Op.getOperand(0);
523 if (!isDouble) //Promote
524 src = DAG.getNode(ISD::FP_EXTEND, MVT::f64, src);
526 src = DAG.getNode(AlphaISD::CVTTQ_, MVT::f64, src);
529 return DAG.getNode(AlphaISD::FTOIT_, MVT::i64, src);
532 DAG.getMachineFunction().getFrameInfo()->CreateStackObject(8, 8);
533 SDOperand FI = DAG.getFrameIndex(FrameIdx, MVT::i64);
534 SDOperand ST = DAG.getNode(ISD::STORE, MVT::Other, DAG.getEntryNode(),
535 src, FI, DAG.getSrcValue(0));
536 return DAG.getLoad(MVT::i64, ST, FI, DAG.getSrcValue(0));
539 case ISD::ConstantPool: {
540 Constant *C = cast<ConstantPoolSDNode>(Op)->get();
541 SDOperand CPI = DAG.getTargetConstantPool(C, MVT::i64);
543 SDOperand Hi = DAG.getNode(AlphaISD::GPRelHi, MVT::i64, CPI,
544 DAG.getNode(AlphaISD::GlobalBaseReg, MVT::i64));
545 SDOperand Lo = DAG.getNode(AlphaISD::GPRelLo, MVT::i64, CPI, Hi);
548 case ISD::GlobalAddress: {
549 GlobalAddressSDNode *GSDN = cast<GlobalAddressSDNode>(Op);
550 GlobalValue *GV = GSDN->getGlobal();
551 SDOperand GA = DAG.getTargetGlobalAddress(GV, MVT::i64, GSDN->getOffset());
553 if (!GV->hasWeakLinkage() && !GV->isExternal()) {
554 SDOperand Hi = DAG.getNode(AlphaISD::GPRelHi, MVT::i64, GA,
555 DAG.getNode(AlphaISD::GlobalBaseReg, MVT::i64));
556 SDOperand Lo = DAG.getNode(AlphaISD::GPRelLo, MVT::i64, GA, Hi);
559 return DAG.getNode(AlphaISD::RelLit, MVT::i64, GA, DAG.getNode(AlphaISD::GlobalBaseReg, MVT::i64));
561 case ISD::ExternalSymbol: {
562 return DAG.getNode(AlphaISD::RelLit, MVT::i64,
563 DAG.getTargetExternalSymbol(cast<ExternalSymbolSDNode>(Op)->getSymbol(), MVT::i64),
564 DAG.getNode(AlphaISD::GlobalBaseReg, MVT::i64));
571 if (MVT::isInteger(Op.getValueType())) {
572 const char* opstr = 0;
573 switch(Op.getOpcode()) {
574 case ISD::UREM: opstr = "__remqu"; break;
575 case ISD::SREM: opstr = "__remq"; break;
576 case ISD::UDIV: opstr = "__divqu"; break;
577 case ISD::SDIV: opstr = "__divq"; break;
579 SDOperand Tmp1 = Op.getOperand(0),
580 Tmp2 = Op.getOperand(1),
581 Addr = DAG.getExternalSymbol(opstr, MVT::i64);
582 return DAG.getNode(AlphaISD::DivCall, MVT::i64, Addr, Tmp1, Tmp2);
591 SDOperand Chain = Op.getOperand(0);
592 SDOperand Address = Op.getOperand(1);
595 unsigned opcode = Op.getOpcode();
597 if (opcode == ISD::LOAD)
598 switch (Op.Val->getValueType(0)) {
599 default: Op.Val->dump(); assert(0 && "Bad load!");
600 case MVT::i64: Opc = AlphaISD::LDQ_; break;
601 case MVT::f64: Opc = AlphaISD::LDT_; break;
602 case MVT::f32: Opc = AlphaISD::LDS_; break;
605 switch (cast<VTSDNode>(Op.getOperand(3))->getVT()) {
606 default: Op.Val->dump(); assert(0 && "Bad sign extend!");
607 case MVT::i32: Opc = AlphaISD::LDL_;
608 assert(opcode != ISD::ZEXTLOAD && "Not sext"); break;
609 case MVT::i16: Opc = AlphaISD::LDWU_;
610 assert(opcode != ISD::SEXTLOAD && "Not zext"); break;
611 case MVT::i1: //FIXME: Treat i1 as i8 since there are problems otherwise
612 case MVT::i8: Opc = AlphaISD::LDBU_;
613 assert(opcode != ISD::SEXTLOAD && "Not zext"); break;
617 getValueInfo(dyn_cast<SrcValueSDNode>(Op.getOperand(2))->getValue(), i, j, k);
619 SDOperand Zero = DAG.getConstant(0, MVT::i64);
620 std::vector<MVT::ValueType> VTS;
621 VTS.push_back(Op.Val->getValueType(0));
622 VTS.push_back(MVT::Other);
623 std::vector<SDOperand> ARGS;
624 ARGS.push_back(Chain);
625 ARGS.push_back(Zero);
626 ARGS.push_back(Address);
627 ARGS.push_back(DAG.getConstant(i, MVT::i64));
628 ARGS.push_back(DAG.getConstant(j, MVT::i64));
629 ARGS.push_back(DAG.getConstant(k, MVT::i64));
630 ARGS.push_back(DAG.getConstant(getUID(), MVT::i64));
631 return DAG.getNode(Opc, VTS, ARGS);