1 //===-- AlphaISelLowering.cpp - Alpha DAG Lowering Implementation ---------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file implements the AlphaISelLowering class.
12 //===----------------------------------------------------------------------===//
14 #include "AlphaISelLowering.h"
15 #include "AlphaTargetMachine.h"
16 #include "llvm/CodeGen/MachineFrameInfo.h"
17 #include "llvm/CodeGen/MachineFunction.h"
18 #include "llvm/CodeGen/MachineInstrBuilder.h"
19 #include "llvm/CodeGen/MachineRegisterInfo.h"
20 #include "llvm/CodeGen/SelectionDAG.h"
21 #include "llvm/CodeGen/MachineRegisterInfo.h"
22 #include "llvm/Constants.h"
23 #include "llvm/Function.h"
24 #include "llvm/Module.h"
25 #include "llvm/Support/CommandLine.h"
28 /// AddLiveIn - This helper function adds the specified physical register to the
29 /// MachineFunction as a live in value. It also creates a corresponding virtual
31 static unsigned AddLiveIn(MachineFunction &MF, unsigned PReg,
32 TargetRegisterClass *RC) {
33 assert(RC->contains(PReg) && "Not the correct regclass!");
34 unsigned VReg = MF.getRegInfo().createVirtualRegister(RC);
35 MF.getRegInfo().addLiveIn(PReg, VReg);
39 AlphaTargetLowering::AlphaTargetLowering(TargetMachine &TM) : TargetLowering(TM) {
40 // Set up the TargetLowering object.
41 //I am having problems with shr n ubyte 1
42 setShiftAmountType(MVT::i64);
43 setSetCCResultContents(ZeroOrOneSetCCResult);
45 setUsesGlobalOffsetTable(true);
47 addRegisterClass(MVT::i64, Alpha::GPRCRegisterClass);
48 addRegisterClass(MVT::f64, Alpha::F8RCRegisterClass);
49 addRegisterClass(MVT::f32, Alpha::F4RCRegisterClass);
51 setLoadXAction(ISD::EXTLOAD, MVT::i1, Promote);
52 setLoadXAction(ISD::EXTLOAD, MVT::f32, Expand);
54 setLoadXAction(ISD::ZEXTLOAD, MVT::i1, Promote);
55 setLoadXAction(ISD::ZEXTLOAD, MVT::i32, Expand);
57 setLoadXAction(ISD::SEXTLOAD, MVT::i1, Promote);
58 setLoadXAction(ISD::SEXTLOAD, MVT::i8, Expand);
59 setLoadXAction(ISD::SEXTLOAD, MVT::i16, Expand);
61 // setOperationAction(ISD::BRIND, MVT::Other, Expand);
62 setOperationAction(ISD::BR_JT, MVT::Other, Expand);
63 setOperationAction(ISD::BR_CC, MVT::Other, Expand);
64 setOperationAction(ISD::SELECT_CC, MVT::Other, Expand);
66 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1, Expand);
68 setOperationAction(ISD::FREM, MVT::f32, Expand);
69 setOperationAction(ISD::FREM, MVT::f64, Expand);
71 setOperationAction(ISD::UINT_TO_FP, MVT::i64, Expand);
72 setOperationAction(ISD::SINT_TO_FP, MVT::i64, Custom);
73 setOperationAction(ISD::FP_TO_UINT, MVT::i64, Expand);
74 setOperationAction(ISD::FP_TO_SINT, MVT::i64, Custom);
76 if (!TM.getSubtarget<AlphaSubtarget>().hasCT()) {
77 setOperationAction(ISD::CTPOP , MVT::i64 , Expand);
78 setOperationAction(ISD::CTTZ , MVT::i64 , Expand);
79 setOperationAction(ISD::CTLZ , MVT::i64 , Expand);
81 setOperationAction(ISD::BSWAP , MVT::i64, Expand);
82 setOperationAction(ISD::ROTL , MVT::i64, Expand);
83 setOperationAction(ISD::ROTR , MVT::i64, Expand);
85 setOperationAction(ISD::SREM , MVT::i64, Custom);
86 setOperationAction(ISD::UREM , MVT::i64, Custom);
87 setOperationAction(ISD::SDIV , MVT::i64, Custom);
88 setOperationAction(ISD::UDIV , MVT::i64, Custom);
90 // We don't support sin/cos/sqrt/pow
91 setOperationAction(ISD::FSIN , MVT::f64, Expand);
92 setOperationAction(ISD::FCOS , MVT::f64, Expand);
93 setOperationAction(ISD::FSIN , MVT::f32, Expand);
94 setOperationAction(ISD::FCOS , MVT::f32, Expand);
96 setOperationAction(ISD::FSQRT, MVT::f64, Expand);
97 setOperationAction(ISD::FSQRT, MVT::f32, Expand);
99 setOperationAction(ISD::FPOW , MVT::f32, Expand);
100 setOperationAction(ISD::FPOW , MVT::f64, Expand);
102 setOperationAction(ISD::SETCC, MVT::f32, Promote);
104 setOperationAction(ISD::BIT_CONVERT, MVT::f32, Promote);
106 // We don't have line number support yet.
107 setOperationAction(ISD::LOCATION, MVT::Other, Expand);
108 setOperationAction(ISD::DEBUG_LOC, MVT::Other, Expand);
109 setOperationAction(ISD::LABEL, MVT::Other, Expand);
111 // Not implemented yet.
112 setOperationAction(ISD::STACKSAVE, MVT::Other, Expand);
113 setOperationAction(ISD::STACKRESTORE, MVT::Other, Expand);
114 setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i64, Expand);
116 // We want to legalize GlobalAddress and ConstantPool and
117 // ExternalSymbols nodes into the appropriate instructions to
118 // materialize the address.
119 setOperationAction(ISD::GlobalAddress, MVT::i64, Custom);
120 setOperationAction(ISD::ConstantPool, MVT::i64, Custom);
121 setOperationAction(ISD::ExternalSymbol, MVT::i64, Custom);
122 setOperationAction(ISD::GlobalTLSAddress, MVT::i64, Custom);
124 setOperationAction(ISD::VASTART, MVT::Other, Custom);
125 setOperationAction(ISD::VAEND, MVT::Other, Expand);
126 setOperationAction(ISD::VACOPY, MVT::Other, Custom);
127 setOperationAction(ISD::VAARG, MVT::Other, Custom);
128 setOperationAction(ISD::VAARG, MVT::i32, Custom);
130 setOperationAction(ISD::RET, MVT::Other, Custom);
132 setOperationAction(ISD::JumpTable, MVT::i64, Custom);
133 setOperationAction(ISD::JumpTable, MVT::i32, Custom);
135 setStackPointerRegisterToSaveRestore(Alpha::R30);
137 addLegalFPImmediate(APFloat(+0.0)); //F31
138 addLegalFPImmediate(APFloat(+0.0f)); //F31
139 addLegalFPImmediate(APFloat(-0.0)); //-F31
140 addLegalFPImmediate(APFloat(-0.0f)); //-F31
143 setJumpBufAlignment(16);
145 computeRegisterProperties();
149 AlphaTargetLowering::getSetCCResultType(const SDOperand &) const {
153 const char *AlphaTargetLowering::getTargetNodeName(unsigned Opcode) const {
156 case AlphaISD::CVTQT_: return "Alpha::CVTQT_";
157 case AlphaISD::CVTQS_: return "Alpha::CVTQS_";
158 case AlphaISD::CVTTQ_: return "Alpha::CVTTQ_";
159 case AlphaISD::GPRelHi: return "Alpha::GPRelHi";
160 case AlphaISD::GPRelLo: return "Alpha::GPRelLo";
161 case AlphaISD::RelLit: return "Alpha::RelLit";
162 case AlphaISD::GlobalRetAddr: return "Alpha::GlobalRetAddr";
163 case AlphaISD::CALL: return "Alpha::CALL";
164 case AlphaISD::DivCall: return "Alpha::DivCall";
165 case AlphaISD::RET_FLAG: return "Alpha::RET_FLAG";
166 case AlphaISD::COND_BRANCH_I: return "Alpha::COND_BRANCH_I";
167 case AlphaISD::COND_BRANCH_F: return "Alpha::COND_BRANCH_F";
171 static SDOperand LowerJumpTable(SDOperand Op, SelectionDAG &DAG) {
172 MVT::ValueType PtrVT = Op.getValueType();
173 JumpTableSDNode *JT = cast<JumpTableSDNode>(Op);
174 SDOperand JTI = DAG.getTargetJumpTable(JT->getIndex(), PtrVT);
175 SDOperand Zero = DAG.getConstant(0, PtrVT);
177 SDOperand Hi = DAG.getNode(AlphaISD::GPRelHi, MVT::i64, JTI,
178 DAG.getNode(ISD::GLOBAL_OFFSET_TABLE, MVT::i64));
179 SDOperand Lo = DAG.getNode(AlphaISD::GPRelLo, MVT::i64, JTI, Hi);
183 //http://www.cs.arizona.edu/computer.help/policy/DIGITAL_unix/
184 //AA-PY8AC-TET1_html/callCH3.html#BLOCK21
186 //For now, just use variable size stack frame format
188 //In a standard call, the first six items are passed in registers $16
189 //- $21 and/or registers $f16 - $f21. (See Section 4.1.2 for details
190 //of argument-to-register correspondence.) The remaining items are
191 //collected in a memory argument list that is a naturally aligned
192 //array of quadwords. In a standard call, this list, if present, must
193 //be passed at 0(SP).
194 //7 ... n 0(SP) ... (n-7)*8(SP)
202 static SDOperand LowerFORMAL_ARGUMENTS(SDOperand Op, SelectionDAG &DAG,
204 int &VarArgsOffset) {
205 MachineFunction &MF = DAG.getMachineFunction();
206 MachineFrameInfo *MFI = MF.getFrameInfo();
207 std::vector<SDOperand> ArgValues;
208 SDOperand Root = Op.getOperand(0);
210 AddLiveIn(MF, Alpha::R29, &Alpha::GPRCRegClass); //GP
211 AddLiveIn(MF, Alpha::R26, &Alpha::GPRCRegClass); //RA
213 unsigned args_int[] = {
214 Alpha::R16, Alpha::R17, Alpha::R18, Alpha::R19, Alpha::R20, Alpha::R21};
215 unsigned args_float[] = {
216 Alpha::F16, Alpha::F17, Alpha::F18, Alpha::F19, Alpha::F20, Alpha::F21};
218 for (unsigned ArgNo = 0, e = Op.Val->getNumValues()-1; ArgNo != e; ++ArgNo) {
220 MVT::ValueType ObjectVT = Op.getValue(ArgNo).getValueType();
226 cerr << "Unknown Type " << ObjectVT << "\n";
229 args_float[ArgNo] = AddLiveIn(MF, args_float[ArgNo],
230 &Alpha::F8RCRegClass);
231 ArgVal = DAG.getCopyFromReg(Root, args_float[ArgNo], ObjectVT);
234 args_float[ArgNo] = AddLiveIn(MF, args_float[ArgNo],
235 &Alpha::F4RCRegClass);
236 ArgVal = DAG.getCopyFromReg(Root, args_float[ArgNo], ObjectVT);
239 args_int[ArgNo] = AddLiveIn(MF, args_int[ArgNo],
240 &Alpha::GPRCRegClass);
241 ArgVal = DAG.getCopyFromReg(Root, args_int[ArgNo], MVT::i64);
245 // Create the frame index object for this incoming parameter...
246 int FI = MFI->CreateFixedObject(8, 8 * (ArgNo - 6));
248 // Create the SelectionDAG nodes corresponding to a load
249 //from this parameter
250 SDOperand FIN = DAG.getFrameIndex(FI, MVT::i64);
251 ArgVal = DAG.getLoad(ObjectVT, Root, FIN, NULL, 0);
253 ArgValues.push_back(ArgVal);
256 // If the functions takes variable number of arguments, copy all regs to stack
257 bool isVarArg = cast<ConstantSDNode>(Op.getOperand(2))->getValue() != 0;
259 VarArgsOffset = (Op.Val->getNumValues()-1) * 8;
260 std::vector<SDOperand> LS;
261 for (int i = 0; i < 6; ++i) {
262 if (TargetRegisterInfo::isPhysicalRegister(args_int[i]))
263 args_int[i] = AddLiveIn(MF, args_int[i], &Alpha::GPRCRegClass);
264 SDOperand argt = DAG.getCopyFromReg(Root, args_int[i], MVT::i64);
265 int FI = MFI->CreateFixedObject(8, -8 * (6 - i));
266 if (i == 0) VarArgsBase = FI;
267 SDOperand SDFI = DAG.getFrameIndex(FI, MVT::i64);
268 LS.push_back(DAG.getStore(Root, argt, SDFI, NULL, 0));
270 if (TargetRegisterInfo::isPhysicalRegister(args_float[i]))
271 args_float[i] = AddLiveIn(MF, args_float[i], &Alpha::F8RCRegClass);
272 argt = DAG.getCopyFromReg(Root, args_float[i], MVT::f64);
273 FI = MFI->CreateFixedObject(8, - 8 * (12 - i));
274 SDFI = DAG.getFrameIndex(FI, MVT::i64);
275 LS.push_back(DAG.getStore(Root, argt, SDFI, NULL, 0));
278 //Set up a token factor with all the stack traffic
279 Root = DAG.getNode(ISD::TokenFactor, MVT::Other, &LS[0], LS.size());
282 ArgValues.push_back(Root);
284 // Return the new list of results.
285 std::vector<MVT::ValueType> RetVT(Op.Val->value_begin(),
286 Op.Val->value_end());
287 return DAG.getNode(ISD::MERGE_VALUES, RetVT, &ArgValues[0], ArgValues.size());
290 static SDOperand LowerRET(SDOperand Op, SelectionDAG &DAG) {
291 SDOperand Copy = DAG.getCopyToReg(Op.getOperand(0), Alpha::R26,
292 DAG.getNode(AlphaISD::GlobalRetAddr,
295 switch (Op.getNumOperands()) {
297 assert(0 && "Do not know how to return this many arguments!");
301 //return SDOperand(); // ret void is legal
303 MVT::ValueType ArgVT = Op.getOperand(1).getValueType();
305 if (MVT::isInteger(ArgVT))
308 assert(MVT::isFloatingPoint(ArgVT));
311 Copy = DAG.getCopyToReg(Copy, ArgReg, Op.getOperand(1), Copy.getValue(1));
312 if (DAG.getMachineFunction().getRegInfo().liveout_empty())
313 DAG.getMachineFunction().getRegInfo().addLiveOut(ArgReg);
317 return DAG.getNode(AlphaISD::RET_FLAG, MVT::Other, Copy, Copy.getValue(1));
320 std::pair<SDOperand, SDOperand>
321 AlphaTargetLowering::LowerCallTo(SDOperand Chain, const Type *RetTy,
322 bool RetSExt, bool RetZExt, bool isVarArg,
323 unsigned CallingConv, bool isTailCall,
324 SDOperand Callee, ArgListTy &Args,
328 NumBytes = (Args.size() - 6) * 8;
330 Chain = DAG.getCALLSEQ_START(Chain,
331 DAG.getConstant(NumBytes, getPointerTy()));
332 std::vector<SDOperand> args_to_use;
333 for (unsigned i = 0, e = Args.size(); i != e; ++i)
335 switch (getValueType(Args[i].Ty)) {
336 default: assert(0 && "Unexpected ValueType for argument!");
341 // Promote the integer to 64 bits. If the input type is signed use a
342 // sign extend, otherwise use a zero extend.
344 Args[i].Node = DAG.getNode(ISD::SIGN_EXTEND, MVT::i64, Args[i].Node);
345 else if (Args[i].isZExt)
346 Args[i].Node = DAG.getNode(ISD::ZERO_EXTEND, MVT::i64, Args[i].Node);
348 Args[i].Node = DAG.getNode(ISD::ANY_EXTEND, MVT::i64, Args[i].Node);
355 args_to_use.push_back(Args[i].Node);
358 std::vector<MVT::ValueType> RetVals;
359 MVT::ValueType RetTyVT = getValueType(RetTy);
360 MVT::ValueType ActualRetTyVT = RetTyVT;
361 if (RetTyVT >= MVT::i1 && RetTyVT <= MVT::i32)
362 ActualRetTyVT = MVT::i64;
364 if (RetTyVT != MVT::isVoid)
365 RetVals.push_back(ActualRetTyVT);
366 RetVals.push_back(MVT::Other);
368 std::vector<SDOperand> Ops;
369 Ops.push_back(Chain);
370 Ops.push_back(Callee);
371 Ops.insert(Ops.end(), args_to_use.begin(), args_to_use.end());
372 SDOperand TheCall = DAG.getNode(AlphaISD::CALL, RetVals, &Ops[0], Ops.size());
373 Chain = TheCall.getValue(RetTyVT != MVT::isVoid);
374 Chain = DAG.getCALLSEQ_END(Chain,
375 DAG.getConstant(NumBytes, getPointerTy()),
376 DAG.getConstant(0, getPointerTy()),
378 SDOperand RetVal = TheCall;
380 if (RetTyVT != ActualRetTyVT) {
381 ISD::NodeType AssertKind = ISD::DELETED_NODE;
383 AssertKind = ISD::AssertSext;
385 AssertKind = ISD::AssertZext;
387 if (AssertKind != ISD::DELETED_NODE)
388 RetVal = DAG.getNode(AssertKind, MVT::i64, RetVal,
389 DAG.getValueType(RetTyVT));
391 RetVal = DAG.getNode(ISD::TRUNCATE, RetTyVT, RetVal);
394 return std::make_pair(RetVal, Chain);
397 /// LowerOperation - Provide custom lowering hooks for some operations.
399 SDOperand AlphaTargetLowering::LowerOperation(SDOperand Op, SelectionDAG &DAG) {
400 switch (Op.getOpcode()) {
401 default: assert(0 && "Wasn't expecting to be able to lower this!");
402 case ISD::FORMAL_ARGUMENTS: return LowerFORMAL_ARGUMENTS(Op, DAG,
406 case ISD::RET: return LowerRET(Op,DAG);
407 case ISD::JumpTable: return LowerJumpTable(Op, DAG);
409 case ISD::SINT_TO_FP: {
410 assert(MVT::i64 == Op.getOperand(0).getValueType() &&
411 "Unhandled SINT_TO_FP type in custom expander!");
413 bool isDouble = MVT::f64 == Op.getValueType();
414 LD = DAG.getNode(ISD::BIT_CONVERT, MVT::f64, Op.getOperand(0));
415 SDOperand FP = DAG.getNode(isDouble?AlphaISD::CVTQT_:AlphaISD::CVTQS_,
416 isDouble?MVT::f64:MVT::f32, LD);
419 case ISD::FP_TO_SINT: {
420 bool isDouble = MVT::f64 == Op.getOperand(0).getValueType();
421 SDOperand src = Op.getOperand(0);
423 if (!isDouble) //Promote
424 src = DAG.getNode(ISD::FP_EXTEND, MVT::f64, src);
426 src = DAG.getNode(AlphaISD::CVTTQ_, MVT::f64, src);
428 return DAG.getNode(ISD::BIT_CONVERT, MVT::i64, src);
430 case ISD::ConstantPool: {
431 ConstantPoolSDNode *CP = cast<ConstantPoolSDNode>(Op);
432 Constant *C = CP->getConstVal();
433 SDOperand CPI = DAG.getTargetConstantPool(C, MVT::i64, CP->getAlignment());
435 SDOperand Hi = DAG.getNode(AlphaISD::GPRelHi, MVT::i64, CPI,
436 DAG.getNode(ISD::GLOBAL_OFFSET_TABLE, MVT::i64));
437 SDOperand Lo = DAG.getNode(AlphaISD::GPRelLo, MVT::i64, CPI, Hi);
440 case ISD::GlobalTLSAddress:
441 assert(0 && "TLS not implemented for Alpha.");
442 case ISD::GlobalAddress: {
443 GlobalAddressSDNode *GSDN = cast<GlobalAddressSDNode>(Op);
444 GlobalValue *GV = GSDN->getGlobal();
445 SDOperand GA = DAG.getTargetGlobalAddress(GV, MVT::i64, GSDN->getOffset());
447 // if (!GV->hasWeakLinkage() && !GV->isDeclaration() && !GV->hasLinkOnceLinkage()) {
448 if (GV->hasInternalLinkage()) {
449 SDOperand Hi = DAG.getNode(AlphaISD::GPRelHi, MVT::i64, GA,
450 DAG.getNode(ISD::GLOBAL_OFFSET_TABLE, MVT::i64));
451 SDOperand Lo = DAG.getNode(AlphaISD::GPRelLo, MVT::i64, GA, Hi);
454 return DAG.getNode(AlphaISD::RelLit, MVT::i64, GA,
455 DAG.getNode(ISD::GLOBAL_OFFSET_TABLE, MVT::i64));
457 case ISD::ExternalSymbol: {
458 return DAG.getNode(AlphaISD::RelLit, MVT::i64,
459 DAG.getTargetExternalSymbol(cast<ExternalSymbolSDNode>(Op)
460 ->getSymbol(), MVT::i64),
461 DAG.getNode(ISD::GLOBAL_OFFSET_TABLE, MVT::i64));
466 //Expand only on constant case
467 if (Op.getOperand(1).getOpcode() == ISD::Constant) {
468 MVT::ValueType VT = Op.Val->getValueType(0);
469 SDOperand Tmp1 = Op.Val->getOpcode() == ISD::UREM ?
470 BuildUDIV(Op.Val, DAG, NULL) :
471 BuildSDIV(Op.Val, DAG, NULL);
472 Tmp1 = DAG.getNode(ISD::MUL, VT, Tmp1, Op.getOperand(1));
473 Tmp1 = DAG.getNode(ISD::SUB, VT, Op.getOperand(0), Tmp1);
479 if (MVT::isInteger(Op.getValueType())) {
480 if (Op.getOperand(1).getOpcode() == ISD::Constant)
481 return Op.getOpcode() == ISD::SDIV ? BuildSDIV(Op.Val, DAG, NULL)
482 : BuildUDIV(Op.Val, DAG, NULL);
483 const char* opstr = 0;
484 switch (Op.getOpcode()) {
485 case ISD::UREM: opstr = "__remqu"; break;
486 case ISD::SREM: opstr = "__remq"; break;
487 case ISD::UDIV: opstr = "__divqu"; break;
488 case ISD::SDIV: opstr = "__divq"; break;
490 SDOperand Tmp1 = Op.getOperand(0),
491 Tmp2 = Op.getOperand(1),
492 Addr = DAG.getExternalSymbol(opstr, MVT::i64);
493 return DAG.getNode(AlphaISD::DivCall, MVT::i64, Addr, Tmp1, Tmp2);
498 SDOperand Chain = Op.getOperand(0);
499 SDOperand VAListP = Op.getOperand(1);
500 const Value *VAListS = cast<SrcValueSDNode>(Op.getOperand(2))->getValue();
502 SDOperand Base = DAG.getLoad(MVT::i64, Chain, VAListP, VAListS, 0);
503 SDOperand Tmp = DAG.getNode(ISD::ADD, MVT::i64, VAListP,
504 DAG.getConstant(8, MVT::i64));
505 SDOperand Offset = DAG.getExtLoad(ISD::SEXTLOAD, MVT::i64, Base.getValue(1),
506 Tmp, NULL, 0, MVT::i32);
507 SDOperand DataPtr = DAG.getNode(ISD::ADD, MVT::i64, Base, Offset);
508 if (MVT::isFloatingPoint(Op.getValueType()))
510 //if fp && Offset < 6*8, then subtract 6*8 from DataPtr
511 SDOperand FPDataPtr = DAG.getNode(ISD::SUB, MVT::i64, DataPtr,
512 DAG.getConstant(8*6, MVT::i64));
513 SDOperand CC = DAG.getSetCC(MVT::i64, Offset,
514 DAG.getConstant(8*6, MVT::i64), ISD::SETLT);
515 DataPtr = DAG.getNode(ISD::SELECT, MVT::i64, CC, FPDataPtr, DataPtr);
518 SDOperand NewOffset = DAG.getNode(ISD::ADD, MVT::i64, Offset,
519 DAG.getConstant(8, MVT::i64));
520 SDOperand Update = DAG.getTruncStore(Offset.getValue(1), NewOffset,
521 Tmp, NULL, 0, MVT::i32);
524 if (Op.getValueType() == MVT::i32)
525 Result = DAG.getExtLoad(ISD::SEXTLOAD, MVT::i64, Update, DataPtr,
528 Result = DAG.getLoad(Op.getValueType(), Update, DataPtr, NULL, 0);
532 SDOperand Chain = Op.getOperand(0);
533 SDOperand DestP = Op.getOperand(1);
534 SDOperand SrcP = Op.getOperand(2);
535 const Value *DestS = cast<SrcValueSDNode>(Op.getOperand(3))->getValue();
536 const Value *SrcS = cast<SrcValueSDNode>(Op.getOperand(4))->getValue();
538 SDOperand Val = DAG.getLoad(getPointerTy(), Chain, SrcP, SrcS, 0);
539 SDOperand Result = DAG.getStore(Val.getValue(1), Val, DestP, DestS, 0);
540 SDOperand NP = DAG.getNode(ISD::ADD, MVT::i64, SrcP,
541 DAG.getConstant(8, MVT::i64));
542 Val = DAG.getExtLoad(ISD::SEXTLOAD, MVT::i64, Result, NP, NULL,0, MVT::i32);
543 SDOperand NPD = DAG.getNode(ISD::ADD, MVT::i64, DestP,
544 DAG.getConstant(8, MVT::i64));
545 return DAG.getTruncStore(Val.getValue(1), Val, NPD, NULL, 0, MVT::i32);
548 SDOperand Chain = Op.getOperand(0);
549 SDOperand VAListP = Op.getOperand(1);
550 const Value *VAListS = cast<SrcValueSDNode>(Op.getOperand(2))->getValue();
552 // vastart stores the address of the VarArgsBase and VarArgsOffset
553 SDOperand FR = DAG.getFrameIndex(VarArgsBase, MVT::i64);
554 SDOperand S1 = DAG.getStore(Chain, FR, VAListP, VAListS, 0);
555 SDOperand SA2 = DAG.getNode(ISD::ADD, MVT::i64, VAListP,
556 DAG.getConstant(8, MVT::i64));
557 return DAG.getTruncStore(S1, DAG.getConstant(VarArgsOffset, MVT::i64),
558 SA2, NULL, 0, MVT::i32);
560 case ISD::RETURNADDR:
561 return DAG.getNode(AlphaISD::GlobalRetAddr, MVT::i64);
563 case ISD::FRAMEADDR: break;
569 SDOperand AlphaTargetLowering::CustomPromoteOperation(SDOperand Op,
571 assert(Op.getValueType() == MVT::i32 &&
572 Op.getOpcode() == ISD::VAARG &&
573 "Unknown node to custom promote!");
575 // The code in LowerOperation already handles i32 vaarg
576 return LowerOperation(Op, DAG);
582 /// getConstraintType - Given a constraint letter, return the type of
583 /// constraint it is for this target.
584 AlphaTargetLowering::ConstraintType
585 AlphaTargetLowering::getConstraintType(const std::string &Constraint) const {
586 if (Constraint.size() == 1) {
587 switch (Constraint[0]) {
591 return C_RegisterClass;
594 return TargetLowering::getConstraintType(Constraint);
597 std::vector<unsigned> AlphaTargetLowering::
598 getRegClassForInlineAsmConstraint(const std::string &Constraint,
599 MVT::ValueType VT) const {
600 if (Constraint.size() == 1) {
601 switch (Constraint[0]) {
602 default: break; // Unknown constriant letter
604 return make_vector<unsigned>(Alpha::F0 , Alpha::F1 , Alpha::F2 ,
605 Alpha::F3 , Alpha::F4 , Alpha::F5 ,
606 Alpha::F6 , Alpha::F7 , Alpha::F8 ,
607 Alpha::F9 , Alpha::F10, Alpha::F11,
608 Alpha::F12, Alpha::F13, Alpha::F14,
609 Alpha::F15, Alpha::F16, Alpha::F17,
610 Alpha::F18, Alpha::F19, Alpha::F20,
611 Alpha::F21, Alpha::F22, Alpha::F23,
612 Alpha::F24, Alpha::F25, Alpha::F26,
613 Alpha::F27, Alpha::F28, Alpha::F29,
614 Alpha::F30, Alpha::F31, 0);
616 return make_vector<unsigned>(Alpha::R0 , Alpha::R1 , Alpha::R2 ,
617 Alpha::R3 , Alpha::R4 , Alpha::R5 ,
618 Alpha::R6 , Alpha::R7 , Alpha::R8 ,
619 Alpha::R9 , Alpha::R10, Alpha::R11,
620 Alpha::R12, Alpha::R13, Alpha::R14,
621 Alpha::R15, Alpha::R16, Alpha::R17,
622 Alpha::R18, Alpha::R19, Alpha::R20,
623 Alpha::R21, Alpha::R22, Alpha::R23,
624 Alpha::R24, Alpha::R25, Alpha::R26,
625 Alpha::R27, Alpha::R28, Alpha::R29,
626 Alpha::R30, Alpha::R31, 0);
630 return std::vector<unsigned>();
632 //===----------------------------------------------------------------------===//
633 // Other Lowering Code
634 //===----------------------------------------------------------------------===//
637 AlphaTargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI,
638 MachineBasicBlock *BB) {
639 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
640 assert((MI->getOpcode() == Alpha::CAS32 ||
641 MI->getOpcode() == Alpha::CAS64 ||
642 MI->getOpcode() == Alpha::LAS32 ||
643 MI->getOpcode() == Alpha::LAS64 ||
644 MI->getOpcode() == Alpha::SWAP32 ||
645 MI->getOpcode() == Alpha::SWAP64) &&
646 "Unexpected instr type to insert");
648 bool is32 = MI->getOpcode() == Alpha::CAS32 ||
649 MI->getOpcode() == Alpha::LAS32 ||
650 MI->getOpcode() == Alpha::SWAP32;
652 //Load locked store conditional for atomic ops take on the same form
655 //do stuff (maybe branch to exit)
657 //test sc and maybe branck to start
659 const BasicBlock *LLVM_BB = BB->getBasicBlock();
660 ilist<MachineBasicBlock>::iterator It = BB;
663 MachineBasicBlock *thisMBB = BB;
664 MachineBasicBlock *llscMBB = new MachineBasicBlock(LLVM_BB);
665 MachineBasicBlock *sinkMBB = new MachineBasicBlock(LLVM_BB);
667 for(MachineBasicBlock::succ_iterator i = thisMBB->succ_begin(),
668 e = thisMBB->succ_end(); i != e; ++i)
669 sinkMBB->addSuccessor(*i);
670 while(!thisMBB->succ_empty())
671 thisMBB->removeSuccessor(thisMBB->succ_begin());
673 MachineFunction *F = BB->getParent();
674 F->getBasicBlockList().insert(It, llscMBB);
675 F->getBasicBlockList().insert(It, sinkMBB);
677 BuildMI(thisMBB, TII->get(Alpha::BR)).addMBB(llscMBB);
679 unsigned reg_res = MI->getOperand(0).getReg(),
680 reg_ptr = MI->getOperand(1).getReg(),
681 reg_v2 = MI->getOperand(2).getReg(),
682 reg_store = F->getRegInfo().createVirtualRegister(&Alpha::GPRCRegClass);
684 BuildMI(llscMBB, TII->get(is32 ? Alpha::LDL_L : Alpha::LDQ_L),
685 reg_res).addImm(0).addReg(reg_ptr);
686 switch (MI->getOpcode()) {
690 = F->getRegInfo().createVirtualRegister(&Alpha::GPRCRegClass);
691 BuildMI(llscMBB, TII->get(Alpha::CMPEQ), reg_cmp)
692 .addReg(reg_v2).addReg(reg_res);
693 BuildMI(llscMBB, TII->get(Alpha::BEQ))
694 .addImm(0).addReg(reg_cmp).addMBB(sinkMBB);
695 BuildMI(llscMBB, TII->get(Alpha::BISr), reg_store)
696 .addReg(Alpha::R31).addReg(MI->getOperand(3).getReg());
701 BuildMI(llscMBB, TII->get(is32 ? Alpha::ADDLr : Alpha::ADDQr), reg_store)
702 .addReg(reg_res).addReg(reg_v2);
706 case Alpha::SWAP64: {
707 BuildMI(llscMBB, TII->get(Alpha::BISr), reg_store)
708 .addReg(reg_v2).addReg(reg_v2);
712 BuildMI(llscMBB, TII->get(is32 ? Alpha::STL_C : Alpha::STQ_C), reg_store)
713 .addReg(reg_store).addImm(0).addReg(reg_ptr);
714 BuildMI(llscMBB, TII->get(Alpha::BEQ))
715 .addImm(0).addReg(reg_store).addMBB(llscMBB);
716 BuildMI(llscMBB, TII->get(Alpha::BR)).addMBB(sinkMBB);
718 thisMBB->addSuccessor(llscMBB);
719 llscMBB->addSuccessor(llscMBB);
720 llscMBB->addSuccessor(sinkMBB);
721 delete MI; // The pseudo instruction is gone now.