1 //===-- AlphaISelLowering.cpp - Alpha DAG Lowering Implementation ---------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file implements the AlphaISelLowering class.
12 //===----------------------------------------------------------------------===//
14 #include "AlphaISelLowering.h"
15 #include "AlphaTargetMachine.h"
16 #include "llvm/CodeGen/CallingConvLower.h"
17 #include "llvm/CodeGen/MachineFrameInfo.h"
18 #include "llvm/CodeGen/MachineFunction.h"
19 #include "llvm/CodeGen/MachineInstrBuilder.h"
20 #include "llvm/CodeGen/MachineRegisterInfo.h"
21 #include "llvm/CodeGen/SelectionDAG.h"
22 #include "llvm/CodeGen/MachineRegisterInfo.h"
23 #include "llvm/CodeGen/PseudoSourceValue.h"
24 #include "llvm/CodeGen/TargetLoweringObjectFileImpl.h"
25 #include "llvm/Constants.h"
26 #include "llvm/Function.h"
27 #include "llvm/Module.h"
28 #include "llvm/Intrinsics.h"
29 #include "llvm/Support/CommandLine.h"
30 #include "llvm/Support/ErrorHandling.h"
31 #include "llvm/Support/raw_ostream.h"
34 /// AddLiveIn - This helper function adds the specified physical register to the
35 /// MachineFunction as a live in value. It also creates a corresponding virtual
37 static unsigned AddLiveIn(MachineFunction &MF, unsigned PReg,
38 TargetRegisterClass *RC) {
39 assert(RC->contains(PReg) && "Not the correct regclass!");
40 unsigned VReg = MF.getRegInfo().createVirtualRegister(RC);
41 MF.getRegInfo().addLiveIn(PReg, VReg);
45 AlphaTargetLowering::AlphaTargetLowering(TargetMachine &TM)
46 : TargetLowering(TM, new TargetLoweringObjectFileELF()) {
47 // Set up the TargetLowering object.
48 //I am having problems with shr n i8 1
49 setShiftAmountType(MVT::i64);
50 setBooleanContents(ZeroOrOneBooleanContent);
52 addRegisterClass(MVT::i64, Alpha::GPRCRegisterClass);
53 addRegisterClass(MVT::f64, Alpha::F8RCRegisterClass);
54 addRegisterClass(MVT::f32, Alpha::F4RCRegisterClass);
56 // We want to custom lower some of our intrinsics.
57 setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::Other, Custom);
59 setLoadExtAction(ISD::EXTLOAD, MVT::i1, Promote);
60 setLoadExtAction(ISD::EXTLOAD, MVT::f32, Expand);
62 setLoadExtAction(ISD::ZEXTLOAD, MVT::i1, Promote);
63 setLoadExtAction(ISD::ZEXTLOAD, MVT::i32, Expand);
65 setLoadExtAction(ISD::SEXTLOAD, MVT::i1, Promote);
66 setLoadExtAction(ISD::SEXTLOAD, MVT::i8, Expand);
67 setLoadExtAction(ISD::SEXTLOAD, MVT::i16, Expand);
69 setTruncStoreAction(MVT::f64, MVT::f32, Expand);
71 // setOperationAction(ISD::BRIND, MVT::Other, Expand);
72 setOperationAction(ISD::BR_JT, MVT::Other, Expand);
73 setOperationAction(ISD::BR_CC, MVT::Other, Expand);
74 setOperationAction(ISD::SELECT_CC, MVT::Other, Expand);
76 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1, Expand);
78 setOperationAction(ISD::FREM, MVT::f32, Expand);
79 setOperationAction(ISD::FREM, MVT::f64, Expand);
81 setOperationAction(ISD::UINT_TO_FP, MVT::i64, Expand);
82 setOperationAction(ISD::SINT_TO_FP, MVT::i64, Custom);
83 setOperationAction(ISD::FP_TO_UINT, MVT::i64, Expand);
84 setOperationAction(ISD::FP_TO_SINT, MVT::i64, Custom);
86 if (!TM.getSubtarget<AlphaSubtarget>().hasCT()) {
87 setOperationAction(ISD::CTPOP , MVT::i64 , Expand);
88 setOperationAction(ISD::CTTZ , MVT::i64 , Expand);
89 setOperationAction(ISD::CTLZ , MVT::i64 , Expand);
91 setOperationAction(ISD::BSWAP , MVT::i64, Expand);
92 setOperationAction(ISD::ROTL , MVT::i64, Expand);
93 setOperationAction(ISD::ROTR , MVT::i64, Expand);
95 setOperationAction(ISD::SREM , MVT::i64, Custom);
96 setOperationAction(ISD::UREM , MVT::i64, Custom);
97 setOperationAction(ISD::SDIV , MVT::i64, Custom);
98 setOperationAction(ISD::UDIV , MVT::i64, Custom);
100 setOperationAction(ISD::ADDC , MVT::i64, Expand);
101 setOperationAction(ISD::ADDE , MVT::i64, Expand);
102 setOperationAction(ISD::SUBC , MVT::i64, Expand);
103 setOperationAction(ISD::SUBE , MVT::i64, Expand);
105 setOperationAction(ISD::UMUL_LOHI, MVT::i64, Expand);
106 setOperationAction(ISD::SMUL_LOHI, MVT::i64, Expand);
108 setOperationAction(ISD::SRL_PARTS, MVT::i64, Custom);
109 setOperationAction(ISD::SRA_PARTS, MVT::i64, Expand);
110 setOperationAction(ISD::SHL_PARTS, MVT::i64, Expand);
112 // We don't support sin/cos/sqrt/pow
113 setOperationAction(ISD::FSIN , MVT::f64, Expand);
114 setOperationAction(ISD::FCOS , MVT::f64, Expand);
115 setOperationAction(ISD::FSIN , MVT::f32, Expand);
116 setOperationAction(ISD::FCOS , MVT::f32, Expand);
118 setOperationAction(ISD::FSQRT, MVT::f64, Expand);
119 setOperationAction(ISD::FSQRT, MVT::f32, Expand);
121 setOperationAction(ISD::FPOW , MVT::f32, Expand);
122 setOperationAction(ISD::FPOW , MVT::f64, Expand);
124 setOperationAction(ISD::SETCC, MVT::f32, Promote);
126 setOperationAction(ISD::BIT_CONVERT, MVT::f32, Promote);
128 setOperationAction(ISD::EH_LABEL, MVT::Other, Expand);
130 // Not implemented yet.
131 setOperationAction(ISD::STACKSAVE, MVT::Other, Expand);
132 setOperationAction(ISD::STACKRESTORE, MVT::Other, Expand);
133 setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i64, Expand);
135 // We want to legalize GlobalAddress and ConstantPool and
136 // ExternalSymbols nodes into the appropriate instructions to
137 // materialize the address.
138 setOperationAction(ISD::GlobalAddress, MVT::i64, Custom);
139 setOperationAction(ISD::ConstantPool, MVT::i64, Custom);
140 setOperationAction(ISD::ExternalSymbol, MVT::i64, Custom);
141 setOperationAction(ISD::GlobalTLSAddress, MVT::i64, Custom);
143 setOperationAction(ISD::VASTART, MVT::Other, Custom);
144 setOperationAction(ISD::VAEND, MVT::Other, Expand);
145 setOperationAction(ISD::VACOPY, MVT::Other, Custom);
146 setOperationAction(ISD::VAARG, MVT::Other, Custom);
147 setOperationAction(ISD::VAARG, MVT::i32, Custom);
149 setOperationAction(ISD::JumpTable, MVT::i64, Custom);
150 setOperationAction(ISD::JumpTable, MVT::i32, Custom);
152 setStackPointerRegisterToSaveRestore(Alpha::R30);
155 setJumpBufAlignment(16);
157 computeRegisterProperties();
160 MVT::SimpleValueType AlphaTargetLowering::getSetCCResultType(EVT VT) const {
164 const char *AlphaTargetLowering::getTargetNodeName(unsigned Opcode) const {
167 case AlphaISD::CVTQT_: return "Alpha::CVTQT_";
168 case AlphaISD::CVTQS_: return "Alpha::CVTQS_";
169 case AlphaISD::CVTTQ_: return "Alpha::CVTTQ_";
170 case AlphaISD::GPRelHi: return "Alpha::GPRelHi";
171 case AlphaISD::GPRelLo: return "Alpha::GPRelLo";
172 case AlphaISD::RelLit: return "Alpha::RelLit";
173 case AlphaISD::GlobalRetAddr: return "Alpha::GlobalRetAddr";
174 case AlphaISD::CALL: return "Alpha::CALL";
175 case AlphaISD::DivCall: return "Alpha::DivCall";
176 case AlphaISD::RET_FLAG: return "Alpha::RET_FLAG";
177 case AlphaISD::COND_BRANCH_I: return "Alpha::COND_BRANCH_I";
178 case AlphaISD::COND_BRANCH_F: return "Alpha::COND_BRANCH_F";
182 /// getFunctionAlignment - Return the Log2 alignment of this function.
183 unsigned AlphaTargetLowering::getFunctionAlignment(const Function *F) const {
187 static SDValue LowerJumpTable(SDValue Op, SelectionDAG &DAG) {
188 EVT PtrVT = Op.getValueType();
189 JumpTableSDNode *JT = cast<JumpTableSDNode>(Op);
190 SDValue JTI = DAG.getTargetJumpTable(JT->getIndex(), PtrVT);
191 // FIXME there isn't really any debug info here
192 DebugLoc dl = Op.getDebugLoc();
194 SDValue Hi = DAG.getNode(AlphaISD::GPRelHi, dl, MVT::i64, JTI,
195 DAG.getGLOBAL_OFFSET_TABLE(MVT::i64));
196 SDValue Lo = DAG.getNode(AlphaISD::GPRelLo, dl, MVT::i64, JTI, Hi);
200 //http://www.cs.arizona.edu/computer.help/policy/DIGITAL_unix/
201 //AA-PY8AC-TET1_html/callCH3.html#BLOCK21
203 //For now, just use variable size stack frame format
205 //In a standard call, the first six items are passed in registers $16
206 //- $21 and/or registers $f16 - $f21. (See Section 4.1.2 for details
207 //of argument-to-register correspondence.) The remaining items are
208 //collected in a memory argument list that is a naturally aligned
209 //array of quadwords. In a standard call, this list, if present, must
210 //be passed at 0(SP).
211 //7 ... n 0(SP) ... (n-7)*8(SP)
219 #include "AlphaGenCallingConv.inc"
222 AlphaTargetLowering::LowerCall(SDValue Chain, SDValue Callee,
223 CallingConv::ID CallConv, bool isVarArg,
225 const SmallVectorImpl<ISD::OutputArg> &Outs,
226 const SmallVectorImpl<ISD::InputArg> &Ins,
227 DebugLoc dl, SelectionDAG &DAG,
228 SmallVectorImpl<SDValue> &InVals) {
229 // Alpha target does not yet support tail call optimization.
232 // Analyze operands of the call, assigning locations to each operand.
233 SmallVector<CCValAssign, 16> ArgLocs;
234 CCState CCInfo(CallConv, isVarArg, getTargetMachine(),
235 ArgLocs, *DAG.getContext());
237 CCInfo.AnalyzeCallOperands(Outs, CC_Alpha);
239 // Get a count of how many bytes are to be pushed on the stack.
240 unsigned NumBytes = CCInfo.getNextStackOffset();
242 Chain = DAG.getCALLSEQ_START(Chain, DAG.getConstant(NumBytes,
243 getPointerTy(), true));
245 SmallVector<std::pair<unsigned, SDValue>, 4> RegsToPass;
246 SmallVector<SDValue, 12> MemOpChains;
249 // Walk the register/memloc assignments, inserting copies/loads.
250 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
251 CCValAssign &VA = ArgLocs[i];
253 SDValue Arg = Outs[i].Val;
255 // Promote the value if needed.
256 switch (VA.getLocInfo()) {
257 default: assert(0 && "Unknown loc info!");
258 case CCValAssign::Full: break;
259 case CCValAssign::SExt:
260 Arg = DAG.getNode(ISD::SIGN_EXTEND, dl, VA.getLocVT(), Arg);
262 case CCValAssign::ZExt:
263 Arg = DAG.getNode(ISD::ZERO_EXTEND, dl, VA.getLocVT(), Arg);
265 case CCValAssign::AExt:
266 Arg = DAG.getNode(ISD::ANY_EXTEND, dl, VA.getLocVT(), Arg);
270 // Arguments that can be passed on register must be kept at RegsToPass
273 RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg));
275 assert(VA.isMemLoc());
277 if (StackPtr.getNode() == 0)
278 StackPtr = DAG.getCopyFromReg(Chain, dl, Alpha::R30, MVT::i64);
280 SDValue PtrOff = DAG.getNode(ISD::ADD, dl, getPointerTy(),
282 DAG.getIntPtrConstant(VA.getLocMemOffset()));
284 MemOpChains.push_back(DAG.getStore(Chain, dl, Arg, PtrOff,
285 PseudoSourceValue::getStack(), 0,
290 // Transform all store nodes into one single node because all store nodes are
291 // independent of each other.
292 if (!MemOpChains.empty())
293 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
294 &MemOpChains[0], MemOpChains.size());
296 // Build a sequence of copy-to-reg nodes chained together with token chain and
297 // flag operands which copy the outgoing args into registers. The InFlag in
298 // necessary since all emited instructions must be stuck together.
300 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) {
301 Chain = DAG.getCopyToReg(Chain, dl, RegsToPass[i].first,
302 RegsToPass[i].second, InFlag);
303 InFlag = Chain.getValue(1);
306 // Returns a chain & a flag for retval copy to use.
307 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Flag);
308 SmallVector<SDValue, 8> Ops;
309 Ops.push_back(Chain);
310 Ops.push_back(Callee);
312 // Add argument registers to the end of the list so that they are
313 // known live into the call.
314 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i)
315 Ops.push_back(DAG.getRegister(RegsToPass[i].first,
316 RegsToPass[i].second.getValueType()));
318 if (InFlag.getNode())
319 Ops.push_back(InFlag);
321 Chain = DAG.getNode(AlphaISD::CALL, dl, NodeTys, &Ops[0], Ops.size());
322 InFlag = Chain.getValue(1);
324 // Create the CALLSEQ_END node.
325 Chain = DAG.getCALLSEQ_END(Chain,
326 DAG.getConstant(NumBytes, getPointerTy(), true),
327 DAG.getConstant(0, getPointerTy(), true),
329 InFlag = Chain.getValue(1);
331 // Handle result values, copying them out of physregs into vregs that we
333 return LowerCallResult(Chain, InFlag, CallConv, isVarArg,
334 Ins, dl, DAG, InVals);
337 /// LowerCallResult - Lower the result values of a call into the
338 /// appropriate copies out of appropriate physical registers.
341 AlphaTargetLowering::LowerCallResult(SDValue Chain, SDValue InFlag,
342 CallingConv::ID CallConv, bool isVarArg,
343 const SmallVectorImpl<ISD::InputArg> &Ins,
344 DebugLoc dl, SelectionDAG &DAG,
345 SmallVectorImpl<SDValue> &InVals) {
347 // Assign locations to each value returned by this call.
348 SmallVector<CCValAssign, 16> RVLocs;
349 CCState CCInfo(CallConv, isVarArg, getTargetMachine(), RVLocs,
352 CCInfo.AnalyzeCallResult(Ins, RetCC_Alpha);
354 // Copy all of the result registers out of their specified physreg.
355 for (unsigned i = 0; i != RVLocs.size(); ++i) {
356 CCValAssign &VA = RVLocs[i];
358 Chain = DAG.getCopyFromReg(Chain, dl, VA.getLocReg(),
359 VA.getLocVT(), InFlag).getValue(1);
360 SDValue RetValue = Chain.getValue(0);
361 InFlag = Chain.getValue(2);
363 // If this is an 8/16/32-bit value, it is really passed promoted to 64
364 // bits. Insert an assert[sz]ext to capture this, then truncate to the
366 if (VA.getLocInfo() == CCValAssign::SExt)
367 RetValue = DAG.getNode(ISD::AssertSext, dl, VA.getLocVT(), RetValue,
368 DAG.getValueType(VA.getValVT()));
369 else if (VA.getLocInfo() == CCValAssign::ZExt)
370 RetValue = DAG.getNode(ISD::AssertZext, dl, VA.getLocVT(), RetValue,
371 DAG.getValueType(VA.getValVT()));
373 if (VA.getLocInfo() != CCValAssign::Full)
374 RetValue = DAG.getNode(ISD::TRUNCATE, dl, VA.getValVT(), RetValue);
376 InVals.push_back(RetValue);
383 AlphaTargetLowering::LowerFormalArguments(SDValue Chain,
384 CallingConv::ID CallConv, bool isVarArg,
385 const SmallVectorImpl<ISD::InputArg>
387 DebugLoc dl, SelectionDAG &DAG,
388 SmallVectorImpl<SDValue> &InVals) {
390 MachineFunction &MF = DAG.getMachineFunction();
391 MachineFrameInfo *MFI = MF.getFrameInfo();
393 unsigned args_int[] = {
394 Alpha::R16, Alpha::R17, Alpha::R18, Alpha::R19, Alpha::R20, Alpha::R21};
395 unsigned args_float[] = {
396 Alpha::F16, Alpha::F17, Alpha::F18, Alpha::F19, Alpha::F20, Alpha::F21};
398 for (unsigned ArgNo = 0, e = Ins.size(); ArgNo != e; ++ArgNo) {
400 EVT ObjectVT = Ins[ArgNo].VT;
404 switch (ObjectVT.getSimpleVT().SimpleTy) {
406 assert(false && "Invalid value type!");
408 args_float[ArgNo] = AddLiveIn(MF, args_float[ArgNo],
409 &Alpha::F8RCRegClass);
410 ArgVal = DAG.getCopyFromReg(Chain, dl, args_float[ArgNo], ObjectVT);
413 args_float[ArgNo] = AddLiveIn(MF, args_float[ArgNo],
414 &Alpha::F4RCRegClass);
415 ArgVal = DAG.getCopyFromReg(Chain, dl, args_float[ArgNo], ObjectVT);
418 args_int[ArgNo] = AddLiveIn(MF, args_int[ArgNo],
419 &Alpha::GPRCRegClass);
420 ArgVal = DAG.getCopyFromReg(Chain, dl, args_int[ArgNo], MVT::i64);
424 // Create the frame index object for this incoming parameter...
425 int FI = MFI->CreateFixedObject(8, 8 * (ArgNo - 6), true, false);
427 // Create the SelectionDAG nodes corresponding to a load
428 //from this parameter
429 SDValue FIN = DAG.getFrameIndex(FI, MVT::i64);
430 ArgVal = DAG.getLoad(ObjectVT, dl, Chain, FIN, NULL, 0,
433 InVals.push_back(ArgVal);
436 // If the functions takes variable number of arguments, copy all regs to stack
438 VarArgsOffset = Ins.size() * 8;
439 std::vector<SDValue> LS;
440 for (int i = 0; i < 6; ++i) {
441 if (TargetRegisterInfo::isPhysicalRegister(args_int[i]))
442 args_int[i] = AddLiveIn(MF, args_int[i], &Alpha::GPRCRegClass);
443 SDValue argt = DAG.getCopyFromReg(Chain, dl, args_int[i], MVT::i64);
444 int FI = MFI->CreateFixedObject(8, -8 * (6 - i), true, false);
445 if (i == 0) VarArgsBase = FI;
446 SDValue SDFI = DAG.getFrameIndex(FI, MVT::i64);
447 LS.push_back(DAG.getStore(Chain, dl, argt, SDFI, NULL, 0,
450 if (TargetRegisterInfo::isPhysicalRegister(args_float[i]))
451 args_float[i] = AddLiveIn(MF, args_float[i], &Alpha::F8RCRegClass);
452 argt = DAG.getCopyFromReg(Chain, dl, args_float[i], MVT::f64);
453 FI = MFI->CreateFixedObject(8, - 8 * (12 - i), true, false);
454 SDFI = DAG.getFrameIndex(FI, MVT::i64);
455 LS.push_back(DAG.getStore(Chain, dl, argt, SDFI, NULL, 0,
459 //Set up a token factor with all the stack traffic
460 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, &LS[0], LS.size());
467 AlphaTargetLowering::LowerReturn(SDValue Chain,
468 CallingConv::ID CallConv, bool isVarArg,
469 const SmallVectorImpl<ISD::OutputArg> &Outs,
470 DebugLoc dl, SelectionDAG &DAG) {
472 SDValue Copy = DAG.getCopyToReg(Chain, dl, Alpha::R26,
473 DAG.getNode(AlphaISD::GlobalRetAddr,
474 DebugLoc(), MVT::i64),
476 switch (Outs.size()) {
478 llvm_unreachable("Do not know how to return this many arguments!");
481 //return SDValue(); // ret void is legal
483 EVT ArgVT = Outs[0].Val.getValueType();
485 if (ArgVT.isInteger())
488 assert(ArgVT.isFloatingPoint());
491 Copy = DAG.getCopyToReg(Copy, dl, ArgReg,
492 Outs[0].Val, Copy.getValue(1));
493 if (DAG.getMachineFunction().getRegInfo().liveout_empty())
494 DAG.getMachineFunction().getRegInfo().addLiveOut(ArgReg);
498 EVT ArgVT = Outs[0].Val.getValueType();
499 unsigned ArgReg1, ArgReg2;
500 if (ArgVT.isInteger()) {
504 assert(ArgVT.isFloatingPoint());
508 Copy = DAG.getCopyToReg(Copy, dl, ArgReg1,
509 Outs[0].Val, Copy.getValue(1));
510 if (std::find(DAG.getMachineFunction().getRegInfo().liveout_begin(),
511 DAG.getMachineFunction().getRegInfo().liveout_end(), ArgReg1)
512 == DAG.getMachineFunction().getRegInfo().liveout_end())
513 DAG.getMachineFunction().getRegInfo().addLiveOut(ArgReg1);
514 Copy = DAG.getCopyToReg(Copy, dl, ArgReg2,
515 Outs[1].Val, Copy.getValue(1));
516 if (std::find(DAG.getMachineFunction().getRegInfo().liveout_begin(),
517 DAG.getMachineFunction().getRegInfo().liveout_end(), ArgReg2)
518 == DAG.getMachineFunction().getRegInfo().liveout_end())
519 DAG.getMachineFunction().getRegInfo().addLiveOut(ArgReg2);
523 return DAG.getNode(AlphaISD::RET_FLAG, dl,
524 MVT::Other, Copy, Copy.getValue(1));
527 void AlphaTargetLowering::LowerVAARG(SDNode *N, SDValue &Chain,
528 SDValue &DataPtr, SelectionDAG &DAG) {
529 Chain = N->getOperand(0);
530 SDValue VAListP = N->getOperand(1);
531 const Value *VAListS = cast<SrcValueSDNode>(N->getOperand(2))->getValue();
532 DebugLoc dl = N->getDebugLoc();
534 SDValue Base = DAG.getLoad(MVT::i64, dl, Chain, VAListP, VAListS, 0,
536 SDValue Tmp = DAG.getNode(ISD::ADD, dl, MVT::i64, VAListP,
537 DAG.getConstant(8, MVT::i64));
538 SDValue Offset = DAG.getExtLoad(ISD::SEXTLOAD, dl, MVT::i64, Base.getValue(1),
539 Tmp, NULL, 0, MVT::i32, false, false, 0);
540 DataPtr = DAG.getNode(ISD::ADD, dl, MVT::i64, Base, Offset);
541 if (N->getValueType(0).isFloatingPoint())
543 //if fp && Offset < 6*8, then subtract 6*8 from DataPtr
544 SDValue FPDataPtr = DAG.getNode(ISD::SUB, dl, MVT::i64, DataPtr,
545 DAG.getConstant(8*6, MVT::i64));
546 SDValue CC = DAG.getSetCC(dl, MVT::i64, Offset,
547 DAG.getConstant(8*6, MVT::i64), ISD::SETLT);
548 DataPtr = DAG.getNode(ISD::SELECT, dl, MVT::i64, CC, FPDataPtr, DataPtr);
551 SDValue NewOffset = DAG.getNode(ISD::ADD, dl, MVT::i64, Offset,
552 DAG.getConstant(8, MVT::i64));
553 Chain = DAG.getTruncStore(Offset.getValue(1), dl, NewOffset, Tmp, NULL, 0,
554 MVT::i32, false, false, 0);
557 /// LowerOperation - Provide custom lowering hooks for some operations.
559 SDValue AlphaTargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) {
560 DebugLoc dl = Op.getDebugLoc();
561 switch (Op.getOpcode()) {
562 default: llvm_unreachable("Wasn't expecting to be able to lower this!");
563 case ISD::JumpTable: return LowerJumpTable(Op, DAG);
565 case ISD::INTRINSIC_WO_CHAIN: {
566 unsigned IntNo = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
568 default: break; // Don't custom lower most intrinsics.
569 case Intrinsic::alpha_umulh:
570 return DAG.getNode(ISD::MULHU, dl, MVT::i64,
571 Op.getOperand(1), Op.getOperand(2));
575 case ISD::SRL_PARTS: {
576 SDValue ShOpLo = Op.getOperand(0);
577 SDValue ShOpHi = Op.getOperand(1);
578 SDValue ShAmt = Op.getOperand(2);
579 SDValue bm = DAG.getNode(ISD::SUB, dl, MVT::i64,
580 DAG.getConstant(64, MVT::i64), ShAmt);
581 SDValue BMCC = DAG.getSetCC(dl, MVT::i64, bm,
582 DAG.getConstant(0, MVT::i64), ISD::SETLE);
583 // if 64 - shAmt <= 0
584 SDValue Hi_Neg = DAG.getConstant(0, MVT::i64);
585 SDValue ShAmt_Neg = DAG.getNode(ISD::SUB, dl, MVT::i64,
586 DAG.getConstant(0, MVT::i64), bm);
587 SDValue Lo_Neg = DAG.getNode(ISD::SRL, dl, MVT::i64, ShOpHi, ShAmt_Neg);
589 SDValue carries = DAG.getNode(ISD::SHL, dl, MVT::i64, ShOpHi, bm);
590 SDValue Hi_Pos = DAG.getNode(ISD::SRL, dl, MVT::i64, ShOpHi, ShAmt);
591 SDValue Lo_Pos = DAG.getNode(ISD::SRL, dl, MVT::i64, ShOpLo, ShAmt);
592 Lo_Pos = DAG.getNode(ISD::OR, dl, MVT::i64, Lo_Pos, carries);
594 SDValue Hi = DAG.getNode(ISD::SELECT, dl, MVT::i64, BMCC, Hi_Neg, Hi_Pos);
595 SDValue Lo = DAG.getNode(ISD::SELECT, dl, MVT::i64, BMCC, Lo_Neg, Lo_Pos);
596 SDValue Ops[2] = { Lo, Hi };
597 return DAG.getMergeValues(Ops, 2, dl);
599 // case ISD::SRA_PARTS:
601 // case ISD::SHL_PARTS:
604 case ISD::SINT_TO_FP: {
605 assert(Op.getOperand(0).getValueType() == MVT::i64 &&
606 "Unhandled SINT_TO_FP type in custom expander!");
608 bool isDouble = Op.getValueType() == MVT::f64;
609 LD = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::f64, Op.getOperand(0));
610 SDValue FP = DAG.getNode(isDouble?AlphaISD::CVTQT_:AlphaISD::CVTQS_, dl,
611 isDouble?MVT::f64:MVT::f32, LD);
614 case ISD::FP_TO_SINT: {
615 bool isDouble = Op.getOperand(0).getValueType() == MVT::f64;
616 SDValue src = Op.getOperand(0);
618 if (!isDouble) //Promote
619 src = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, src);
621 src = DAG.getNode(AlphaISD::CVTTQ_, dl, MVT::f64, src);
623 return DAG.getNode(ISD::BIT_CONVERT, dl, MVT::i64, src);
625 case ISD::ConstantPool: {
626 ConstantPoolSDNode *CP = cast<ConstantPoolSDNode>(Op);
627 Constant *C = CP->getConstVal();
628 SDValue CPI = DAG.getTargetConstantPool(C, MVT::i64, CP->getAlignment());
629 // FIXME there isn't really any debug info here
631 SDValue Hi = DAG.getNode(AlphaISD::GPRelHi, dl, MVT::i64, CPI,
632 DAG.getGLOBAL_OFFSET_TABLE(MVT::i64));
633 SDValue Lo = DAG.getNode(AlphaISD::GPRelLo, dl, MVT::i64, CPI, Hi);
636 case ISD::GlobalTLSAddress:
637 llvm_unreachable("TLS not implemented for Alpha.");
638 case ISD::GlobalAddress: {
639 GlobalAddressSDNode *GSDN = cast<GlobalAddressSDNode>(Op);
640 GlobalValue *GV = GSDN->getGlobal();
641 SDValue GA = DAG.getTargetGlobalAddress(GV, MVT::i64, GSDN->getOffset());
642 // FIXME there isn't really any debug info here
644 // if (!GV->hasWeakLinkage() && !GV->isDeclaration() && !GV->hasLinkOnceLinkage()) {
645 if (GV->hasLocalLinkage()) {
646 SDValue Hi = DAG.getNode(AlphaISD::GPRelHi, dl, MVT::i64, GA,
647 DAG.getGLOBAL_OFFSET_TABLE(MVT::i64));
648 SDValue Lo = DAG.getNode(AlphaISD::GPRelLo, dl, MVT::i64, GA, Hi);
651 return DAG.getNode(AlphaISD::RelLit, dl, MVT::i64, GA,
652 DAG.getGLOBAL_OFFSET_TABLE(MVT::i64));
654 case ISD::ExternalSymbol: {
655 return DAG.getNode(AlphaISD::RelLit, dl, MVT::i64,
656 DAG.getTargetExternalSymbol(cast<ExternalSymbolSDNode>(Op)
657 ->getSymbol(), MVT::i64),
658 DAG.getGLOBAL_OFFSET_TABLE(MVT::i64));
663 //Expand only on constant case
664 if (Op.getOperand(1).getOpcode() == ISD::Constant) {
665 EVT VT = Op.getNode()->getValueType(0);
666 SDValue Tmp1 = Op.getNode()->getOpcode() == ISD::UREM ?
667 BuildUDIV(Op.getNode(), DAG, NULL) :
668 BuildSDIV(Op.getNode(), DAG, NULL);
669 Tmp1 = DAG.getNode(ISD::MUL, dl, VT, Tmp1, Op.getOperand(1));
670 Tmp1 = DAG.getNode(ISD::SUB, dl, VT, Op.getOperand(0), Tmp1);
676 if (Op.getValueType().isInteger()) {
677 if (Op.getOperand(1).getOpcode() == ISD::Constant)
678 return Op.getOpcode() == ISD::SDIV ? BuildSDIV(Op.getNode(), DAG, NULL)
679 : BuildUDIV(Op.getNode(), DAG, NULL);
680 const char* opstr = 0;
681 switch (Op.getOpcode()) {
682 case ISD::UREM: opstr = "__remqu"; break;
683 case ISD::SREM: opstr = "__remq"; break;
684 case ISD::UDIV: opstr = "__divqu"; break;
685 case ISD::SDIV: opstr = "__divq"; break;
687 SDValue Tmp1 = Op.getOperand(0),
688 Tmp2 = Op.getOperand(1),
689 Addr = DAG.getExternalSymbol(opstr, MVT::i64);
690 return DAG.getNode(AlphaISD::DivCall, dl, MVT::i64, Addr, Tmp1, Tmp2);
695 SDValue Chain, DataPtr;
696 LowerVAARG(Op.getNode(), Chain, DataPtr, DAG);
699 if (Op.getValueType() == MVT::i32)
700 Result = DAG.getExtLoad(ISD::SEXTLOAD, dl, MVT::i64, Chain, DataPtr,
701 NULL, 0, MVT::i32, false, false, 0);
703 Result = DAG.getLoad(Op.getValueType(), dl, Chain, DataPtr, NULL, 0,
708 SDValue Chain = Op.getOperand(0);
709 SDValue DestP = Op.getOperand(1);
710 SDValue SrcP = Op.getOperand(2);
711 const Value *DestS = cast<SrcValueSDNode>(Op.getOperand(3))->getValue();
712 const Value *SrcS = cast<SrcValueSDNode>(Op.getOperand(4))->getValue();
714 SDValue Val = DAG.getLoad(getPointerTy(), dl, Chain, SrcP, SrcS, 0,
716 SDValue Result = DAG.getStore(Val.getValue(1), dl, Val, DestP, DestS, 0,
718 SDValue NP = DAG.getNode(ISD::ADD, dl, MVT::i64, SrcP,
719 DAG.getConstant(8, MVT::i64));
720 Val = DAG.getExtLoad(ISD::SEXTLOAD, dl, MVT::i64, Result,
721 NP, NULL,0, MVT::i32, false, false, 0);
722 SDValue NPD = DAG.getNode(ISD::ADD, dl, MVT::i64, DestP,
723 DAG.getConstant(8, MVT::i64));
724 return DAG.getTruncStore(Val.getValue(1), dl, Val, NPD, NULL, 0, MVT::i32,
728 SDValue Chain = Op.getOperand(0);
729 SDValue VAListP = Op.getOperand(1);
730 const Value *VAListS = cast<SrcValueSDNode>(Op.getOperand(2))->getValue();
732 // vastart stores the address of the VarArgsBase and VarArgsOffset
733 SDValue FR = DAG.getFrameIndex(VarArgsBase, MVT::i64);
734 SDValue S1 = DAG.getStore(Chain, dl, FR, VAListP, VAListS, 0,
736 SDValue SA2 = DAG.getNode(ISD::ADD, dl, MVT::i64, VAListP,
737 DAG.getConstant(8, MVT::i64));
738 return DAG.getTruncStore(S1, dl, DAG.getConstant(VarArgsOffset, MVT::i64),
739 SA2, NULL, 0, MVT::i32, false, false, 0);
741 case ISD::RETURNADDR:
742 return DAG.getNode(AlphaISD::GlobalRetAddr, DebugLoc(), MVT::i64);
744 case ISD::FRAMEADDR: break;
750 void AlphaTargetLowering::ReplaceNodeResults(SDNode *N,
751 SmallVectorImpl<SDValue>&Results,
753 DebugLoc dl = N->getDebugLoc();
754 assert(N->getValueType(0) == MVT::i32 &&
755 N->getOpcode() == ISD::VAARG &&
756 "Unknown node to custom promote!");
758 SDValue Chain, DataPtr;
759 LowerVAARG(N, Chain, DataPtr, DAG);
760 SDValue Res = DAG.getLoad(N->getValueType(0), dl, Chain, DataPtr, NULL, 0,
762 Results.push_back(Res);
763 Results.push_back(SDValue(Res.getNode(), 1));
769 /// getConstraintType - Given a constraint letter, return the type of
770 /// constraint it is for this target.
771 AlphaTargetLowering::ConstraintType
772 AlphaTargetLowering::getConstraintType(const std::string &Constraint) const {
773 if (Constraint.size() == 1) {
774 switch (Constraint[0]) {
778 return C_RegisterClass;
781 return TargetLowering::getConstraintType(Constraint);
784 std::vector<unsigned> AlphaTargetLowering::
785 getRegClassForInlineAsmConstraint(const std::string &Constraint,
787 if (Constraint.size() == 1) {
788 switch (Constraint[0]) {
789 default: break; // Unknown constriant letter
791 return make_vector<unsigned>(Alpha::F0 , Alpha::F1 , Alpha::F2 ,
792 Alpha::F3 , Alpha::F4 , Alpha::F5 ,
793 Alpha::F6 , Alpha::F7 , Alpha::F8 ,
794 Alpha::F9 , Alpha::F10, Alpha::F11,
795 Alpha::F12, Alpha::F13, Alpha::F14,
796 Alpha::F15, Alpha::F16, Alpha::F17,
797 Alpha::F18, Alpha::F19, Alpha::F20,
798 Alpha::F21, Alpha::F22, Alpha::F23,
799 Alpha::F24, Alpha::F25, Alpha::F26,
800 Alpha::F27, Alpha::F28, Alpha::F29,
801 Alpha::F30, Alpha::F31, 0);
803 return make_vector<unsigned>(Alpha::R0 , Alpha::R1 , Alpha::R2 ,
804 Alpha::R3 , Alpha::R4 , Alpha::R5 ,
805 Alpha::R6 , Alpha::R7 , Alpha::R8 ,
806 Alpha::R9 , Alpha::R10, Alpha::R11,
807 Alpha::R12, Alpha::R13, Alpha::R14,
808 Alpha::R15, Alpha::R16, Alpha::R17,
809 Alpha::R18, Alpha::R19, Alpha::R20,
810 Alpha::R21, Alpha::R22, Alpha::R23,
811 Alpha::R24, Alpha::R25, Alpha::R26,
812 Alpha::R27, Alpha::R28, Alpha::R29,
813 Alpha::R30, Alpha::R31, 0);
817 return std::vector<unsigned>();
819 //===----------------------------------------------------------------------===//
820 // Other Lowering Code
821 //===----------------------------------------------------------------------===//
824 AlphaTargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI,
825 MachineBasicBlock *BB,
826 DenseMap<MachineBasicBlock*, MachineBasicBlock*> *EM) const {
827 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
828 assert((MI->getOpcode() == Alpha::CAS32 ||
829 MI->getOpcode() == Alpha::CAS64 ||
830 MI->getOpcode() == Alpha::LAS32 ||
831 MI->getOpcode() == Alpha::LAS64 ||
832 MI->getOpcode() == Alpha::SWAP32 ||
833 MI->getOpcode() == Alpha::SWAP64) &&
834 "Unexpected instr type to insert");
836 bool is32 = MI->getOpcode() == Alpha::CAS32 ||
837 MI->getOpcode() == Alpha::LAS32 ||
838 MI->getOpcode() == Alpha::SWAP32;
840 //Load locked store conditional for atomic ops take on the same form
843 //do stuff (maybe branch to exit)
845 //test sc and maybe branck to start
847 const BasicBlock *LLVM_BB = BB->getBasicBlock();
848 DebugLoc dl = MI->getDebugLoc();
849 MachineFunction::iterator It = BB;
852 MachineBasicBlock *thisMBB = BB;
853 MachineFunction *F = BB->getParent();
854 MachineBasicBlock *llscMBB = F->CreateMachineBasicBlock(LLVM_BB);
855 MachineBasicBlock *sinkMBB = F->CreateMachineBasicBlock(LLVM_BB);
857 // Inform sdisel of the edge changes.
858 for (MachineBasicBlock::succ_iterator I = BB->succ_begin(),
859 E = BB->succ_end(); I != E; ++I)
860 EM->insert(std::make_pair(*I, sinkMBB));
862 sinkMBB->transferSuccessors(thisMBB);
864 F->insert(It, llscMBB);
865 F->insert(It, sinkMBB);
867 BuildMI(thisMBB, dl, TII->get(Alpha::BR)).addMBB(llscMBB);
869 unsigned reg_res = MI->getOperand(0).getReg(),
870 reg_ptr = MI->getOperand(1).getReg(),
871 reg_v2 = MI->getOperand(2).getReg(),
872 reg_store = F->getRegInfo().createVirtualRegister(&Alpha::GPRCRegClass);
874 BuildMI(llscMBB, dl, TII->get(is32 ? Alpha::LDL_L : Alpha::LDQ_L),
875 reg_res).addImm(0).addReg(reg_ptr);
876 switch (MI->getOpcode()) {
880 = F->getRegInfo().createVirtualRegister(&Alpha::GPRCRegClass);
881 BuildMI(llscMBB, dl, TII->get(Alpha::CMPEQ), reg_cmp)
882 .addReg(reg_v2).addReg(reg_res);
883 BuildMI(llscMBB, dl, TII->get(Alpha::BEQ))
884 .addImm(0).addReg(reg_cmp).addMBB(sinkMBB);
885 BuildMI(llscMBB, dl, TII->get(Alpha::BISr), reg_store)
886 .addReg(Alpha::R31).addReg(MI->getOperand(3).getReg());
891 BuildMI(llscMBB, dl,TII->get(is32 ? Alpha::ADDLr : Alpha::ADDQr), reg_store)
892 .addReg(reg_res).addReg(reg_v2);
896 case Alpha::SWAP64: {
897 BuildMI(llscMBB, dl, TII->get(Alpha::BISr), reg_store)
898 .addReg(reg_v2).addReg(reg_v2);
902 BuildMI(llscMBB, dl, TII->get(is32 ? Alpha::STL_C : Alpha::STQ_C), reg_store)
903 .addReg(reg_store).addImm(0).addReg(reg_ptr);
904 BuildMI(llscMBB, dl, TII->get(Alpha::BEQ))
905 .addImm(0).addReg(reg_store).addMBB(llscMBB);
906 BuildMI(llscMBB, dl, TII->get(Alpha::BR)).addMBB(sinkMBB);
908 thisMBB->addSuccessor(llscMBB);
909 llscMBB->addSuccessor(llscMBB);
910 llscMBB->addSuccessor(sinkMBB);
911 F->DeleteMachineInstr(MI); // The pseudo instruction is gone now.
917 AlphaTargetLowering::isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const {
918 // The Alpha target isn't yet aware of offsets.
922 bool AlphaTargetLowering::isFPImmLegal(const APFloat &Imm, EVT VT) const {
923 if (VT != MVT::f32 && VT != MVT::f64)
929 return Imm.isZero() || Imm.isNegZero();