1 //===-- AlphaISelLowering.cpp - Alpha DAG Lowering Implementation ---------===//
3 // The LLVM Compiler Infrastructure
5 // This file was developed by Andrew Lenharth and is distributed under
6 // the University of Illinois Open Source License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file implements the AlphaISelLowering class.
12 //===----------------------------------------------------------------------===//
14 #include "AlphaISelLowering.h"
15 #include "AlphaTargetMachine.h"
16 #include "llvm/CodeGen/MachineFrameInfo.h"
17 #include "llvm/CodeGen/MachineFunction.h"
18 #include "llvm/CodeGen/MachineInstrBuilder.h"
19 #include "llvm/CodeGen/SelectionDAG.h"
20 #include "llvm/CodeGen/SSARegMap.h"
21 #include "llvm/Constants.h"
22 #include "llvm/Function.h"
23 #include "llvm/Module.h"
24 #include "llvm/Support/CommandLine.h"
27 /// AddLiveIn - This helper function adds the specified physical register to the
28 /// MachineFunction as a live in value. It also creates a corresponding virtual
30 static unsigned AddLiveIn(MachineFunction &MF, unsigned PReg,
31 TargetRegisterClass *RC) {
32 assert(RC->contains(PReg) && "Not the correct regclass!");
33 unsigned VReg = MF.getSSARegMap()->createVirtualRegister(RC);
34 MF.addLiveIn(PReg, VReg);
38 AlphaTargetLowering::AlphaTargetLowering(TargetMachine &TM) : TargetLowering(TM) {
39 // Set up the TargetLowering object.
40 //I am having problems with shr n ubyte 1
41 setShiftAmountType(MVT::i64);
42 setSetCCResultType(MVT::i64);
43 setSetCCResultContents(ZeroOrOneSetCCResult);
45 setUsesGlobalOffsetTable(true);
47 addRegisterClass(MVT::i64, Alpha::GPRCRegisterClass);
48 addRegisterClass(MVT::f64, Alpha::F8RCRegisterClass);
49 addRegisterClass(MVT::f32, Alpha::F4RCRegisterClass);
51 setLoadXAction(ISD::EXTLOAD, MVT::i1, Promote);
52 setLoadXAction(ISD::EXTLOAD, MVT::f32, Expand);
54 setLoadXAction(ISD::ZEXTLOAD, MVT::i1, Promote);
55 setLoadXAction(ISD::ZEXTLOAD, MVT::i32, Expand);
57 setLoadXAction(ISD::SEXTLOAD, MVT::i1, Promote);
58 setLoadXAction(ISD::SEXTLOAD, MVT::i8, Expand);
59 setLoadXAction(ISD::SEXTLOAD, MVT::i16, Expand);
61 setStoreXAction(MVT::i1, Promote);
63 // setOperationAction(ISD::BRIND, MVT::Other, Expand);
64 setOperationAction(ISD::BR_JT, MVT::Other, Expand);
65 setOperationAction(ISD::BR_CC, MVT::Other, Expand);
66 setOperationAction(ISD::SELECT_CC, MVT::Other, Expand);
68 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1, Expand);
70 setOperationAction(ISD::FREM, MVT::f32, Expand);
71 setOperationAction(ISD::FREM, MVT::f64, Expand);
73 setOperationAction(ISD::UINT_TO_FP, MVT::i64, Expand);
74 setOperationAction(ISD::SINT_TO_FP, MVT::i64, Custom);
75 setOperationAction(ISD::FP_TO_UINT, MVT::i64, Expand);
76 setOperationAction(ISD::FP_TO_SINT, MVT::i64, Custom);
78 if (!TM.getSubtarget<AlphaSubtarget>().hasCT()) {
79 setOperationAction(ISD::CTPOP , MVT::i64 , Expand);
80 setOperationAction(ISD::CTTZ , MVT::i64 , Expand);
81 setOperationAction(ISD::CTLZ , MVT::i64 , Expand);
83 setOperationAction(ISD::BSWAP , MVT::i64, Expand);
84 setOperationAction(ISD::ROTL , MVT::i64, Expand);
85 setOperationAction(ISD::ROTR , MVT::i64, Expand);
87 setOperationAction(ISD::SREM , MVT::i64, Custom);
88 setOperationAction(ISD::UREM , MVT::i64, Custom);
89 setOperationAction(ISD::SDIV , MVT::i64, Custom);
90 setOperationAction(ISD::UDIV , MVT::i64, Custom);
92 setOperationAction(ISD::MEMMOVE , MVT::Other, Expand);
93 setOperationAction(ISD::MEMSET , MVT::Other, Expand);
94 setOperationAction(ISD::MEMCPY , MVT::Other, Expand);
96 // We don't support sin/cos/sqrt
97 setOperationAction(ISD::FSIN , MVT::f64, Expand);
98 setOperationAction(ISD::FCOS , MVT::f64, Expand);
99 setOperationAction(ISD::FSIN , MVT::f32, Expand);
100 setOperationAction(ISD::FCOS , MVT::f32, Expand);
102 setOperationAction(ISD::FSQRT, MVT::f64, Expand);
103 setOperationAction(ISD::FSQRT, MVT::f32, Expand);
105 setOperationAction(ISD::SETCC, MVT::f32, Promote);
107 setOperationAction(ISD::BIT_CONVERT, MVT::f32, Promote);
109 // We don't have line number support yet.
110 setOperationAction(ISD::LOCATION, MVT::Other, Expand);
111 setOperationAction(ISD::DEBUG_LOC, MVT::Other, Expand);
112 setOperationAction(ISD::LABEL, MVT::Other, Expand);
114 // Not implemented yet.
115 setOperationAction(ISD::STACKSAVE, MVT::Other, Expand);
116 setOperationAction(ISD::STACKRESTORE, MVT::Other, Expand);
117 setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i64, Expand);
119 // We want to legalize GlobalAddress and ConstantPool and
120 // ExternalSymbols nodes into the appropriate instructions to
121 // materialize the address.
122 setOperationAction(ISD::GlobalAddress, MVT::i64, Custom);
123 setOperationAction(ISD::ConstantPool, MVT::i64, Custom);
124 setOperationAction(ISD::ExternalSymbol, MVT::i64, Custom);
125 setOperationAction(ISD::GlobalTLSAddress, MVT::i64, Custom);
127 setOperationAction(ISD::VASTART, MVT::Other, Custom);
128 setOperationAction(ISD::VAEND, MVT::Other, Expand);
129 setOperationAction(ISD::VACOPY, MVT::Other, Custom);
130 setOperationAction(ISD::VAARG, MVT::Other, Custom);
131 setOperationAction(ISD::VAARG, MVT::i32, Custom);
133 setOperationAction(ISD::RET, MVT::Other, Custom);
135 setOperationAction(ISD::JumpTable, MVT::i64, Custom);
136 setOperationAction(ISD::JumpTable, MVT::i32, Custom);
138 setStackPointerRegisterToSaveRestore(Alpha::R30);
140 setOperationAction(ISD::ConstantFP, MVT::f64, Expand);
141 setOperationAction(ISD::ConstantFP, MVT::f32, Expand);
142 addLegalFPImmediate(+0.0); //F31
143 addLegalFPImmediate(-0.0); //-F31
146 setJumpBufAlignment(16);
148 computeRegisterProperties();
151 const char *AlphaTargetLowering::getTargetNodeName(unsigned Opcode) const {
154 case AlphaISD::CVTQT_: return "Alpha::CVTQT_";
155 case AlphaISD::CVTQS_: return "Alpha::CVTQS_";
156 case AlphaISD::CVTTQ_: return "Alpha::CVTTQ_";
157 case AlphaISD::GPRelHi: return "Alpha::GPRelHi";
158 case AlphaISD::GPRelLo: return "Alpha::GPRelLo";
159 case AlphaISD::RelLit: return "Alpha::RelLit";
160 case AlphaISD::GlobalRetAddr: return "Alpha::GlobalRetAddr";
161 case AlphaISD::CALL: return "Alpha::CALL";
162 case AlphaISD::DivCall: return "Alpha::DivCall";
163 case AlphaISD::RET_FLAG: return "Alpha::RET_FLAG";
164 case AlphaISD::COND_BRANCH_I: return "Alpha::COND_BRANCH_I";
165 case AlphaISD::COND_BRANCH_F: return "Alpha::COND_BRANCH_F";
169 static SDOperand LowerJumpTable(SDOperand Op, SelectionDAG &DAG) {
170 MVT::ValueType PtrVT = Op.getValueType();
171 JumpTableSDNode *JT = cast<JumpTableSDNode>(Op);
172 SDOperand JTI = DAG.getTargetJumpTable(JT->getIndex(), PtrVT);
173 SDOperand Zero = DAG.getConstant(0, PtrVT);
175 SDOperand Hi = DAG.getNode(AlphaISD::GPRelHi, MVT::i64, JTI,
176 DAG.getNode(ISD::GLOBAL_OFFSET_TABLE, MVT::i64));
177 SDOperand Lo = DAG.getNode(AlphaISD::GPRelLo, MVT::i64, JTI, Hi);
181 //http://www.cs.arizona.edu/computer.help/policy/DIGITAL_unix/
182 //AA-PY8AC-TET1_html/callCH3.html#BLOCK21
184 //For now, just use variable size stack frame format
186 //In a standard call, the first six items are passed in registers $16
187 //- $21 and/or registers $f16 - $f21. (See Section 4.1.2 for details
188 //of argument-to-register correspondence.) The remaining items are
189 //collected in a memory argument list that is a naturally aligned
190 //array of quadwords. In a standard call, this list, if present, must
191 //be passed at 0(SP).
192 //7 ... n 0(SP) ... (n-7)*8(SP)
200 static SDOperand LowerFORMAL_ARGUMENTS(SDOperand Op, SelectionDAG &DAG,
202 int &VarArgsOffset) {
203 MachineFunction &MF = DAG.getMachineFunction();
204 MachineFrameInfo *MFI = MF.getFrameInfo();
205 std::vector<SDOperand> ArgValues;
206 SDOperand Root = Op.getOperand(0);
208 AddLiveIn(MF, Alpha::R29, &Alpha::GPRCRegClass); //GP
209 AddLiveIn(MF, Alpha::R26, &Alpha::GPRCRegClass); //RA
211 unsigned args_int[] = {
212 Alpha::R16, Alpha::R17, Alpha::R18, Alpha::R19, Alpha::R20, Alpha::R21};
213 unsigned args_float[] = {
214 Alpha::F16, Alpha::F17, Alpha::F18, Alpha::F19, Alpha::F20, Alpha::F21};
216 for (unsigned ArgNo = 0, e = Op.Val->getNumValues()-1; ArgNo != e; ++ArgNo) {
218 MVT::ValueType ObjectVT = Op.getValue(ArgNo).getValueType();
224 cerr << "Unknown Type " << ObjectVT << "\n";
227 args_float[ArgNo] = AddLiveIn(MF, args_float[ArgNo],
228 &Alpha::F8RCRegClass);
229 ArgVal = DAG.getCopyFromReg(Root, args_float[ArgNo], ObjectVT);
232 args_float[ArgNo] = AddLiveIn(MF, args_float[ArgNo],
233 &Alpha::F4RCRegClass);
234 ArgVal = DAG.getCopyFromReg(Root, args_float[ArgNo], ObjectVT);
237 args_int[ArgNo] = AddLiveIn(MF, args_int[ArgNo],
238 &Alpha::GPRCRegClass);
239 ArgVal = DAG.getCopyFromReg(Root, args_int[ArgNo], MVT::i64);
243 // Create the frame index object for this incoming parameter...
244 int FI = MFI->CreateFixedObject(8, 8 * (ArgNo - 6));
246 // Create the SelectionDAG nodes corresponding to a load
247 //from this parameter
248 SDOperand FIN = DAG.getFrameIndex(FI, MVT::i64);
249 ArgVal = DAG.getLoad(ObjectVT, Root, FIN, NULL, 0);
251 ArgValues.push_back(ArgVal);
254 // If the functions takes variable number of arguments, copy all regs to stack
255 bool isVarArg = cast<ConstantSDNode>(Op.getOperand(2))->getValue() != 0;
257 VarArgsOffset = (Op.Val->getNumValues()-1) * 8;
258 std::vector<SDOperand> LS;
259 for (int i = 0; i < 6; ++i) {
260 if (MRegisterInfo::isPhysicalRegister(args_int[i]))
261 args_int[i] = AddLiveIn(MF, args_int[i], &Alpha::GPRCRegClass);
262 SDOperand argt = DAG.getCopyFromReg(Root, args_int[i], MVT::i64);
263 int FI = MFI->CreateFixedObject(8, -8 * (6 - i));
264 if (i == 0) VarArgsBase = FI;
265 SDOperand SDFI = DAG.getFrameIndex(FI, MVT::i64);
266 LS.push_back(DAG.getStore(Root, argt, SDFI, NULL, 0));
268 if (MRegisterInfo::isPhysicalRegister(args_float[i]))
269 args_float[i] = AddLiveIn(MF, args_float[i], &Alpha::F8RCRegClass);
270 argt = DAG.getCopyFromReg(Root, args_float[i], MVT::f64);
271 FI = MFI->CreateFixedObject(8, - 8 * (12 - i));
272 SDFI = DAG.getFrameIndex(FI, MVT::i64);
273 LS.push_back(DAG.getStore(Root, argt, SDFI, NULL, 0));
276 //Set up a token factor with all the stack traffic
277 Root = DAG.getNode(ISD::TokenFactor, MVT::Other, &LS[0], LS.size());
280 ArgValues.push_back(Root);
282 // Return the new list of results.
283 std::vector<MVT::ValueType> RetVT(Op.Val->value_begin(),
284 Op.Val->value_end());
285 return DAG.getNode(ISD::MERGE_VALUES, RetVT, &ArgValues[0], ArgValues.size());
288 static SDOperand LowerRET(SDOperand Op, SelectionDAG &DAG) {
289 SDOperand Copy = DAG.getCopyToReg(Op.getOperand(0), Alpha::R26,
290 DAG.getNode(AlphaISD::GlobalRetAddr,
293 switch (Op.getNumOperands()) {
295 assert(0 && "Do not know how to return this many arguments!");
299 //return SDOperand(); // ret void is legal
301 MVT::ValueType ArgVT = Op.getOperand(1).getValueType();
303 if (MVT::isInteger(ArgVT))
306 assert(MVT::isFloatingPoint(ArgVT));
309 Copy = DAG.getCopyToReg(Copy, ArgReg, Op.getOperand(1), Copy.getValue(1));
310 if (DAG.getMachineFunction().liveout_empty())
311 DAG.getMachineFunction().addLiveOut(ArgReg);
315 return DAG.getNode(AlphaISD::RET_FLAG, MVT::Other, Copy, Copy.getValue(1));
318 std::pair<SDOperand, SDOperand>
319 AlphaTargetLowering::LowerCallTo(SDOperand Chain, const Type *RetTy,
320 bool RetTyIsSigned, bool isVarArg,
321 unsigned CallingConv, bool isTailCall,
322 SDOperand Callee, ArgListTy &Args,
326 NumBytes = (Args.size() - 6) * 8;
328 Chain = DAG.getCALLSEQ_START(Chain,
329 DAG.getConstant(NumBytes, getPointerTy()));
330 std::vector<SDOperand> args_to_use;
331 for (unsigned i = 0, e = Args.size(); i != e; ++i)
333 switch (getValueType(Args[i].Ty)) {
334 default: assert(0 && "Unexpected ValueType for argument!");
339 // Promote the integer to 64 bits. If the input type is signed use a
340 // sign extend, otherwise use a zero extend.
342 Args[i].Node = DAG.getNode(ISD::SIGN_EXTEND, MVT::i64, Args[i].Node);
343 else if (Args[i].isZExt)
344 Args[i].Node = DAG.getNode(ISD::ZERO_EXTEND, MVT::i64, Args[i].Node);
346 Args[i].Node = DAG.getNode(ISD::ANY_EXTEND, MVT::i64, Args[i].Node);
353 args_to_use.push_back(Args[i].Node);
356 std::vector<MVT::ValueType> RetVals;
357 MVT::ValueType RetTyVT = getValueType(RetTy);
358 MVT::ValueType ActualRetTyVT = RetTyVT;
359 if (RetTyVT >= MVT::i1 && RetTyVT <= MVT::i32)
360 ActualRetTyVT = MVT::i64;
362 if (RetTyVT != MVT::isVoid)
363 RetVals.push_back(ActualRetTyVT);
364 RetVals.push_back(MVT::Other);
366 std::vector<SDOperand> Ops;
367 Ops.push_back(Chain);
368 Ops.push_back(Callee);
369 Ops.insert(Ops.end(), args_to_use.begin(), args_to_use.end());
370 SDOperand TheCall = DAG.getNode(AlphaISD::CALL, RetVals, &Ops[0], Ops.size());
371 Chain = TheCall.getValue(RetTyVT != MVT::isVoid);
372 Chain = DAG.getNode(ISD::CALLSEQ_END, MVT::Other, Chain,
373 DAG.getConstant(NumBytes, getPointerTy()));
374 SDOperand RetVal = TheCall;
376 if (RetTyVT != ActualRetTyVT) {
377 RetVal = DAG.getNode(RetTyIsSigned ? ISD::AssertSext : ISD::AssertZext,
378 MVT::i64, RetVal, DAG.getValueType(RetTyVT));
379 RetVal = DAG.getNode(ISD::TRUNCATE, RetTyVT, RetVal);
382 return std::make_pair(RetVal, Chain);
385 /// LowerOperation - Provide custom lowering hooks for some operations.
387 SDOperand AlphaTargetLowering::LowerOperation(SDOperand Op, SelectionDAG &DAG) {
388 switch (Op.getOpcode()) {
389 default: assert(0 && "Wasn't expecting to be able to lower this!");
390 case ISD::FORMAL_ARGUMENTS: return LowerFORMAL_ARGUMENTS(Op, DAG,
394 case ISD::RET: return LowerRET(Op,DAG);
395 case ISD::JumpTable: return LowerJumpTable(Op, DAG);
397 case ISD::SINT_TO_FP: {
398 assert(MVT::i64 == Op.getOperand(0).getValueType() &&
399 "Unhandled SINT_TO_FP type in custom expander!");
401 bool isDouble = MVT::f64 == Op.getValueType();
402 LD = DAG.getNode(ISD::BIT_CONVERT, MVT::f64, Op.getOperand(0));
403 SDOperand FP = DAG.getNode(isDouble?AlphaISD::CVTQT_:AlphaISD::CVTQS_,
404 isDouble?MVT::f64:MVT::f32, LD);
407 case ISD::FP_TO_SINT: {
408 bool isDouble = MVT::f64 == Op.getOperand(0).getValueType();
409 SDOperand src = Op.getOperand(0);
411 if (!isDouble) //Promote
412 src = DAG.getNode(ISD::FP_EXTEND, MVT::f64, src);
414 src = DAG.getNode(AlphaISD::CVTTQ_, MVT::f64, src);
416 return DAG.getNode(ISD::BIT_CONVERT, MVT::i64, src);
418 case ISD::ConstantPool: {
419 ConstantPoolSDNode *CP = cast<ConstantPoolSDNode>(Op);
420 Constant *C = CP->getConstVal();
421 SDOperand CPI = DAG.getTargetConstantPool(C, MVT::i64, CP->getAlignment());
423 SDOperand Hi = DAG.getNode(AlphaISD::GPRelHi, MVT::i64, CPI,
424 DAG.getNode(ISD::GLOBAL_OFFSET_TABLE, MVT::i64));
425 SDOperand Lo = DAG.getNode(AlphaISD::GPRelLo, MVT::i64, CPI, Hi);
428 case ISD::GlobalTLSAddress:
429 assert(0 && "TLS not implemented for Alpha.");
430 case ISD::GlobalAddress: {
431 GlobalAddressSDNode *GSDN = cast<GlobalAddressSDNode>(Op);
432 GlobalValue *GV = GSDN->getGlobal();
433 SDOperand GA = DAG.getTargetGlobalAddress(GV, MVT::i64, GSDN->getOffset());
435 // if (!GV->hasWeakLinkage() && !GV->isDeclaration() && !GV->hasLinkOnceLinkage()) {
436 if (GV->hasInternalLinkage()) {
437 SDOperand Hi = DAG.getNode(AlphaISD::GPRelHi, MVT::i64, GA,
438 DAG.getNode(ISD::GLOBAL_OFFSET_TABLE, MVT::i64));
439 SDOperand Lo = DAG.getNode(AlphaISD::GPRelLo, MVT::i64, GA, Hi);
442 return DAG.getNode(AlphaISD::RelLit, MVT::i64, GA,
443 DAG.getNode(ISD::GLOBAL_OFFSET_TABLE, MVT::i64));
445 case ISD::ExternalSymbol: {
446 return DAG.getNode(AlphaISD::RelLit, MVT::i64,
447 DAG.getTargetExternalSymbol(cast<ExternalSymbolSDNode>(Op)
448 ->getSymbol(), MVT::i64),
449 DAG.getNode(ISD::GLOBAL_OFFSET_TABLE, MVT::i64));
454 //Expand only on constant case
455 if (Op.getOperand(1).getOpcode() == ISD::Constant) {
456 MVT::ValueType VT = Op.Val->getValueType(0);
457 SDOperand Tmp1 = Op.Val->getOpcode() == ISD::UREM ?
458 BuildUDIV(Op.Val, DAG, NULL) :
459 BuildSDIV(Op.Val, DAG, NULL);
460 Tmp1 = DAG.getNode(ISD::MUL, VT, Tmp1, Op.getOperand(1));
461 Tmp1 = DAG.getNode(ISD::SUB, VT, Op.getOperand(0), Tmp1);
467 if (MVT::isInteger(Op.getValueType())) {
468 if (Op.getOperand(1).getOpcode() == ISD::Constant)
469 return Op.getOpcode() == ISD::SDIV ? BuildSDIV(Op.Val, DAG, NULL)
470 : BuildUDIV(Op.Val, DAG, NULL);
471 const char* opstr = 0;
472 switch (Op.getOpcode()) {
473 case ISD::UREM: opstr = "__remqu"; break;
474 case ISD::SREM: opstr = "__remq"; break;
475 case ISD::UDIV: opstr = "__divqu"; break;
476 case ISD::SDIV: opstr = "__divq"; break;
478 SDOperand Tmp1 = Op.getOperand(0),
479 Tmp2 = Op.getOperand(1),
480 Addr = DAG.getExternalSymbol(opstr, MVT::i64);
481 return DAG.getNode(AlphaISD::DivCall, MVT::i64, Addr, Tmp1, Tmp2);
486 SDOperand Chain = Op.getOperand(0);
487 SDOperand VAListP = Op.getOperand(1);
488 SrcValueSDNode *VAListS = cast<SrcValueSDNode>(Op.getOperand(2));
490 SDOperand Base = DAG.getLoad(MVT::i64, Chain, VAListP, VAListS->getValue(),
491 VAListS->getOffset());
492 SDOperand Tmp = DAG.getNode(ISD::ADD, MVT::i64, VAListP,
493 DAG.getConstant(8, MVT::i64));
494 SDOperand Offset = DAG.getExtLoad(ISD::SEXTLOAD, MVT::i64, Base.getValue(1),
495 Tmp, NULL, 0, MVT::i32);
496 SDOperand DataPtr = DAG.getNode(ISD::ADD, MVT::i64, Base, Offset);
497 if (MVT::isFloatingPoint(Op.getValueType()))
499 //if fp && Offset < 6*8, then subtract 6*8 from DataPtr
500 SDOperand FPDataPtr = DAG.getNode(ISD::SUB, MVT::i64, DataPtr,
501 DAG.getConstant(8*6, MVT::i64));
502 SDOperand CC = DAG.getSetCC(MVT::i64, Offset,
503 DAG.getConstant(8*6, MVT::i64), ISD::SETLT);
504 DataPtr = DAG.getNode(ISD::SELECT, MVT::i64, CC, FPDataPtr, DataPtr);
507 SDOperand NewOffset = DAG.getNode(ISD::ADD, MVT::i64, Offset,
508 DAG.getConstant(8, MVT::i64));
509 SDOperand Update = DAG.getTruncStore(Offset.getValue(1), NewOffset,
510 Tmp, NULL, 0, MVT::i32);
513 if (Op.getValueType() == MVT::i32)
514 Result = DAG.getExtLoad(ISD::SEXTLOAD, MVT::i64, Update, DataPtr,
517 Result = DAG.getLoad(Op.getValueType(), Update, DataPtr, NULL, 0);
521 SDOperand Chain = Op.getOperand(0);
522 SDOperand DestP = Op.getOperand(1);
523 SDOperand SrcP = Op.getOperand(2);
524 SrcValueSDNode *DestS = cast<SrcValueSDNode>(Op.getOperand(3));
525 SrcValueSDNode *SrcS = cast<SrcValueSDNode>(Op.getOperand(4));
527 SDOperand Val = DAG.getLoad(getPointerTy(), Chain, SrcP,
528 SrcS->getValue(), SrcS->getOffset());
529 SDOperand Result = DAG.getStore(Val.getValue(1), Val, DestP, DestS->getValue(),
531 SDOperand NP = DAG.getNode(ISD::ADD, MVT::i64, SrcP,
532 DAG.getConstant(8, MVT::i64));
533 Val = DAG.getExtLoad(ISD::SEXTLOAD, MVT::i64, Result, NP, NULL,0, MVT::i32);
534 SDOperand NPD = DAG.getNode(ISD::ADD, MVT::i64, DestP,
535 DAG.getConstant(8, MVT::i64));
536 return DAG.getTruncStore(Val.getValue(1), Val, NPD, NULL, 0, MVT::i32);
539 SDOperand Chain = Op.getOperand(0);
540 SDOperand VAListP = Op.getOperand(1);
541 SrcValueSDNode *VAListS = cast<SrcValueSDNode>(Op.getOperand(2));
543 // vastart stores the address of the VarArgsBase and VarArgsOffset
544 SDOperand FR = DAG.getFrameIndex(VarArgsBase, MVT::i64);
545 SDOperand S1 = DAG.getStore(Chain, FR, VAListP, VAListS->getValue(),
546 VAListS->getOffset());
547 SDOperand SA2 = DAG.getNode(ISD::ADD, MVT::i64, VAListP,
548 DAG.getConstant(8, MVT::i64));
549 return DAG.getTruncStore(S1, DAG.getConstant(VarArgsOffset, MVT::i64),
550 SA2, NULL, 0, MVT::i32);
552 case ISD::RETURNADDR:
553 return DAG.getNode(AlphaISD::GlobalRetAddr, MVT::i64);
555 case ISD::FRAMEADDR: break;
561 SDOperand AlphaTargetLowering::CustomPromoteOperation(SDOperand Op,
563 assert(Op.getValueType() == MVT::i32 &&
564 Op.getOpcode() == ISD::VAARG &&
565 "Unknown node to custom promote!");
567 // The code in LowerOperation already handles i32 vaarg
568 return LowerOperation(Op, DAG);
574 /// getConstraintType - Given a constraint letter, return the type of
575 /// constraint it is for this target.
576 AlphaTargetLowering::ConstraintType
577 AlphaTargetLowering::getConstraintType(const std::string &Constraint) const {
578 if (Constraint.size() == 1) {
579 switch (Constraint[0]) {
583 return C_RegisterClass;
586 return TargetLowering::getConstraintType(Constraint);
589 std::vector<unsigned> AlphaTargetLowering::
590 getRegClassForInlineAsmConstraint(const std::string &Constraint,
591 MVT::ValueType VT) const {
592 if (Constraint.size() == 1) {
593 switch (Constraint[0]) {
594 default: break; // Unknown constriant letter
596 return make_vector<unsigned>(Alpha::F0 , Alpha::F1 , Alpha::F2 ,
597 Alpha::F3 , Alpha::F4 , Alpha::F5 ,
598 Alpha::F6 , Alpha::F7 , Alpha::F8 ,
599 Alpha::F9 , Alpha::F10, Alpha::F11,
600 Alpha::F12, Alpha::F13, Alpha::F14,
601 Alpha::F15, Alpha::F16, Alpha::F17,
602 Alpha::F18, Alpha::F19, Alpha::F20,
603 Alpha::F21, Alpha::F22, Alpha::F23,
604 Alpha::F24, Alpha::F25, Alpha::F26,
605 Alpha::F27, Alpha::F28, Alpha::F29,
606 Alpha::F30, Alpha::F31, 0);
608 return make_vector<unsigned>(Alpha::R0 , Alpha::R1 , Alpha::R2 ,
609 Alpha::R3 , Alpha::R4 , Alpha::R5 ,
610 Alpha::R6 , Alpha::R7 , Alpha::R8 ,
611 Alpha::R9 , Alpha::R10, Alpha::R11,
612 Alpha::R12, Alpha::R13, Alpha::R14,
613 Alpha::R15, Alpha::R16, Alpha::R17,
614 Alpha::R18, Alpha::R19, Alpha::R20,
615 Alpha::R21, Alpha::R22, Alpha::R23,
616 Alpha::R24, Alpha::R25, Alpha::R26,
617 Alpha::R27, Alpha::R28, Alpha::R29,
618 Alpha::R30, Alpha::R31, 0);
622 return std::vector<unsigned>();