1 //===-- AlphaISelLowering.cpp - Alpha DAG Lowering Implementation ---------===//
3 // The LLVM Compiler Infrastructure
5 // This file was developed by Andrew Lenharth and is distributed under
6 // the University of Illinois Open Source License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file implements the AlphaISelLowering class.
12 //===----------------------------------------------------------------------===//
14 #include "AlphaISelLowering.h"
15 #include "AlphaTargetMachine.h"
16 #include "llvm/CodeGen/MachineFrameInfo.h"
17 #include "llvm/CodeGen/MachineFunction.h"
18 #include "llvm/CodeGen/MachineInstrBuilder.h"
19 #include "llvm/CodeGen/SelectionDAG.h"
20 #include "llvm/CodeGen/SSARegMap.h"
21 #include "llvm/Constants.h"
22 #include "llvm/Function.h"
23 #include "llvm/Support/CommandLine.h"
29 extern cl::opt<bool> EnableAlphaIDIV;
30 extern cl::opt<bool> EnableAlphaCount;
31 extern cl::opt<bool> EnableAlphaLSMark;
34 /// AddLiveIn - This helper function adds the specified physical register to the
35 /// MachineFunction as a live in value. It also creates a corresponding virtual
37 static unsigned AddLiveIn(MachineFunction &MF, unsigned PReg,
38 TargetRegisterClass *RC) {
39 assert(RC->contains(PReg) && "Not the correct regclass!");
40 unsigned VReg = MF.getSSARegMap()->createVirtualRegister(RC);
41 MF.addLiveIn(PReg, VReg);
45 AlphaTargetLowering::AlphaTargetLowering(TargetMachine &TM) : TargetLowering(TM) {
46 // Set up the TargetLowering object.
47 //I am having problems with shr n ubyte 1
48 setShiftAmountType(MVT::i64);
49 setSetCCResultType(MVT::i64);
50 setSetCCResultContents(ZeroOrOneSetCCResult);
52 addRegisterClass(MVT::i64, Alpha::GPRCRegisterClass);
53 addRegisterClass(MVT::f64, Alpha::F8RCRegisterClass);
54 addRegisterClass(MVT::f32, Alpha::F4RCRegisterClass);
56 setOperationAction(ISD::BRCONDTWOWAY, MVT::Other, Expand);
57 setOperationAction(ISD::BRTWOWAY_CC, MVT::Other, Expand);
59 setOperationAction(ISD::EXTLOAD, MVT::i1, Promote);
60 setOperationAction(ISD::EXTLOAD, MVT::f32, Expand);
62 setOperationAction(ISD::ZEXTLOAD, MVT::i1, Promote);
63 setOperationAction(ISD::ZEXTLOAD, MVT::i32, Expand);
65 setOperationAction(ISD::SEXTLOAD, MVT::i1, Promote);
66 setOperationAction(ISD::SEXTLOAD, MVT::i8, Expand);
67 setOperationAction(ISD::SEXTLOAD, MVT::i16, Expand);
69 setOperationAction(ISD::TRUNCSTORE, MVT::i1, Promote);
71 setOperationAction(ISD::FREM, MVT::f32, Expand);
72 setOperationAction(ISD::FREM, MVT::f64, Expand);
74 setOperationAction(ISD::UINT_TO_FP, MVT::i64, Expand);
75 setOperationAction(ISD::SINT_TO_FP, MVT::i64, Custom);
76 setOperationAction(ISD::FP_TO_UINT, MVT::i64, Expand);
77 setOperationAction(ISD::FP_TO_SINT, MVT::i64, Custom);
79 if (!TM.getSubtarget<AlphaSubtarget>().hasCT()) {
80 setOperationAction(ISD::CTPOP , MVT::i64 , Expand);
81 setOperationAction(ISD::CTTZ , MVT::i64 , Expand);
82 setOperationAction(ISD::CTLZ , MVT::i64 , Expand);
84 setOperationAction(ISD::ROTL , MVT::i64, Expand);
85 setOperationAction(ISD::ROTR , MVT::i64, Expand);
87 setOperationAction(ISD::SREM , MVT::i64, Custom);
88 setOperationAction(ISD::UREM , MVT::i64, Custom);
89 setOperationAction(ISD::SDIV , MVT::i64, Custom);
90 setOperationAction(ISD::UDIV , MVT::i64, Custom);
92 setOperationAction(ISD::MEMMOVE , MVT::Other, Expand);
93 setOperationAction(ISD::MEMSET , MVT::Other, Expand);
94 setOperationAction(ISD::MEMCPY , MVT::Other, Expand);
96 // We don't support sin/cos/sqrt
97 setOperationAction(ISD::FSIN , MVT::f64, Expand);
98 setOperationAction(ISD::FCOS , MVT::f64, Expand);
99 setOperationAction(ISD::FSQRT, MVT::f64, Expand);
100 setOperationAction(ISD::FSIN , MVT::f32, Expand);
101 setOperationAction(ISD::FCOS , MVT::f32, Expand);
102 setOperationAction(ISD::FSQRT, MVT::f32, Expand);
104 setOperationAction(ISD::SETCC, MVT::f32, Promote);
106 // We don't have line number support yet.
107 setOperationAction(ISD::LOCATION, MVT::Other, Expand);
108 setOperationAction(ISD::DEBUG_LOC, MVT::Other, Expand);
109 setOperationAction(ISD::DEBUG_LABEL, MVT::Other, Expand);
111 // Not implemented yet.
112 setOperationAction(ISD::STACKSAVE, MVT::Other, Expand);
113 setOperationAction(ISD::STACKRESTORE, MVT::Other, Expand);
115 // We want to legalize GlobalAddress and ConstantPool and
116 // ExternalSymbols nodes into the appropriate instructions to
117 // materialize the address.
118 setOperationAction(ISD::GlobalAddress, MVT::i64, Custom);
119 setOperationAction(ISD::ConstantPool, MVT::i64, Custom);
120 setOperationAction(ISD::ExternalSymbol, MVT::i64, Custom);
122 addLegalFPImmediate(+0.0); //F31
123 addLegalFPImmediate(-0.0); //-F31
125 computeRegisterProperties();
127 useITOF = TM.getSubtarget<AlphaSubtarget>().hasF2I();
131 //http://www.cs.arizona.edu/computer.help/policy/DIGITAL_unix/AA-PY8AC-TET1_html/callCH3.html#BLOCK21
133 //For now, just use variable size stack frame format
135 //In a standard call, the first six items are passed in registers $16
136 //- $21 and/or registers $f16 - $f21. (See Section 4.1.2 for details
137 //of argument-to-register correspondence.) The remaining items are
138 //collected in a memory argument list that is a naturally aligned
139 //array of quadwords. In a standard call, this list, if present, must
140 //be passed at 0(SP).
141 //7 ... n 0(SP) ... (n-7)*8(SP)
149 std::vector<SDOperand>
150 AlphaTargetLowering::LowerArguments(Function &F, SelectionDAG &DAG)
152 MachineFunction &MF = DAG.getMachineFunction();
153 MachineFrameInfo *MFI = MF.getFrameInfo();
154 MachineBasicBlock& BB = MF.front();
155 std::vector<SDOperand> ArgValues;
157 unsigned args_int[] = {
158 Alpha::R16, Alpha::R17, Alpha::R18, Alpha::R19, Alpha::R20, Alpha::R21};
159 unsigned args_float[] = {
160 Alpha::F16, Alpha::F17, Alpha::F18, Alpha::F19, Alpha::F20, Alpha::F21};
164 GP = AddLiveIn(MF, Alpha::R29, getRegClassFor(MVT::i64));
165 RA = AddLiveIn(MF, Alpha::R26, getRegClassFor(MVT::i64));
167 for (Function::arg_iterator I = F.arg_begin(), E = F.arg_end(); I != E; ++I)
172 MVT::ValueType VT = getValueType(I->getType());
175 std::cerr << "Unknown Type " << VT << "\n";
179 args_float[count] = AddLiveIn(MF, args_float[count], getRegClassFor(VT));
180 argt = DAG.getCopyFromReg(DAG.getRoot(), args_float[count], VT);
181 DAG.setRoot(argt.getValue(1));
188 args_int[count] = AddLiveIn(MF, args_int[count], getRegClassFor(MVT::i64));
189 argt = DAG.getCopyFromReg(DAG.getRoot(), args_int[count], MVT::i64);
190 DAG.setRoot(argt.getValue(1));
191 if (VT != MVT::i64) {
193 I->getType()->isSigned() ? ISD::AssertSext : ISD::AssertZext;
194 argt = DAG.getNode(AssertOp, MVT::i64, argt,
195 DAG.getValueType(VT));
196 argt = DAG.getNode(ISD::TRUNCATE, VT, argt);
201 // Create the frame index object for this incoming parameter...
202 int FI = MFI->CreateFixedObject(8, 8 * (count - 6));
204 // Create the SelectionDAG nodes corresponding to a load
205 //from this parameter
206 SDOperand FIN = DAG.getFrameIndex(FI, MVT::i64);
207 argt = DAG.getLoad(getValueType(I->getType()),
208 DAG.getEntryNode(), FIN, DAG.getSrcValue(NULL));
211 ArgValues.push_back(argt);
214 // If the functions takes variable number of arguments, copy all regs to stack
216 VarArgsOffset = count * 8;
217 std::vector<SDOperand> LS;
218 for (int i = 0; i < 6; ++i) {
219 if (MRegisterInfo::isPhysicalRegister(args_int[i]))
220 args_int[i] = AddLiveIn(MF, args_int[i], getRegClassFor(MVT::i64));
221 SDOperand argt = DAG.getCopyFromReg(DAG.getRoot(), args_int[i], MVT::i64);
222 int FI = MFI->CreateFixedObject(8, -8 * (6 - i));
223 if (i == 0) VarArgsBase = FI;
224 SDOperand SDFI = DAG.getFrameIndex(FI, MVT::i64);
225 LS.push_back(DAG.getNode(ISD::STORE, MVT::Other, DAG.getRoot(), argt,
226 SDFI, DAG.getSrcValue(NULL)));
228 if (MRegisterInfo::isPhysicalRegister(args_float[i]))
229 args_float[i] = AddLiveIn(MF, args_float[i], getRegClassFor(MVT::f64));
230 argt = DAG.getCopyFromReg(DAG.getRoot(), args_float[i], MVT::f64);
231 FI = MFI->CreateFixedObject(8, - 8 * (12 - i));
232 SDFI = DAG.getFrameIndex(FI, MVT::i64);
233 LS.push_back(DAG.getNode(ISD::STORE, MVT::Other, DAG.getRoot(), argt,
234 SDFI, DAG.getSrcValue(NULL)));
237 //Set up a token factor with all the stack traffic
238 DAG.setRoot(DAG.getNode(ISD::TokenFactor, MVT::Other, LS));
241 // Finally, inform the code generator which regs we return values in.
242 switch (getValueType(F.getReturnType())) {
243 default: assert(0 && "Unknown type!");
244 case MVT::isVoid: break;
250 MF.addLiveOut(Alpha::R0);
254 MF.addLiveOut(Alpha::F0);
258 //return the arguments
262 std::pair<SDOperand, SDOperand>
263 AlphaTargetLowering::LowerCallTo(SDOperand Chain,
264 const Type *RetTy, bool isVarArg,
265 unsigned CallingConv, bool isTailCall,
266 SDOperand Callee, ArgListTy &Args,
270 NumBytes = (Args.size() - 6) * 8;
272 Chain = DAG.getNode(ISD::CALLSEQ_START, MVT::Other, Chain,
273 DAG.getConstant(NumBytes, getPointerTy()));
274 std::vector<SDOperand> args_to_use;
275 for (unsigned i = 0, e = Args.size(); i != e; ++i)
277 switch (getValueType(Args[i].second)) {
278 default: assert(0 && "Unexpected ValueType for argument!");
283 // Promote the integer to 64 bits. If the input type is signed use a
284 // sign extend, otherwise use a zero extend.
285 if (Args[i].second->isSigned())
286 Args[i].first = DAG.getNode(ISD::SIGN_EXTEND, MVT::i64, Args[i].first);
288 Args[i].first = DAG.getNode(ISD::ZERO_EXTEND, MVT::i64, Args[i].first);
295 args_to_use.push_back(Args[i].first);
298 std::vector<MVT::ValueType> RetVals;
299 MVT::ValueType RetTyVT = getValueType(RetTy);
300 MVT::ValueType ActualRetTyVT = RetTyVT;
301 if (RetTyVT >= MVT::i1 && RetTyVT <= MVT::i32)
302 ActualRetTyVT = MVT::i64;
304 if (RetTyVT != MVT::isVoid)
305 RetVals.push_back(ActualRetTyVT);
306 RetVals.push_back(MVT::Other);
308 SDOperand TheCall = SDOperand(DAG.getCall(RetVals,
309 Chain, Callee, args_to_use), 0);
310 Chain = TheCall.getValue(RetTyVT != MVT::isVoid);
311 Chain = DAG.getNode(ISD::CALLSEQ_END, MVT::Other, Chain,
312 DAG.getConstant(NumBytes, getPointerTy()));
313 SDOperand RetVal = TheCall;
315 if (RetTyVT != ActualRetTyVT) {
316 RetVal = DAG.getNode(RetTy->isSigned() ? ISD::AssertSext : ISD::AssertZext,
317 MVT::i64, RetVal, DAG.getValueType(RetTyVT));
318 RetVal = DAG.getNode(ISD::TRUNCATE, RetTyVT, RetVal);
321 return std::make_pair(RetVal, Chain);
324 SDOperand AlphaTargetLowering::LowerVAStart(SDOperand Chain, SDOperand VAListP,
325 Value *VAListV, SelectionDAG &DAG) {
326 // vastart stores the address of the VarArgsBase and VarArgsOffset
327 SDOperand FR = DAG.getFrameIndex(VarArgsBase, MVT::i64);
328 SDOperand S1 = DAG.getNode(ISD::STORE, MVT::Other, Chain, FR, VAListP,
329 DAG.getSrcValue(VAListV));
330 SDOperand SA2 = DAG.getNode(ISD::ADD, MVT::i64, VAListP,
331 DAG.getConstant(8, MVT::i64));
332 return DAG.getNode(ISD::TRUNCSTORE, MVT::Other, S1,
333 DAG.getConstant(VarArgsOffset, MVT::i64), SA2,
334 DAG.getSrcValue(VAListV, 8), DAG.getValueType(MVT::i32));
337 std::pair<SDOperand,SDOperand> AlphaTargetLowering::
338 LowerVAArg(SDOperand Chain, SDOperand VAListP, Value *VAListV,
339 const Type *ArgTy, SelectionDAG &DAG) {
340 SDOperand Base = DAG.getLoad(MVT::i64, Chain, VAListP,
341 DAG.getSrcValue(VAListV));
342 SDOperand Tmp = DAG.getNode(ISD::ADD, MVT::i64, VAListP,
343 DAG.getConstant(8, MVT::i64));
344 SDOperand Offset = DAG.getExtLoad(ISD::SEXTLOAD, MVT::i64, Base.getValue(1),
345 Tmp, DAG.getSrcValue(VAListV, 8), MVT::i32);
346 SDOperand DataPtr = DAG.getNode(ISD::ADD, MVT::i64, Base, Offset);
347 if (ArgTy->isFloatingPoint())
349 //if fp && Offset < 6*8, then subtract 6*8 from DataPtr
350 SDOperand FPDataPtr = DAG.getNode(ISD::SUB, MVT::i64, DataPtr,
351 DAG.getConstant(8*6, MVT::i64));
352 SDOperand CC = DAG.getSetCC(MVT::i64, Offset,
353 DAG.getConstant(8*6, MVT::i64), ISD::SETLT);
354 DataPtr = DAG.getNode(ISD::SELECT, MVT::i64, CC, FPDataPtr, DataPtr);
358 if (ArgTy == Type::IntTy)
359 Result = DAG.getExtLoad(ISD::SEXTLOAD, MVT::i64, Offset.getValue(1),
360 DataPtr, DAG.getSrcValue(NULL), MVT::i32);
361 else if (ArgTy == Type::UIntTy)
362 Result = DAG.getExtLoad(ISD::ZEXTLOAD, MVT::i64, Offset.getValue(1),
363 DataPtr, DAG.getSrcValue(NULL), MVT::i32);
365 Result = DAG.getLoad(getValueType(ArgTy), Offset.getValue(1), DataPtr,
366 DAG.getSrcValue(NULL));
368 SDOperand NewOffset = DAG.getNode(ISD::ADD, MVT::i64, Offset,
369 DAG.getConstant(8, MVT::i64));
370 SDOperand Update = DAG.getNode(ISD::TRUNCSTORE, MVT::Other,
371 Result.getValue(1), NewOffset,
372 Tmp, DAG.getSrcValue(VAListV, 8),
373 DAG.getValueType(MVT::i32));
374 Result = DAG.getNode(ISD::TRUNCATE, getValueType(ArgTy), Result);
376 return std::make_pair(Result, Update);
380 SDOperand AlphaTargetLowering::
381 LowerVACopy(SDOperand Chain, SDOperand SrcP, Value *SrcV, SDOperand DestP,
382 Value *DestV, SelectionDAG &DAG) {
383 SDOperand Val = DAG.getLoad(getPointerTy(), Chain, SrcP,
384 DAG.getSrcValue(SrcV));
385 SDOperand Result = DAG.getNode(ISD::STORE, MVT::Other, Val.getValue(1),
386 Val, DestP, DAG.getSrcValue(DestV));
387 SDOperand NP = DAG.getNode(ISD::ADD, MVT::i64, SrcP,
388 DAG.getConstant(8, MVT::i64));
389 Val = DAG.getExtLoad(ISD::SEXTLOAD, MVT::i64, Result, NP,
390 DAG.getSrcValue(SrcV, 8), MVT::i32);
391 SDOperand NPD = DAG.getNode(ISD::ADD, MVT::i64, DestP,
392 DAG.getConstant(8, MVT::i64));
393 return DAG.getNode(ISD::TRUNCSTORE, MVT::Other, Val.getValue(1),
394 Val, NPD, DAG.getSrcValue(DestV, 8),
395 DAG.getValueType(MVT::i32));
398 void AlphaTargetLowering::restoreGP(MachineBasicBlock* BB)
400 BuildMI(BB, Alpha::BIS, 2, Alpha::R29).addReg(GP).addReg(GP);
402 void AlphaTargetLowering::restoreRA(MachineBasicBlock* BB)
404 BuildMI(BB, Alpha::BIS, 2, Alpha::R26).addReg(RA).addReg(RA);
408 /// LowerOperation - Provide custom lowering hooks for some operations.
410 SDOperand AlphaTargetLowering::LowerOperation(SDOperand Op, SelectionDAG &DAG) {
411 switch (Op.getOpcode()) {
412 default: assert(0 && "Wasn't expecting to be able to lower this!");
413 case ISD::SINT_TO_FP: {
414 assert(MVT::i64 == Op.getOperand(0).getValueType() &&
415 "Unhandled SINT_TO_FP type in custom expander!");
417 bool isDouble = MVT::f64 == Op.getValueType();
419 LD = DAG.getNode(AlphaISD::ITOFT_, MVT::f64, Op.getOperand(0));
422 DAG.getMachineFunction().getFrameInfo()->CreateStackObject(8, 8);
423 SDOperand FI = DAG.getFrameIndex(FrameIdx, MVT::i64);
424 SDOperand ST = DAG.getNode(ISD::STORE, MVT::Other, DAG.getEntryNode(),
425 Op.getOperand(0), FI, DAG.getSrcValue(0));
426 LD = DAG.getLoad(MVT::f64, ST, FI, DAG.getSrcValue(0));
428 SDOperand FP = DAG.getNode(isDouble?AlphaISD::CVTQT_:AlphaISD::CVTQS_,
429 isDouble?MVT::f64:MVT::f32, LD);
432 case ISD::FP_TO_SINT: {
433 bool isDouble = MVT::f64 == Op.getOperand(0).getValueType();
434 SDOperand src = Op.getOperand(0);
436 if (!isDouble) //Promote
437 src = DAG.getNode(ISD::FP_EXTEND, MVT::f64, src);
439 src = DAG.getNode(AlphaISD::CVTTQ_, MVT::f64, src);
442 return DAG.getNode(AlphaISD::FTOIT_, MVT::i64, src);
445 DAG.getMachineFunction().getFrameInfo()->CreateStackObject(8, 8);
446 SDOperand FI = DAG.getFrameIndex(FrameIdx, MVT::i64);
447 SDOperand ST = DAG.getNode(ISD::STORE, MVT::Other, DAG.getEntryNode(),
448 src, FI, DAG.getSrcValue(0));
449 return DAG.getLoad(MVT::i64, ST, FI, DAG.getSrcValue(0));
452 case ISD::ConstantPool: {
453 Constant *C = cast<ConstantPoolSDNode>(Op)->get();
454 SDOperand CPI = DAG.getTargetConstantPool(C, MVT::i64);
456 SDOperand Hi = DAG.getNode(AlphaISD::GPRelHi, MVT::i64, CPI,
457 DAG.getNode(AlphaISD::GlobalBaseReg, MVT::i64));
458 SDOperand Lo = DAG.getNode(AlphaISD::GPRelLo, MVT::i64, CPI, Hi);
461 case ISD::GlobalAddress: {
462 GlobalAddressSDNode *GSDN = cast<GlobalAddressSDNode>(Op);
463 GlobalValue *GV = GSDN->getGlobal();
464 SDOperand GA = DAG.getTargetGlobalAddress(GV, MVT::i64, GSDN->getOffset());
466 if (!GV->hasWeakLinkage() && !GV->isExternal()) {
467 SDOperand Hi = DAG.getNode(AlphaISD::GPRelHi, MVT::i64, GA,
468 DAG.getNode(AlphaISD::GlobalBaseReg, MVT::i64));
469 SDOperand Lo = DAG.getNode(AlphaISD::GPRelLo, MVT::i64, GA, Hi);
472 return DAG.getNode(AlphaISD::RelLit, MVT::i64, GA, DAG.getNode(AlphaISD::GlobalBaseReg, MVT::i64));
474 case ISD::ExternalSymbol: {
475 return DAG.getNode(AlphaISD::RelLit, MVT::i64,
476 DAG.getTargetExternalSymbol(cast<ExternalSymbolSDNode>(Op)->getSymbol(), MVT::i64),
477 DAG.getNode(AlphaISD::GlobalBaseReg, MVT::i64));
484 if (MVT::isInteger(Op.getValueType())) {
485 const char* opstr = 0;
486 switch(Op.getOpcode()) {
487 case ISD::UREM: opstr = "__remqu"; break;
488 case ISD::SREM: opstr = "__remq"; break;
489 case ISD::UDIV: opstr = "__divqu"; break;
490 case ISD::SDIV: opstr = "__divq"; break;
492 SDOperand Tmp1 = Op.getOperand(0),
493 Tmp2 = Op.getOperand(1),
494 Addr = DAG.getExternalSymbol(opstr, MVT::i64);
495 return DAG.getNode(AlphaISD::DivCall, MVT::i64, Addr, Tmp1, Tmp2);