1 //===-- AlphaISelLowering.cpp - Alpha DAG Lowering Implementation ---------===//
3 // The LLVM Compiler Infrastructure
5 // This file was developed by Andrew Lenharth and is distributed under
6 // the University of Illinois Open Source License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file implements the AlphaISelLowering class.
12 //===----------------------------------------------------------------------===//
14 #include "AlphaISelLowering.h"
15 #include "AlphaTargetMachine.h"
16 #include "llvm/CodeGen/MachineFrameInfo.h"
17 #include "llvm/CodeGen/MachineFunction.h"
18 #include "llvm/CodeGen/MachineInstrBuilder.h"
19 #include "llvm/CodeGen/SelectionDAG.h"
20 #include "llvm/CodeGen/SSARegMap.h"
21 #include "llvm/Constants.h"
22 #include "llvm/Function.h"
23 #include "llvm/Module.h"
24 #include "llvm/Support/CommandLine.h"
30 extern cl::opt<bool> EnableAlphaIDIV;
31 extern cl::opt<bool> EnableAlphaCount;
32 extern cl::opt<bool> EnableAlphaLSMark;
35 /// AddLiveIn - This helper function adds the specified physical register to the
36 /// MachineFunction as a live in value. It also creates a corresponding virtual
38 static unsigned AddLiveIn(MachineFunction &MF, unsigned PReg,
39 TargetRegisterClass *RC) {
40 assert(RC->contains(PReg) && "Not the correct regclass!");
41 unsigned VReg = MF.getSSARegMap()->createVirtualRegister(RC);
42 MF.addLiveIn(PReg, VReg);
46 AlphaTargetLowering::AlphaTargetLowering(TargetMachine &TM) : TargetLowering(TM) {
47 // Set up the TargetLowering object.
48 //I am having problems with shr n ubyte 1
49 setShiftAmountType(MVT::i64);
50 setSetCCResultType(MVT::i64);
51 setSetCCResultContents(ZeroOrOneSetCCResult);
53 addRegisterClass(MVT::i64, Alpha::GPRCRegisterClass);
54 addRegisterClass(MVT::f64, Alpha::F8RCRegisterClass);
55 addRegisterClass(MVT::f32, Alpha::F4RCRegisterClass);
57 setOperationAction(ISD::BRCONDTWOWAY, MVT::Other, Expand);
58 setOperationAction(ISD::BRTWOWAY_CC, MVT::Other, Expand);
60 setOperationAction(ISD::EXTLOAD, MVT::i1, Promote);
61 setOperationAction(ISD::EXTLOAD, MVT::f32, Expand);
63 setOperationAction(ISD::ZEXTLOAD, MVT::i1, Promote);
64 setOperationAction(ISD::ZEXTLOAD, MVT::i32, Expand);
66 setOperationAction(ISD::SEXTLOAD, MVT::i1, Promote);
67 setOperationAction(ISD::SEXTLOAD, MVT::i8, Expand);
68 setOperationAction(ISD::SEXTLOAD, MVT::i16, Expand);
70 setOperationAction(ISD::TRUNCSTORE, MVT::i1, Promote);
72 if (EnableAlphaLSMark) {
73 setOperationAction(ISD::LOAD, MVT::i64, Custom);
74 setOperationAction(ISD::LOAD, MVT::f64, Custom);
75 setOperationAction(ISD::LOAD, MVT::f32, Custom);
78 setOperationAction(ISD::FREM, MVT::f32, Expand);
79 setOperationAction(ISD::FREM, MVT::f64, Expand);
81 setOperationAction(ISD::UINT_TO_FP, MVT::i64, Expand);
82 setOperationAction(ISD::SINT_TO_FP, MVT::i64, Custom);
83 setOperationAction(ISD::FP_TO_UINT, MVT::i64, Expand);
84 setOperationAction(ISD::FP_TO_SINT, MVT::i64, Custom);
86 if (!TM.getSubtarget<AlphaSubtarget>().hasCT()) {
87 setOperationAction(ISD::CTPOP , MVT::i64 , Expand);
88 setOperationAction(ISD::CTTZ , MVT::i64 , Expand);
89 setOperationAction(ISD::CTLZ , MVT::i64 , Expand);
91 setOperationAction(ISD::BSWAP , MVT::i64, Expand);
92 setOperationAction(ISD::ROTL , MVT::i64, Expand);
93 setOperationAction(ISD::ROTR , MVT::i64, Expand);
95 setOperationAction(ISD::SREM , MVT::i64, Custom);
96 setOperationAction(ISD::UREM , MVT::i64, Custom);
97 setOperationAction(ISD::SDIV , MVT::i64, Custom);
98 setOperationAction(ISD::UDIV , MVT::i64, Custom);
100 setOperationAction(ISD::MEMMOVE , MVT::Other, Expand);
101 setOperationAction(ISD::MEMSET , MVT::Other, Expand);
102 setOperationAction(ISD::MEMCPY , MVT::Other, Expand);
104 // We don't support sin/cos/sqrt
105 setOperationAction(ISD::FSIN , MVT::f64, Expand);
106 setOperationAction(ISD::FCOS , MVT::f64, Expand);
107 setOperationAction(ISD::FSIN , MVT::f32, Expand);
108 setOperationAction(ISD::FCOS , MVT::f32, Expand);
110 setOperationAction(ISD::FSQRT, MVT::f64, Expand);
111 setOperationAction(ISD::FSQRT, MVT::f32, Expand);
113 setOperationAction(ISD::SETCC, MVT::f32, Promote);
115 // We don't have line number support yet.
116 setOperationAction(ISD::LOCATION, MVT::Other, Expand);
117 setOperationAction(ISD::DEBUG_LOC, MVT::Other, Expand);
118 setOperationAction(ISD::DEBUG_LABEL, MVT::Other, Expand);
120 // Not implemented yet.
121 setOperationAction(ISD::STACKSAVE, MVT::Other, Expand);
122 setOperationAction(ISD::STACKRESTORE, MVT::Other, Expand);
123 setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i64, Expand);
125 // We want to legalize GlobalAddress and ConstantPool and
126 // ExternalSymbols nodes into the appropriate instructions to
127 // materialize the address.
128 setOperationAction(ISD::GlobalAddress, MVT::i64, Custom);
129 setOperationAction(ISD::ConstantPool, MVT::i64, Custom);
130 setOperationAction(ISD::ExternalSymbol, MVT::i64, Custom);
132 setStackPointerRegisterToSaveRestore(Alpha::R30);
134 addLegalFPImmediate(+0.0); //F31
135 addLegalFPImmediate(-0.0); //-F31
137 computeRegisterProperties();
139 useITOF = TM.getSubtarget<AlphaSubtarget>().hasF2I();
142 const char *AlphaTargetLowering::getTargetNodeName(unsigned Opcode) const {
145 case AlphaISD::ITOFT_: return "Alpha::ITOFT_";
146 case AlphaISD::FTOIT_: return "Alpha::FTOIT_";
147 case AlphaISD::CVTQT_: return "Alpha::CVTQT_";
148 case AlphaISD::CVTQS_: return "Alpha::CVTQS_";
149 case AlphaISD::CVTTQ_: return "Alpha::CVTTQ_";
150 case AlphaISD::GPRelHi: return "Alpha::GPRelHi";
151 case AlphaISD::GPRelLo: return "Alpha::GPRelLo";
152 case AlphaISD::RelLit: return "Alpha::RelLit";
153 case AlphaISD::GlobalBaseReg: return "Alpha::GlobalBaseReg";
154 case AlphaISD::DivCall: return "Alpha::DivCall";
155 case AlphaISD::LDQ_: return "Alpha::LDQ_";
156 case AlphaISD::LDT_: return "Alpha::LDT_";
157 case AlphaISD::LDS_: return "Alpha::LDS_";
158 case AlphaISD::LDL_: return "Alpha::LDL_";
159 case AlphaISD::LDWU_: return "Alpha::LDWU_";
160 case AlphaISD::LDBU_: return "Alpha::LDBU_";
164 //http://www.cs.arizona.edu/computer.help/policy/DIGITAL_unix/AA-PY8AC-TET1_html/callCH3.html#BLOCK21
166 //For now, just use variable size stack frame format
168 //In a standard call, the first six items are passed in registers $16
169 //- $21 and/or registers $f16 - $f21. (See Section 4.1.2 for details
170 //of argument-to-register correspondence.) The remaining items are
171 //collected in a memory argument list that is a naturally aligned
172 //array of quadwords. In a standard call, this list, if present, must
173 //be passed at 0(SP).
174 //7 ... n 0(SP) ... (n-7)*8(SP)
182 std::vector<SDOperand>
183 AlphaTargetLowering::LowerArguments(Function &F, SelectionDAG &DAG)
185 MachineFunction &MF = DAG.getMachineFunction();
186 MachineFrameInfo *MFI = MF.getFrameInfo();
187 MachineBasicBlock& BB = MF.front();
188 std::vector<SDOperand> ArgValues;
190 unsigned args_int[] = {
191 Alpha::R16, Alpha::R17, Alpha::R18, Alpha::R19, Alpha::R20, Alpha::R21};
192 unsigned args_float[] = {
193 Alpha::F16, Alpha::F17, Alpha::F18, Alpha::F19, Alpha::F20, Alpha::F21};
197 GP = AddLiveIn(MF, Alpha::R29, getRegClassFor(MVT::i64));
198 RA = AddLiveIn(MF, Alpha::R26, getRegClassFor(MVT::i64));
200 for (Function::arg_iterator I = F.arg_begin(), E = F.arg_end(); I != E; ++I)
205 MVT::ValueType VT = getValueType(I->getType());
208 std::cerr << "Unknown Type " << VT << "\n";
212 args_float[count] = AddLiveIn(MF, args_float[count], getRegClassFor(VT));
213 argt = DAG.getCopyFromReg(DAG.getRoot(), args_float[count], VT);
214 DAG.setRoot(argt.getValue(1));
221 args_int[count] = AddLiveIn(MF, args_int[count], getRegClassFor(MVT::i64));
222 argt = DAG.getCopyFromReg(DAG.getRoot(), args_int[count], MVT::i64);
223 DAG.setRoot(argt.getValue(1));
224 if (VT != MVT::i64) {
226 I->getType()->isSigned() ? ISD::AssertSext : ISD::AssertZext;
227 argt = DAG.getNode(AssertOp, MVT::i64, argt,
228 DAG.getValueType(VT));
229 argt = DAG.getNode(ISD::TRUNCATE, VT, argt);
234 // Create the frame index object for this incoming parameter...
235 int FI = MFI->CreateFixedObject(8, 8 * (count - 6));
237 // Create the SelectionDAG nodes corresponding to a load
238 //from this parameter
239 SDOperand FIN = DAG.getFrameIndex(FI, MVT::i64);
240 argt = DAG.getLoad(getValueType(I->getType()),
241 DAG.getEntryNode(), FIN, DAG.getSrcValue(NULL));
244 ArgValues.push_back(argt);
247 // If the functions takes variable number of arguments, copy all regs to stack
249 VarArgsOffset = count * 8;
250 std::vector<SDOperand> LS;
251 for (int i = 0; i < 6; ++i) {
252 if (MRegisterInfo::isPhysicalRegister(args_int[i]))
253 args_int[i] = AddLiveIn(MF, args_int[i], getRegClassFor(MVT::i64));
254 SDOperand argt = DAG.getCopyFromReg(DAG.getRoot(), args_int[i], MVT::i64);
255 int FI = MFI->CreateFixedObject(8, -8 * (6 - i));
256 if (i == 0) VarArgsBase = FI;
257 SDOperand SDFI = DAG.getFrameIndex(FI, MVT::i64);
258 LS.push_back(DAG.getNode(ISD::STORE, MVT::Other, DAG.getRoot(), argt,
259 SDFI, DAG.getSrcValue(NULL)));
261 if (MRegisterInfo::isPhysicalRegister(args_float[i]))
262 args_float[i] = AddLiveIn(MF, args_float[i], getRegClassFor(MVT::f64));
263 argt = DAG.getCopyFromReg(DAG.getRoot(), args_float[i], MVT::f64);
264 FI = MFI->CreateFixedObject(8, - 8 * (12 - i));
265 SDFI = DAG.getFrameIndex(FI, MVT::i64);
266 LS.push_back(DAG.getNode(ISD::STORE, MVT::Other, DAG.getRoot(), argt,
267 SDFI, DAG.getSrcValue(NULL)));
270 //Set up a token factor with all the stack traffic
271 DAG.setRoot(DAG.getNode(ISD::TokenFactor, MVT::Other, LS));
274 // Finally, inform the code generator which regs we return values in.
275 switch (getValueType(F.getReturnType())) {
276 default: assert(0 && "Unknown type!");
277 case MVT::isVoid: break;
283 MF.addLiveOut(Alpha::R0);
287 MF.addLiveOut(Alpha::F0);
291 //return the arguments
295 std::pair<SDOperand, SDOperand>
296 AlphaTargetLowering::LowerCallTo(SDOperand Chain,
297 const Type *RetTy, bool isVarArg,
298 unsigned CallingConv, bool isTailCall,
299 SDOperand Callee, ArgListTy &Args,
303 NumBytes = (Args.size() - 6) * 8;
305 Chain = DAG.getNode(ISD::CALLSEQ_START, MVT::Other, Chain,
306 DAG.getConstant(NumBytes, getPointerTy()));
307 std::vector<SDOperand> args_to_use;
308 for (unsigned i = 0, e = Args.size(); i != e; ++i)
310 switch (getValueType(Args[i].second)) {
311 default: assert(0 && "Unexpected ValueType for argument!");
316 // Promote the integer to 64 bits. If the input type is signed use a
317 // sign extend, otherwise use a zero extend.
318 if (Args[i].second->isSigned())
319 Args[i].first = DAG.getNode(ISD::SIGN_EXTEND, MVT::i64, Args[i].first);
321 Args[i].first = DAG.getNode(ISD::ZERO_EXTEND, MVT::i64, Args[i].first);
328 args_to_use.push_back(Args[i].first);
331 std::vector<MVT::ValueType> RetVals;
332 MVT::ValueType RetTyVT = getValueType(RetTy);
333 MVT::ValueType ActualRetTyVT = RetTyVT;
334 if (RetTyVT >= MVT::i1 && RetTyVT <= MVT::i32)
335 ActualRetTyVT = MVT::i64;
337 if (RetTyVT != MVT::isVoid)
338 RetVals.push_back(ActualRetTyVT);
339 RetVals.push_back(MVT::Other);
341 SDOperand TheCall = SDOperand(DAG.getCall(RetVals,
342 Chain, Callee, args_to_use), 0);
343 Chain = TheCall.getValue(RetTyVT != MVT::isVoid);
344 Chain = DAG.getNode(ISD::CALLSEQ_END, MVT::Other, Chain,
345 DAG.getConstant(NumBytes, getPointerTy()));
346 SDOperand RetVal = TheCall;
348 if (RetTyVT != ActualRetTyVT) {
349 RetVal = DAG.getNode(RetTy->isSigned() ? ISD::AssertSext : ISD::AssertZext,
350 MVT::i64, RetVal, DAG.getValueType(RetTyVT));
351 RetVal = DAG.getNode(ISD::TRUNCATE, RetTyVT, RetVal);
354 return std::make_pair(RetVal, Chain);
357 SDOperand AlphaTargetLowering::LowerVAStart(SDOperand Chain, SDOperand VAListP,
358 Value *VAListV, SelectionDAG &DAG) {
359 // vastart stores the address of the VarArgsBase and VarArgsOffset
360 SDOperand FR = DAG.getFrameIndex(VarArgsBase, MVT::i64);
361 SDOperand S1 = DAG.getNode(ISD::STORE, MVT::Other, Chain, FR, VAListP,
362 DAG.getSrcValue(VAListV));
363 SDOperand SA2 = DAG.getNode(ISD::ADD, MVT::i64, VAListP,
364 DAG.getConstant(8, MVT::i64));
365 return DAG.getNode(ISD::TRUNCSTORE, MVT::Other, S1,
366 DAG.getConstant(VarArgsOffset, MVT::i64), SA2,
367 DAG.getSrcValue(VAListV, 8), DAG.getValueType(MVT::i32));
370 std::pair<SDOperand,SDOperand> AlphaTargetLowering::
371 LowerVAArg(SDOperand Chain, SDOperand VAListP, Value *VAListV,
372 const Type *ArgTy, SelectionDAG &DAG) {
373 SDOperand Base = DAG.getLoad(MVT::i64, Chain, VAListP,
374 DAG.getSrcValue(VAListV));
375 SDOperand Tmp = DAG.getNode(ISD::ADD, MVT::i64, VAListP,
376 DAG.getConstant(8, MVT::i64));
377 SDOperand Offset = DAG.getExtLoad(ISD::SEXTLOAD, MVT::i64, Base.getValue(1),
378 Tmp, DAG.getSrcValue(VAListV, 8), MVT::i32);
379 SDOperand DataPtr = DAG.getNode(ISD::ADD, MVT::i64, Base, Offset);
380 if (ArgTy->isFloatingPoint())
382 //if fp && Offset < 6*8, then subtract 6*8 from DataPtr
383 SDOperand FPDataPtr = DAG.getNode(ISD::SUB, MVT::i64, DataPtr,
384 DAG.getConstant(8*6, MVT::i64));
385 SDOperand CC = DAG.getSetCC(MVT::i64, Offset,
386 DAG.getConstant(8*6, MVT::i64), ISD::SETLT);
387 DataPtr = DAG.getNode(ISD::SELECT, MVT::i64, CC, FPDataPtr, DataPtr);
391 if (ArgTy == Type::IntTy)
392 Result = DAG.getExtLoad(ISD::SEXTLOAD, MVT::i64, Offset.getValue(1),
393 DataPtr, DAG.getSrcValue(NULL), MVT::i32);
394 else if (ArgTy == Type::UIntTy)
395 Result = DAG.getExtLoad(ISD::ZEXTLOAD, MVT::i64, Offset.getValue(1),
396 DataPtr, DAG.getSrcValue(NULL), MVT::i32);
398 Result = DAG.getLoad(getValueType(ArgTy), Offset.getValue(1), DataPtr,
399 DAG.getSrcValue(NULL));
401 SDOperand NewOffset = DAG.getNode(ISD::ADD, MVT::i64, Offset,
402 DAG.getConstant(8, MVT::i64));
403 SDOperand Update = DAG.getNode(ISD::TRUNCSTORE, MVT::Other,
404 Result.getValue(1), NewOffset,
405 Tmp, DAG.getSrcValue(VAListV, 8),
406 DAG.getValueType(MVT::i32));
407 Result = DAG.getNode(ISD::TRUNCATE, getValueType(ArgTy), Result);
409 return std::make_pair(Result, Update);
412 SDOperand AlphaTargetLowering::
413 LowerVACopy(SDOperand Chain, SDOperand SrcP, Value *SrcV, SDOperand DestP,
414 Value *DestV, SelectionDAG &DAG) {
415 SDOperand Val = DAG.getLoad(getPointerTy(), Chain, SrcP,
416 DAG.getSrcValue(SrcV));
417 SDOperand Result = DAG.getNode(ISD::STORE, MVT::Other, Val.getValue(1),
418 Val, DestP, DAG.getSrcValue(DestV));
419 SDOperand NP = DAG.getNode(ISD::ADD, MVT::i64, SrcP,
420 DAG.getConstant(8, MVT::i64));
421 Val = DAG.getExtLoad(ISD::SEXTLOAD, MVT::i64, Result, NP,
422 DAG.getSrcValue(SrcV, 8), MVT::i32);
423 SDOperand NPD = DAG.getNode(ISD::ADD, MVT::i64, DestP,
424 DAG.getConstant(8, MVT::i64));
425 return DAG.getNode(ISD::TRUNCSTORE, MVT::Other, Val.getValue(1),
426 Val, NPD, DAG.getSrcValue(DestV, 8),
427 DAG.getValueType(MVT::i32));
430 void AlphaTargetLowering::restoreGP(MachineBasicBlock* BB)
432 BuildMI(BB, Alpha::BIS, 2, Alpha::R29).addReg(GP).addReg(GP);
434 void AlphaTargetLowering::restoreRA(MachineBasicBlock* BB)
436 BuildMI(BB, Alpha::BIS, 2, Alpha::R26).addReg(RA).addReg(RA);
441 static void getValueInfo(const Value* v, int& type, int& fun, int& offset)
443 fun = type = offset = 0;
446 } else if (const GlobalValue* GV = dyn_cast<GlobalValue>(v)) {
448 const Module* M = GV->getParent();
449 for(Module::const_global_iterator ii = M->global_begin(); &*ii != GV; ++ii)
451 } else if (const Argument* Arg = dyn_cast<Argument>(v)) {
453 const Function* F = Arg->getParent();
454 const Module* M = F->getParent();
455 for(Module::const_iterator ii = M->begin(); &*ii != F; ++ii)
457 for(Function::const_arg_iterator ii = F->arg_begin(); &*ii != Arg; ++ii)
459 } else if (const Instruction* I = dyn_cast<Instruction>(v)) {
460 assert(dyn_cast<PointerType>(I->getType()));
462 const BasicBlock* bb = I->getParent();
463 const Function* F = bb->getParent();
464 const Module* M = F->getParent();
465 for(Module::const_iterator ii = M->begin(); &*ii != F; ++ii)
467 for(Function::const_iterator ii = F->begin(); &*ii != bb; ++ii)
468 offset += ii->size();
469 for(BasicBlock::const_iterator ii = bb->begin(); &*ii != I; ++ii)
471 } else if (const Constant* C = dyn_cast<Constant>(v)) {
472 //Don't know how to look these up yet
475 assert(0 && "Error in value marking");
477 //type = 4: register spilling
478 //type = 5: global address loading or constant loading
487 /// LowerOperation - Provide custom lowering hooks for some operations.
489 SDOperand AlphaTargetLowering::LowerOperation(SDOperand Op, SelectionDAG &DAG) {
490 switch (Op.getOpcode()) {
491 default: assert(0 && "Wasn't expecting to be able to lower this!");
492 case ISD::SINT_TO_FP: {
493 assert(MVT::i64 == Op.getOperand(0).getValueType() &&
494 "Unhandled SINT_TO_FP type in custom expander!");
496 bool isDouble = MVT::f64 == Op.getValueType();
498 LD = DAG.getNode(AlphaISD::ITOFT_, MVT::f64, Op.getOperand(0));
501 DAG.getMachineFunction().getFrameInfo()->CreateStackObject(8, 8);
502 SDOperand FI = DAG.getFrameIndex(FrameIdx, MVT::i64);
503 SDOperand ST = DAG.getNode(ISD::STORE, MVT::Other, DAG.getEntryNode(),
504 Op.getOperand(0), FI, DAG.getSrcValue(0));
505 LD = DAG.getLoad(MVT::f64, ST, FI, DAG.getSrcValue(0));
507 SDOperand FP = DAG.getNode(isDouble?AlphaISD::CVTQT_:AlphaISD::CVTQS_,
508 isDouble?MVT::f64:MVT::f32, LD);
511 case ISD::FP_TO_SINT: {
512 bool isDouble = MVT::f64 == Op.getOperand(0).getValueType();
513 SDOperand src = Op.getOperand(0);
515 if (!isDouble) //Promote
516 src = DAG.getNode(ISD::FP_EXTEND, MVT::f64, src);
518 src = DAG.getNode(AlphaISD::CVTTQ_, MVT::f64, src);
521 return DAG.getNode(AlphaISD::FTOIT_, MVT::i64, src);
524 DAG.getMachineFunction().getFrameInfo()->CreateStackObject(8, 8);
525 SDOperand FI = DAG.getFrameIndex(FrameIdx, MVT::i64);
526 SDOperand ST = DAG.getNode(ISD::STORE, MVT::Other, DAG.getEntryNode(),
527 src, FI, DAG.getSrcValue(0));
528 return DAG.getLoad(MVT::i64, ST, FI, DAG.getSrcValue(0));
531 case ISD::ConstantPool: {
532 Constant *C = cast<ConstantPoolSDNode>(Op)->get();
533 SDOperand CPI = DAG.getTargetConstantPool(C, MVT::i64);
535 SDOperand Hi = DAG.getNode(AlphaISD::GPRelHi, MVT::i64, CPI,
536 DAG.getNode(AlphaISD::GlobalBaseReg, MVT::i64));
537 SDOperand Lo = DAG.getNode(AlphaISD::GPRelLo, MVT::i64, CPI, Hi);
540 case ISD::GlobalAddress: {
541 GlobalAddressSDNode *GSDN = cast<GlobalAddressSDNode>(Op);
542 GlobalValue *GV = GSDN->getGlobal();
543 SDOperand GA = DAG.getTargetGlobalAddress(GV, MVT::i64, GSDN->getOffset());
545 if (!GV->hasWeakLinkage() && !GV->isExternal()) {
546 SDOperand Hi = DAG.getNode(AlphaISD::GPRelHi, MVT::i64, GA,
547 DAG.getNode(AlphaISD::GlobalBaseReg, MVT::i64));
548 SDOperand Lo = DAG.getNode(AlphaISD::GPRelLo, MVT::i64, GA, Hi);
551 return DAG.getNode(AlphaISD::RelLit, MVT::i64, GA, DAG.getNode(AlphaISD::GlobalBaseReg, MVT::i64));
553 case ISD::ExternalSymbol: {
554 return DAG.getNode(AlphaISD::RelLit, MVT::i64,
555 DAG.getTargetExternalSymbol(cast<ExternalSymbolSDNode>(Op)->getSymbol(), MVT::i64),
556 DAG.getNode(AlphaISD::GlobalBaseReg, MVT::i64));
563 if (MVT::isInteger(Op.getValueType())) {
564 const char* opstr = 0;
565 switch(Op.getOpcode()) {
566 case ISD::UREM: opstr = "__remqu"; break;
567 case ISD::SREM: opstr = "__remq"; break;
568 case ISD::UDIV: opstr = "__divqu"; break;
569 case ISD::SDIV: opstr = "__divq"; break;
571 SDOperand Tmp1 = Op.getOperand(0),
572 Tmp2 = Op.getOperand(1),
573 Addr = DAG.getExternalSymbol(opstr, MVT::i64);
574 return DAG.getNode(AlphaISD::DivCall, MVT::i64, Addr, Tmp1, Tmp2);
582 SDOperand Chain = Op.getOperand(0);
583 SDOperand Address = Op.getOperand(1);
586 unsigned opcode = Op.getOpcode();
588 if (opcode == ISD::LOAD)
589 switch (Op.Val->getValueType(0)) {
590 default: Op.Val->dump(); assert(0 && "Bad load!");
591 case MVT::i64: Opc = AlphaISD::LDQ_; break;
592 case MVT::f64: Opc = AlphaISD::LDT_; break;
593 case MVT::f32: Opc = AlphaISD::LDS_; break;
596 switch (cast<VTSDNode>(Op.getOperand(3))->getVT()) {
597 default: Op.Val->dump(); assert(0 && "Bad sign extend!");
598 case MVT::i32: Opc = AlphaISD::LDL_;
599 assert(opcode != ISD::ZEXTLOAD && "Not sext"); break;
600 case MVT::i16: Opc = AlphaISD::LDWU_;
601 assert(opcode != ISD::SEXTLOAD && "Not zext"); break;
602 case MVT::i1: //FIXME: Treat i1 as i8 since there are problems otherwise
603 case MVT::i8: Opc = AlphaISD::LDBU_;
604 assert(opcode != ISD::SEXTLOAD && "Not zext"); break;
608 getValueInfo(dyn_cast<SrcValueSDNode>(Op.getOperand(2))->getValue(), i, j, k);
610 SDOperand Zero = DAG.getConstant(0, MVT::i64);
611 std::vector<MVT::ValueType> VTS;
612 VTS.push_back(Op.Val->getValueType(0));
613 VTS.push_back(MVT::Other);
614 std::vector<SDOperand> ARGS;
615 ARGS.push_back(Zero);
616 ARGS.push_back(Address);
617 ARGS.push_back(DAG.getConstant(i, MVT::i64));
618 ARGS.push_back(DAG.getConstant(j, MVT::i64));
619 ARGS.push_back(DAG.getConstant(k, MVT::i64));
620 ARGS.push_back(DAG.getConstant(getUID(), MVT::i64));
621 ARGS.push_back(Chain);
622 return DAG.getNode(Opc, VTS, ARGS);