1 //===-- AlphaISelLowering.cpp - Alpha DAG Lowering Implementation ---------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file implements the AlphaISelLowering class.
12 //===----------------------------------------------------------------------===//
14 #include "AlphaISelLowering.h"
15 #include "AlphaTargetMachine.h"
16 #include "llvm/CodeGen/MachineFrameInfo.h"
17 #include "llvm/CodeGen/MachineFunction.h"
18 #include "llvm/CodeGen/MachineInstrBuilder.h"
19 #include "llvm/CodeGen/MachineRegisterInfo.h"
20 #include "llvm/CodeGen/SelectionDAG.h"
21 #include "llvm/CodeGen/MachineRegisterInfo.h"
22 #include "llvm/Constants.h"
23 #include "llvm/Function.h"
24 #include "llvm/Module.h"
25 #include "llvm/Intrinsics.h"
26 #include "llvm/Support/CommandLine.h"
29 /// AddLiveIn - This helper function adds the specified physical register to the
30 /// MachineFunction as a live in value. It also creates a corresponding virtual
32 static unsigned AddLiveIn(MachineFunction &MF, unsigned PReg,
33 TargetRegisterClass *RC) {
34 assert(RC->contains(PReg) && "Not the correct regclass!");
35 unsigned VReg = MF.getRegInfo().createVirtualRegister(RC);
36 MF.getRegInfo().addLiveIn(PReg, VReg);
40 AlphaTargetLowering::AlphaTargetLowering(TargetMachine &TM) : TargetLowering(TM) {
41 // Set up the TargetLowering object.
42 //I am having problems with shr n ubyte 1
43 setShiftAmountType(MVT::i64);
44 setSetCCResultContents(ZeroOrOneSetCCResult);
46 setUsesGlobalOffsetTable(true);
48 addRegisterClass(MVT::i64, Alpha::GPRCRegisterClass);
49 addRegisterClass(MVT::f64, Alpha::F8RCRegisterClass);
50 addRegisterClass(MVT::f32, Alpha::F4RCRegisterClass);
52 // We want to custom lower some of our intrinsics.
53 setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::Other, Custom);
55 setLoadXAction(ISD::EXTLOAD, MVT::i1, Promote);
56 setLoadXAction(ISD::EXTLOAD, MVT::f32, Expand);
58 setLoadXAction(ISD::ZEXTLOAD, MVT::i1, Promote);
59 setLoadXAction(ISD::ZEXTLOAD, MVT::i32, Expand);
61 setLoadXAction(ISD::SEXTLOAD, MVT::i1, Promote);
62 setLoadXAction(ISD::SEXTLOAD, MVT::i8, Expand);
63 setLoadXAction(ISD::SEXTLOAD, MVT::i16, Expand);
65 // setOperationAction(ISD::BRIND, MVT::Other, Expand);
66 setOperationAction(ISD::BR_JT, MVT::Other, Expand);
67 setOperationAction(ISD::BR_CC, MVT::Other, Expand);
68 setOperationAction(ISD::SELECT_CC, MVT::Other, Expand);
70 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1, Expand);
72 setOperationAction(ISD::FREM, MVT::f32, Expand);
73 setOperationAction(ISD::FREM, MVT::f64, Expand);
75 setOperationAction(ISD::UINT_TO_FP, MVT::i64, Expand);
76 setOperationAction(ISD::SINT_TO_FP, MVT::i64, Custom);
77 setOperationAction(ISD::FP_TO_UINT, MVT::i64, Expand);
78 setOperationAction(ISD::FP_TO_SINT, MVT::i64, Custom);
80 if (!TM.getSubtarget<AlphaSubtarget>().hasCT()) {
81 setOperationAction(ISD::CTPOP , MVT::i64 , Expand);
82 setOperationAction(ISD::CTTZ , MVT::i64 , Expand);
83 setOperationAction(ISD::CTLZ , MVT::i64 , Expand);
85 setOperationAction(ISD::BSWAP , MVT::i64, Expand);
86 setOperationAction(ISD::ROTL , MVT::i64, Expand);
87 setOperationAction(ISD::ROTR , MVT::i64, Expand);
89 setOperationAction(ISD::SREM , MVT::i64, Custom);
90 setOperationAction(ISD::UREM , MVT::i64, Custom);
91 setOperationAction(ISD::SDIV , MVT::i64, Custom);
92 setOperationAction(ISD::UDIV , MVT::i64, Custom);
94 setOperationAction(ISD::ADDC , MVT::i64, Expand);
95 setOperationAction(ISD::ADDE , MVT::i64, Expand);
96 setOperationAction(ISD::SUBC , MVT::i64, Expand);
97 setOperationAction(ISD::SUBE , MVT::i64, Expand);
99 setOperationAction(ISD::UMUL_LOHI, MVT::i64, Expand);
102 // We don't support sin/cos/sqrt/pow
103 setOperationAction(ISD::FSIN , MVT::f64, Expand);
104 setOperationAction(ISD::FCOS , MVT::f64, Expand);
105 setOperationAction(ISD::FSIN , MVT::f32, Expand);
106 setOperationAction(ISD::FCOS , MVT::f32, Expand);
108 setOperationAction(ISD::FSQRT, MVT::f64, Expand);
109 setOperationAction(ISD::FSQRT, MVT::f32, Expand);
111 setOperationAction(ISD::FPOW , MVT::f32, Expand);
112 setOperationAction(ISD::FPOW , MVT::f64, Expand);
114 setOperationAction(ISD::SETCC, MVT::f32, Promote);
116 setOperationAction(ISD::BIT_CONVERT, MVT::f32, Promote);
118 // We don't have line number support yet.
119 setOperationAction(ISD::DBG_STOPPOINT, MVT::Other, Expand);
120 setOperationAction(ISD::DEBUG_LOC, MVT::Other, Expand);
121 setOperationAction(ISD::DBG_LABEL, MVT::Other, Expand);
122 setOperationAction(ISD::EH_LABEL, MVT::Other, Expand);
124 // Not implemented yet.
125 setOperationAction(ISD::STACKSAVE, MVT::Other, Expand);
126 setOperationAction(ISD::STACKRESTORE, MVT::Other, Expand);
127 setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i64, Expand);
129 // We want to legalize GlobalAddress and ConstantPool and
130 // ExternalSymbols nodes into the appropriate instructions to
131 // materialize the address.
132 setOperationAction(ISD::GlobalAddress, MVT::i64, Custom);
133 setOperationAction(ISD::ConstantPool, MVT::i64, Custom);
134 setOperationAction(ISD::ExternalSymbol, MVT::i64, Custom);
135 setOperationAction(ISD::GlobalTLSAddress, MVT::i64, Custom);
137 setOperationAction(ISD::VASTART, MVT::Other, Custom);
138 setOperationAction(ISD::VAEND, MVT::Other, Expand);
139 setOperationAction(ISD::VACOPY, MVT::Other, Custom);
140 setOperationAction(ISD::VAARG, MVT::Other, Custom);
141 setOperationAction(ISD::VAARG, MVT::i32, Custom);
143 setOperationAction(ISD::RET, MVT::Other, Custom);
145 setOperationAction(ISD::JumpTable, MVT::i64, Custom);
146 setOperationAction(ISD::JumpTable, MVT::i32, Custom);
148 setStackPointerRegisterToSaveRestore(Alpha::R30);
150 addLegalFPImmediate(APFloat(+0.0)); //F31
151 addLegalFPImmediate(APFloat(+0.0f)); //F31
152 addLegalFPImmediate(APFloat(-0.0)); //-F31
153 addLegalFPImmediate(APFloat(-0.0f)); //-F31
156 setJumpBufAlignment(16);
158 computeRegisterProperties();
161 MVT AlphaTargetLowering::getSetCCResultType(const SDValue &) const {
165 const char *AlphaTargetLowering::getTargetNodeName(unsigned Opcode) const {
168 case AlphaISD::CVTQT_: return "Alpha::CVTQT_";
169 case AlphaISD::CVTQS_: return "Alpha::CVTQS_";
170 case AlphaISD::CVTTQ_: return "Alpha::CVTTQ_";
171 case AlphaISD::GPRelHi: return "Alpha::GPRelHi";
172 case AlphaISD::GPRelLo: return "Alpha::GPRelLo";
173 case AlphaISD::RelLit: return "Alpha::RelLit";
174 case AlphaISD::GlobalRetAddr: return "Alpha::GlobalRetAddr";
175 case AlphaISD::CALL: return "Alpha::CALL";
176 case AlphaISD::DivCall: return "Alpha::DivCall";
177 case AlphaISD::RET_FLAG: return "Alpha::RET_FLAG";
178 case AlphaISD::COND_BRANCH_I: return "Alpha::COND_BRANCH_I";
179 case AlphaISD::COND_BRANCH_F: return "Alpha::COND_BRANCH_F";
183 static SDValue LowerJumpTable(SDValue Op, SelectionDAG &DAG) {
184 MVT PtrVT = Op.getValueType();
185 JumpTableSDNode *JT = cast<JumpTableSDNode>(Op);
186 SDValue JTI = DAG.getTargetJumpTable(JT->getIndex(), PtrVT);
187 SDValue Zero = DAG.getConstant(0, PtrVT);
189 SDValue Hi = DAG.getNode(AlphaISD::GPRelHi, MVT::i64, JTI,
190 DAG.getNode(ISD::GLOBAL_OFFSET_TABLE, MVT::i64));
191 SDValue Lo = DAG.getNode(AlphaISD::GPRelLo, MVT::i64, JTI, Hi);
195 //http://www.cs.arizona.edu/computer.help/policy/DIGITAL_unix/
196 //AA-PY8AC-TET1_html/callCH3.html#BLOCK21
198 //For now, just use variable size stack frame format
200 //In a standard call, the first six items are passed in registers $16
201 //- $21 and/or registers $f16 - $f21. (See Section 4.1.2 for details
202 //of argument-to-register correspondence.) The remaining items are
203 //collected in a memory argument list that is a naturally aligned
204 //array of quadwords. In a standard call, this list, if present, must
205 //be passed at 0(SP).
206 //7 ... n 0(SP) ... (n-7)*8(SP)
214 static SDValue LowerFORMAL_ARGUMENTS(SDValue Op, SelectionDAG &DAG,
216 int &VarArgsOffset) {
217 MachineFunction &MF = DAG.getMachineFunction();
218 MachineFrameInfo *MFI = MF.getFrameInfo();
219 std::vector<SDValue> ArgValues;
220 SDValue Root = Op.getOperand(0);
222 AddLiveIn(MF, Alpha::R29, &Alpha::GPRCRegClass); //GP
223 AddLiveIn(MF, Alpha::R26, &Alpha::GPRCRegClass); //RA
225 unsigned args_int[] = {
226 Alpha::R16, Alpha::R17, Alpha::R18, Alpha::R19, Alpha::R20, Alpha::R21};
227 unsigned args_float[] = {
228 Alpha::F16, Alpha::F17, Alpha::F18, Alpha::F19, Alpha::F20, Alpha::F21};
230 for (unsigned ArgNo = 0, e = Op.getNode()->getNumValues()-1; ArgNo != e; ++ArgNo) {
232 MVT ObjectVT = Op.getValue(ArgNo).getValueType();
236 switch (ObjectVT.getSimpleVT()) {
238 assert(false && "Invalid value type!");
240 args_float[ArgNo] = AddLiveIn(MF, args_float[ArgNo],
241 &Alpha::F8RCRegClass);
242 ArgVal = DAG.getCopyFromReg(Root, args_float[ArgNo], ObjectVT);
245 args_float[ArgNo] = AddLiveIn(MF, args_float[ArgNo],
246 &Alpha::F4RCRegClass);
247 ArgVal = DAG.getCopyFromReg(Root, args_float[ArgNo], ObjectVT);
250 args_int[ArgNo] = AddLiveIn(MF, args_int[ArgNo],
251 &Alpha::GPRCRegClass);
252 ArgVal = DAG.getCopyFromReg(Root, args_int[ArgNo], MVT::i64);
256 // Create the frame index object for this incoming parameter...
257 int FI = MFI->CreateFixedObject(8, 8 * (ArgNo - 6));
259 // Create the SelectionDAG nodes corresponding to a load
260 //from this parameter
261 SDValue FIN = DAG.getFrameIndex(FI, MVT::i64);
262 ArgVal = DAG.getLoad(ObjectVT, Root, FIN, NULL, 0);
264 ArgValues.push_back(ArgVal);
267 // If the functions takes variable number of arguments, copy all regs to stack
268 bool isVarArg = cast<ConstantSDNode>(Op.getOperand(2))->getZExtValue() != 0;
270 VarArgsOffset = (Op.getNode()->getNumValues()-1) * 8;
271 std::vector<SDValue> LS;
272 for (int i = 0; i < 6; ++i) {
273 if (TargetRegisterInfo::isPhysicalRegister(args_int[i]))
274 args_int[i] = AddLiveIn(MF, args_int[i], &Alpha::GPRCRegClass);
275 SDValue argt = DAG.getCopyFromReg(Root, args_int[i], MVT::i64);
276 int FI = MFI->CreateFixedObject(8, -8 * (6 - i));
277 if (i == 0) VarArgsBase = FI;
278 SDValue SDFI = DAG.getFrameIndex(FI, MVT::i64);
279 LS.push_back(DAG.getStore(Root, argt, SDFI, NULL, 0));
281 if (TargetRegisterInfo::isPhysicalRegister(args_float[i]))
282 args_float[i] = AddLiveIn(MF, args_float[i], &Alpha::F8RCRegClass);
283 argt = DAG.getCopyFromReg(Root, args_float[i], MVT::f64);
284 FI = MFI->CreateFixedObject(8, - 8 * (12 - i));
285 SDFI = DAG.getFrameIndex(FI, MVT::i64);
286 LS.push_back(DAG.getStore(Root, argt, SDFI, NULL, 0));
289 //Set up a token factor with all the stack traffic
290 Root = DAG.getNode(ISD::TokenFactor, MVT::Other, &LS[0], LS.size());
293 ArgValues.push_back(Root);
295 // Return the new list of results.
296 return DAG.getMergeValues(Op.getNode()->getVTList(), &ArgValues[0],
300 static SDValue LowerRET(SDValue Op, SelectionDAG &DAG) {
301 SDValue Copy = DAG.getCopyToReg(Op.getOperand(0), Alpha::R26,
302 DAG.getNode(AlphaISD::GlobalRetAddr,
305 switch (Op.getNumOperands()) {
307 assert(0 && "Do not know how to return this many arguments!");
311 //return SDValue(); // ret void is legal
313 MVT ArgVT = Op.getOperand(1).getValueType();
315 if (ArgVT.isInteger())
318 assert(ArgVT.isFloatingPoint());
321 Copy = DAG.getCopyToReg(Copy, ArgReg, Op.getOperand(1), Copy.getValue(1));
322 if (DAG.getMachineFunction().getRegInfo().liveout_empty())
323 DAG.getMachineFunction().getRegInfo().addLiveOut(ArgReg);
327 MVT ArgVT = Op.getOperand(1).getValueType();
328 unsigned ArgReg1, ArgReg2;
329 if (ArgVT.isInteger()) {
333 assert(ArgVT.isFloatingPoint());
337 Copy = DAG.getCopyToReg(Copy, ArgReg1, Op.getOperand(1), Copy.getValue(1));
338 if (std::find(DAG.getMachineFunction().getRegInfo().liveout_begin(),
339 DAG.getMachineFunction().getRegInfo().liveout_end(), ArgReg1)
340 == DAG.getMachineFunction().getRegInfo().liveout_end())
341 DAG.getMachineFunction().getRegInfo().addLiveOut(ArgReg1);
342 Copy = DAG.getCopyToReg(Copy, ArgReg2, Op.getOperand(3), Copy.getValue(1));
343 if (std::find(DAG.getMachineFunction().getRegInfo().liveout_begin(),
344 DAG.getMachineFunction().getRegInfo().liveout_end(), ArgReg2)
345 == DAG.getMachineFunction().getRegInfo().liveout_end())
346 DAG.getMachineFunction().getRegInfo().addLiveOut(ArgReg2);
350 return DAG.getNode(AlphaISD::RET_FLAG, MVT::Other, Copy, Copy.getValue(1));
353 std::pair<SDValue, SDValue>
354 AlphaTargetLowering::LowerCallTo(SDValue Chain, const Type *RetTy,
355 bool RetSExt, bool RetZExt, bool isVarArg,
356 bool isInreg, unsigned CallingConv,
357 bool isTailCall, SDValue Callee,
358 ArgListTy &Args, SelectionDAG &DAG) {
361 NumBytes = (Args.size() - 6) * 8;
363 Chain = DAG.getCALLSEQ_START(Chain,
364 DAG.getConstant(NumBytes, getPointerTy()));
365 std::vector<SDValue> args_to_use;
366 for (unsigned i = 0, e = Args.size(); i != e; ++i)
368 switch (getValueType(Args[i].Ty).getSimpleVT()) {
369 default: assert(0 && "Unexpected ValueType for argument!");
374 // Promote the integer to 64 bits. If the input type is signed use a
375 // sign extend, otherwise use a zero extend.
377 Args[i].Node = DAG.getNode(ISD::SIGN_EXTEND, MVT::i64, Args[i].Node);
378 else if (Args[i].isZExt)
379 Args[i].Node = DAG.getNode(ISD::ZERO_EXTEND, MVT::i64, Args[i].Node);
381 Args[i].Node = DAG.getNode(ISD::ANY_EXTEND, MVT::i64, Args[i].Node);
388 args_to_use.push_back(Args[i].Node);
391 std::vector<MVT> RetVals;
392 MVT RetTyVT = getValueType(RetTy);
393 MVT ActualRetTyVT = RetTyVT;
394 if (RetTyVT.getSimpleVT() >= MVT::i1 && RetTyVT.getSimpleVT() <= MVT::i32)
395 ActualRetTyVT = MVT::i64;
397 if (RetTyVT != MVT::isVoid)
398 RetVals.push_back(ActualRetTyVT);
399 RetVals.push_back(MVT::Other);
401 std::vector<SDValue> Ops;
402 Ops.push_back(Chain);
403 Ops.push_back(Callee);
404 Ops.insert(Ops.end(), args_to_use.begin(), args_to_use.end());
405 SDValue TheCall = DAG.getNode(AlphaISD::CALL, RetVals, &Ops[0], Ops.size());
406 Chain = TheCall.getValue(RetTyVT != MVT::isVoid);
407 Chain = DAG.getCALLSEQ_END(Chain,
408 DAG.getConstant(NumBytes, getPointerTy()),
409 DAG.getConstant(0, getPointerTy()),
411 SDValue RetVal = TheCall;
413 if (RetTyVT != ActualRetTyVT) {
414 ISD::NodeType AssertKind = ISD::DELETED_NODE;
416 AssertKind = ISD::AssertSext;
418 AssertKind = ISD::AssertZext;
420 if (AssertKind != ISD::DELETED_NODE)
421 RetVal = DAG.getNode(AssertKind, MVT::i64, RetVal,
422 DAG.getValueType(RetTyVT));
424 RetVal = DAG.getNode(ISD::TRUNCATE, RetTyVT, RetVal);
427 return std::make_pair(RetVal, Chain);
430 void AlphaTargetLowering::LowerVAARG(SDNode *N, SDValue &Chain,
431 SDValue &DataPtr, SelectionDAG &DAG) {
432 Chain = N->getOperand(0);
433 SDValue VAListP = N->getOperand(1);
434 const Value *VAListS = cast<SrcValueSDNode>(N->getOperand(2))->getValue();
436 SDValue Base = DAG.getLoad(MVT::i64, Chain, VAListP, VAListS, 0);
437 SDValue Tmp = DAG.getNode(ISD::ADD, MVT::i64, VAListP,
438 DAG.getConstant(8, MVT::i64));
439 SDValue Offset = DAG.getExtLoad(ISD::SEXTLOAD, MVT::i64, Base.getValue(1),
440 Tmp, NULL, 0, MVT::i32);
441 DataPtr = DAG.getNode(ISD::ADD, MVT::i64, Base, Offset);
442 if (N->getValueType(0).isFloatingPoint())
444 //if fp && Offset < 6*8, then subtract 6*8 from DataPtr
445 SDValue FPDataPtr = DAG.getNode(ISD::SUB, MVT::i64, DataPtr,
446 DAG.getConstant(8*6, MVT::i64));
447 SDValue CC = DAG.getSetCC(MVT::i64, Offset,
448 DAG.getConstant(8*6, MVT::i64), ISD::SETLT);
449 DataPtr = DAG.getNode(ISD::SELECT, MVT::i64, CC, FPDataPtr, DataPtr);
452 SDValue NewOffset = DAG.getNode(ISD::ADD, MVT::i64, Offset,
453 DAG.getConstant(8, MVT::i64));
454 Chain = DAG.getTruncStore(Offset.getValue(1), NewOffset, Tmp, NULL, 0,
458 /// LowerOperation - Provide custom lowering hooks for some operations.
460 SDValue AlphaTargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) {
461 switch (Op.getOpcode()) {
462 default: assert(0 && "Wasn't expecting to be able to lower this!");
463 case ISD::FORMAL_ARGUMENTS: return LowerFORMAL_ARGUMENTS(Op, DAG,
467 case ISD::RET: return LowerRET(Op,DAG);
468 case ISD::JumpTable: return LowerJumpTable(Op, DAG);
470 case ISD::INTRINSIC_WO_CHAIN: {
471 unsigned IntNo = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
473 default: break; // Don't custom lower most intrinsics.
474 case Intrinsic::alpha_umulh:
475 return DAG.getNode(ISD::MULHU, MVT::i64, Op.getOperand(1), Op.getOperand(2));
479 case ISD::SINT_TO_FP: {
480 assert(Op.getOperand(0).getValueType() == MVT::i64 &&
481 "Unhandled SINT_TO_FP type in custom expander!");
483 bool isDouble = Op.getValueType() == MVT::f64;
484 LD = DAG.getNode(ISD::BIT_CONVERT, MVT::f64, Op.getOperand(0));
485 SDValue FP = DAG.getNode(isDouble?AlphaISD::CVTQT_:AlphaISD::CVTQS_,
486 isDouble?MVT::f64:MVT::f32, LD);
489 case ISD::FP_TO_SINT: {
490 bool isDouble = Op.getOperand(0).getValueType() == MVT::f64;
491 SDValue src = Op.getOperand(0);
493 if (!isDouble) //Promote
494 src = DAG.getNode(ISD::FP_EXTEND, MVT::f64, src);
496 src = DAG.getNode(AlphaISD::CVTTQ_, MVT::f64, src);
498 return DAG.getNode(ISD::BIT_CONVERT, MVT::i64, src);
500 case ISD::ConstantPool: {
501 ConstantPoolSDNode *CP = cast<ConstantPoolSDNode>(Op);
502 Constant *C = CP->getConstVal();
503 SDValue CPI = DAG.getTargetConstantPool(C, MVT::i64, CP->getAlignment());
505 SDValue Hi = DAG.getNode(AlphaISD::GPRelHi, MVT::i64, CPI,
506 DAG.getNode(ISD::GLOBAL_OFFSET_TABLE, MVT::i64));
507 SDValue Lo = DAG.getNode(AlphaISD::GPRelLo, MVT::i64, CPI, Hi);
510 case ISD::GlobalTLSAddress:
511 assert(0 && "TLS not implemented for Alpha.");
512 case ISD::GlobalAddress: {
513 GlobalAddressSDNode *GSDN = cast<GlobalAddressSDNode>(Op);
514 GlobalValue *GV = GSDN->getGlobal();
515 SDValue GA = DAG.getTargetGlobalAddress(GV, MVT::i64, GSDN->getOffset());
517 // if (!GV->hasWeakLinkage() && !GV->isDeclaration() && !GV->hasLinkOnceLinkage()) {
518 if (GV->hasInternalLinkage()) {
519 SDValue Hi = DAG.getNode(AlphaISD::GPRelHi, MVT::i64, GA,
520 DAG.getNode(ISD::GLOBAL_OFFSET_TABLE, MVT::i64));
521 SDValue Lo = DAG.getNode(AlphaISD::GPRelLo, MVT::i64, GA, Hi);
524 return DAG.getNode(AlphaISD::RelLit, MVT::i64, GA,
525 DAG.getNode(ISD::GLOBAL_OFFSET_TABLE, MVT::i64));
527 case ISD::ExternalSymbol: {
528 return DAG.getNode(AlphaISD::RelLit, MVT::i64,
529 DAG.getTargetExternalSymbol(cast<ExternalSymbolSDNode>(Op)
530 ->getSymbol(), MVT::i64),
531 DAG.getNode(ISD::GLOBAL_OFFSET_TABLE, MVT::i64));
536 //Expand only on constant case
537 if (Op.getOperand(1).getOpcode() == ISD::Constant) {
538 MVT VT = Op.getNode()->getValueType(0);
539 SDValue Tmp1 = Op.getNode()->getOpcode() == ISD::UREM ?
540 BuildUDIV(Op.getNode(), DAG, NULL) :
541 BuildSDIV(Op.getNode(), DAG, NULL);
542 Tmp1 = DAG.getNode(ISD::MUL, VT, Tmp1, Op.getOperand(1));
543 Tmp1 = DAG.getNode(ISD::SUB, VT, Op.getOperand(0), Tmp1);
549 if (Op.getValueType().isInteger()) {
550 if (Op.getOperand(1).getOpcode() == ISD::Constant)
551 return Op.getOpcode() == ISD::SDIV ? BuildSDIV(Op.getNode(), DAG, NULL)
552 : BuildUDIV(Op.getNode(), DAG, NULL);
553 const char* opstr = 0;
554 switch (Op.getOpcode()) {
555 case ISD::UREM: opstr = "__remqu"; break;
556 case ISD::SREM: opstr = "__remq"; break;
557 case ISD::UDIV: opstr = "__divqu"; break;
558 case ISD::SDIV: opstr = "__divq"; break;
560 SDValue Tmp1 = Op.getOperand(0),
561 Tmp2 = Op.getOperand(1),
562 Addr = DAG.getExternalSymbol(opstr, MVT::i64);
563 return DAG.getNode(AlphaISD::DivCall, MVT::i64, Addr, Tmp1, Tmp2);
568 SDValue Chain, DataPtr;
569 LowerVAARG(Op.getNode(), Chain, DataPtr, DAG);
572 if (Op.getValueType() == MVT::i32)
573 Result = DAG.getExtLoad(ISD::SEXTLOAD, MVT::i64, Chain, DataPtr,
576 Result = DAG.getLoad(Op.getValueType(), Chain, DataPtr, NULL, 0);
580 SDValue Chain = Op.getOperand(0);
581 SDValue DestP = Op.getOperand(1);
582 SDValue SrcP = Op.getOperand(2);
583 const Value *DestS = cast<SrcValueSDNode>(Op.getOperand(3))->getValue();
584 const Value *SrcS = cast<SrcValueSDNode>(Op.getOperand(4))->getValue();
586 SDValue Val = DAG.getLoad(getPointerTy(), Chain, SrcP, SrcS, 0);
587 SDValue Result = DAG.getStore(Val.getValue(1), Val, DestP, DestS, 0);
588 SDValue NP = DAG.getNode(ISD::ADD, MVT::i64, SrcP,
589 DAG.getConstant(8, MVT::i64));
590 Val = DAG.getExtLoad(ISD::SEXTLOAD, MVT::i64, Result, NP, NULL,0, MVT::i32);
591 SDValue NPD = DAG.getNode(ISD::ADD, MVT::i64, DestP,
592 DAG.getConstant(8, MVT::i64));
593 return DAG.getTruncStore(Val.getValue(1), Val, NPD, NULL, 0, MVT::i32);
596 SDValue Chain = Op.getOperand(0);
597 SDValue VAListP = Op.getOperand(1);
598 const Value *VAListS = cast<SrcValueSDNode>(Op.getOperand(2))->getValue();
600 // vastart stores the address of the VarArgsBase and VarArgsOffset
601 SDValue FR = DAG.getFrameIndex(VarArgsBase, MVT::i64);
602 SDValue S1 = DAG.getStore(Chain, FR, VAListP, VAListS, 0);
603 SDValue SA2 = DAG.getNode(ISD::ADD, MVT::i64, VAListP,
604 DAG.getConstant(8, MVT::i64));
605 return DAG.getTruncStore(S1, DAG.getConstant(VarArgsOffset, MVT::i64),
606 SA2, NULL, 0, MVT::i32);
608 case ISD::RETURNADDR:
609 return DAG.getNode(AlphaISD::GlobalRetAddr, MVT::i64);
611 case ISD::FRAMEADDR: break;
617 SDNode *AlphaTargetLowering::ReplaceNodeResults(SDNode *N,
619 assert(N->getValueType(0) == MVT::i32 &&
620 N->getOpcode() == ISD::VAARG &&
621 "Unknown node to custom promote!");
623 SDValue Chain, DataPtr;
624 LowerVAARG(N, Chain, DataPtr, DAG);
625 return DAG.getLoad(N->getValueType(0), Chain, DataPtr, NULL, 0).getNode();
631 /// getConstraintType - Given a constraint letter, return the type of
632 /// constraint it is for this target.
633 AlphaTargetLowering::ConstraintType
634 AlphaTargetLowering::getConstraintType(const std::string &Constraint) const {
635 if (Constraint.size() == 1) {
636 switch (Constraint[0]) {
640 return C_RegisterClass;
643 return TargetLowering::getConstraintType(Constraint);
646 std::vector<unsigned> AlphaTargetLowering::
647 getRegClassForInlineAsmConstraint(const std::string &Constraint,
649 if (Constraint.size() == 1) {
650 switch (Constraint[0]) {
651 default: break; // Unknown constriant letter
653 return make_vector<unsigned>(Alpha::F0 , Alpha::F1 , Alpha::F2 ,
654 Alpha::F3 , Alpha::F4 , Alpha::F5 ,
655 Alpha::F6 , Alpha::F7 , Alpha::F8 ,
656 Alpha::F9 , Alpha::F10, Alpha::F11,
657 Alpha::F12, Alpha::F13, Alpha::F14,
658 Alpha::F15, Alpha::F16, Alpha::F17,
659 Alpha::F18, Alpha::F19, Alpha::F20,
660 Alpha::F21, Alpha::F22, Alpha::F23,
661 Alpha::F24, Alpha::F25, Alpha::F26,
662 Alpha::F27, Alpha::F28, Alpha::F29,
663 Alpha::F30, Alpha::F31, 0);
665 return make_vector<unsigned>(Alpha::R0 , Alpha::R1 , Alpha::R2 ,
666 Alpha::R3 , Alpha::R4 , Alpha::R5 ,
667 Alpha::R6 , Alpha::R7 , Alpha::R8 ,
668 Alpha::R9 , Alpha::R10, Alpha::R11,
669 Alpha::R12, Alpha::R13, Alpha::R14,
670 Alpha::R15, Alpha::R16, Alpha::R17,
671 Alpha::R18, Alpha::R19, Alpha::R20,
672 Alpha::R21, Alpha::R22, Alpha::R23,
673 Alpha::R24, Alpha::R25, Alpha::R26,
674 Alpha::R27, Alpha::R28, Alpha::R29,
675 Alpha::R30, Alpha::R31, 0);
679 return std::vector<unsigned>();
681 //===----------------------------------------------------------------------===//
682 // Other Lowering Code
683 //===----------------------------------------------------------------------===//
686 AlphaTargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI,
687 MachineBasicBlock *BB) {
688 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
689 assert((MI->getOpcode() == Alpha::CAS32 ||
690 MI->getOpcode() == Alpha::CAS64 ||
691 MI->getOpcode() == Alpha::LAS32 ||
692 MI->getOpcode() == Alpha::LAS64 ||
693 MI->getOpcode() == Alpha::SWAP32 ||
694 MI->getOpcode() == Alpha::SWAP64) &&
695 "Unexpected instr type to insert");
697 bool is32 = MI->getOpcode() == Alpha::CAS32 ||
698 MI->getOpcode() == Alpha::LAS32 ||
699 MI->getOpcode() == Alpha::SWAP32;
701 //Load locked store conditional for atomic ops take on the same form
704 //do stuff (maybe branch to exit)
706 //test sc and maybe branck to start
708 const BasicBlock *LLVM_BB = BB->getBasicBlock();
709 MachineFunction::iterator It = BB;
712 MachineBasicBlock *thisMBB = BB;
713 MachineFunction *F = BB->getParent();
714 MachineBasicBlock *llscMBB = F->CreateMachineBasicBlock(LLVM_BB);
715 MachineBasicBlock *sinkMBB = F->CreateMachineBasicBlock(LLVM_BB);
717 sinkMBB->transferSuccessors(thisMBB);
719 F->insert(It, llscMBB);
720 F->insert(It, sinkMBB);
722 BuildMI(thisMBB, TII->get(Alpha::BR)).addMBB(llscMBB);
724 unsigned reg_res = MI->getOperand(0).getReg(),
725 reg_ptr = MI->getOperand(1).getReg(),
726 reg_v2 = MI->getOperand(2).getReg(),
727 reg_store = F->getRegInfo().createVirtualRegister(&Alpha::GPRCRegClass);
729 BuildMI(llscMBB, TII->get(is32 ? Alpha::LDL_L : Alpha::LDQ_L),
730 reg_res).addImm(0).addReg(reg_ptr);
731 switch (MI->getOpcode()) {
735 = F->getRegInfo().createVirtualRegister(&Alpha::GPRCRegClass);
736 BuildMI(llscMBB, TII->get(Alpha::CMPEQ), reg_cmp)
737 .addReg(reg_v2).addReg(reg_res);
738 BuildMI(llscMBB, TII->get(Alpha::BEQ))
739 .addImm(0).addReg(reg_cmp).addMBB(sinkMBB);
740 BuildMI(llscMBB, TII->get(Alpha::BISr), reg_store)
741 .addReg(Alpha::R31).addReg(MI->getOperand(3).getReg());
746 BuildMI(llscMBB, TII->get(is32 ? Alpha::ADDLr : Alpha::ADDQr), reg_store)
747 .addReg(reg_res).addReg(reg_v2);
751 case Alpha::SWAP64: {
752 BuildMI(llscMBB, TII->get(Alpha::BISr), reg_store)
753 .addReg(reg_v2).addReg(reg_v2);
757 BuildMI(llscMBB, TII->get(is32 ? Alpha::STL_C : Alpha::STQ_C), reg_store)
758 .addReg(reg_store).addImm(0).addReg(reg_ptr);
759 BuildMI(llscMBB, TII->get(Alpha::BEQ))
760 .addImm(0).addReg(reg_store).addMBB(llscMBB);
761 BuildMI(llscMBB, TII->get(Alpha::BR)).addMBB(sinkMBB);
763 thisMBB->addSuccessor(llscMBB);
764 llscMBB->addSuccessor(llscMBB);
765 llscMBB->addSuccessor(sinkMBB);
766 F->DeleteMachineInstr(MI); // The pseudo instruction is gone now.