1 //===-- AlphaISelLowering.cpp - Alpha DAG Lowering Implementation ---------===//
3 // The LLVM Compiler Infrastructure
5 // This file was developed by Andrew Lenharth and is distributed under
6 // the University of Illinois Open Source License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file implements the AlphaISelLowering class.
12 //===----------------------------------------------------------------------===//
14 #include "AlphaISelLowering.h"
15 #include "AlphaTargetMachine.h"
16 #include "llvm/CodeGen/MachineFrameInfo.h"
17 #include "llvm/CodeGen/MachineFunction.h"
18 #include "llvm/CodeGen/MachineInstrBuilder.h"
19 #include "llvm/CodeGen/SelectionDAG.h"
20 #include "llvm/CodeGen/SSARegMap.h"
21 #include "llvm/Constants.h"
22 #include "llvm/Function.h"
23 #include "llvm/Module.h"
24 #include "llvm/Support/CommandLine.h"
29 /// AddLiveIn - This helper function adds the specified physical register to the
30 /// MachineFunction as a live in value. It also creates a corresponding virtual
32 static unsigned AddLiveIn(MachineFunction &MF, unsigned PReg,
33 TargetRegisterClass *RC) {
34 assert(RC->contains(PReg) && "Not the correct regclass!");
35 unsigned VReg = MF.getSSARegMap()->createVirtualRegister(RC);
36 MF.addLiveIn(PReg, VReg);
40 AlphaTargetLowering::AlphaTargetLowering(TargetMachine &TM) : TargetLowering(TM) {
41 // Set up the TargetLowering object.
42 //I am having problems with shr n ubyte 1
43 setShiftAmountType(MVT::i64);
44 setSetCCResultType(MVT::i64);
45 setSetCCResultContents(ZeroOrOneSetCCResult);
47 addRegisterClass(MVT::i64, Alpha::GPRCRegisterClass);
48 addRegisterClass(MVT::f64, Alpha::F8RCRegisterClass);
49 addRegisterClass(MVT::f32, Alpha::F4RCRegisterClass);
51 setOperationAction(ISD::BRIND, MVT::i64, Expand);
52 setOperationAction(ISD::BR_CC, MVT::Other, Expand);
53 setOperationAction(ISD::SELECT_CC, MVT::Other, Expand);
55 setOperationAction(ISD::EXTLOAD, MVT::i1, Promote);
56 setOperationAction(ISD::EXTLOAD, MVT::f32, Expand);
58 setOperationAction(ISD::ZEXTLOAD, MVT::i1, Promote);
59 setOperationAction(ISD::ZEXTLOAD, MVT::i32, Expand);
61 setOperationAction(ISD::SEXTLOAD, MVT::i1, Promote);
62 setOperationAction(ISD::SEXTLOAD, MVT::i8, Expand);
63 setOperationAction(ISD::SEXTLOAD, MVT::i16, Expand);
65 setOperationAction(ISD::TRUNCSTORE, MVT::i1, Promote);
67 setOperationAction(ISD::FREM, MVT::f32, Expand);
68 setOperationAction(ISD::FREM, MVT::f64, Expand);
70 setOperationAction(ISD::UINT_TO_FP, MVT::i64, Expand);
71 setOperationAction(ISD::SINT_TO_FP, MVT::i64, Custom);
72 setOperationAction(ISD::FP_TO_UINT, MVT::i64, Expand);
73 setOperationAction(ISD::FP_TO_SINT, MVT::i64, Custom);
75 if (!TM.getSubtarget<AlphaSubtarget>().hasCT()) {
76 setOperationAction(ISD::CTPOP , MVT::i64 , Expand);
77 setOperationAction(ISD::CTTZ , MVT::i64 , Expand);
78 setOperationAction(ISD::CTLZ , MVT::i64 , Expand);
80 setOperationAction(ISD::BSWAP , MVT::i64, Expand);
81 setOperationAction(ISD::ROTL , MVT::i64, Expand);
82 setOperationAction(ISD::ROTR , MVT::i64, Expand);
84 setOperationAction(ISD::SREM , MVT::i64, Custom);
85 setOperationAction(ISD::UREM , MVT::i64, Custom);
86 setOperationAction(ISD::SDIV , MVT::i64, Custom);
87 setOperationAction(ISD::UDIV , MVT::i64, Custom);
89 setOperationAction(ISD::MEMMOVE , MVT::Other, Expand);
90 setOperationAction(ISD::MEMSET , MVT::Other, Expand);
91 setOperationAction(ISD::MEMCPY , MVT::Other, Expand);
93 // We don't support sin/cos/sqrt
94 setOperationAction(ISD::FSIN , MVT::f64, Expand);
95 setOperationAction(ISD::FCOS , MVT::f64, Expand);
96 setOperationAction(ISD::FSIN , MVT::f32, Expand);
97 setOperationAction(ISD::FCOS , MVT::f32, Expand);
99 setOperationAction(ISD::FSQRT, MVT::f64, Expand);
100 setOperationAction(ISD::FSQRT, MVT::f32, Expand);
102 // FIXME: Alpha supports fcopysign natively!?
103 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Expand);
104 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Expand);
106 setOperationAction(ISD::SETCC, MVT::f32, Promote);
108 // We don't have line number support yet.
109 setOperationAction(ISD::LOCATION, MVT::Other, Expand);
110 setOperationAction(ISD::DEBUG_LOC, MVT::Other, Expand);
111 setOperationAction(ISD::DEBUG_LABEL, MVT::Other, Expand);
113 // Not implemented yet.
114 setOperationAction(ISD::STACKSAVE, MVT::Other, Expand);
115 setOperationAction(ISD::STACKRESTORE, MVT::Other, Expand);
116 setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i64, Expand);
118 // We want to legalize GlobalAddress and ConstantPool and
119 // ExternalSymbols nodes into the appropriate instructions to
120 // materialize the address.
121 setOperationAction(ISD::GlobalAddress, MVT::i64, Custom);
122 setOperationAction(ISD::ConstantPool, MVT::i64, Custom);
123 setOperationAction(ISD::ExternalSymbol, MVT::i64, Custom);
125 setOperationAction(ISD::VASTART, MVT::Other, Custom);
126 setOperationAction(ISD::VAEND, MVT::Other, Expand);
127 setOperationAction(ISD::VACOPY, MVT::Other, Custom);
128 setOperationAction(ISD::VAARG, MVT::Other, Custom);
129 setOperationAction(ISD::VAARG, MVT::i32, Custom);
131 setOperationAction(ISD::RET, MVT::Other, Custom);
133 setStackPointerRegisterToSaveRestore(Alpha::R30);
135 setOperationAction(ISD::ConstantFP, MVT::f64, Expand);
136 setOperationAction(ISD::ConstantFP, MVT::f32, Expand);
137 addLegalFPImmediate(+0.0); //F31
138 addLegalFPImmediate(-0.0); //-F31
140 computeRegisterProperties();
142 useITOF = TM.getSubtarget<AlphaSubtarget>().hasF2I();
145 const char *AlphaTargetLowering::getTargetNodeName(unsigned Opcode) const {
148 case AlphaISD::ITOFT_: return "Alpha::ITOFT_";
149 case AlphaISD::FTOIT_: return "Alpha::FTOIT_";
150 case AlphaISD::CVTQT_: return "Alpha::CVTQT_";
151 case AlphaISD::CVTQS_: return "Alpha::CVTQS_";
152 case AlphaISD::CVTTQ_: return "Alpha::CVTTQ_";
153 case AlphaISD::GPRelHi: return "Alpha::GPRelHi";
154 case AlphaISD::GPRelLo: return "Alpha::GPRelLo";
155 case AlphaISD::RelLit: return "Alpha::RelLit";
156 case AlphaISD::GlobalBaseReg: return "Alpha::GlobalBaseReg";
157 case AlphaISD::GlobalRetAddr: return "Alpha::GlobalRetAddr";
158 case AlphaISD::CALL: return "Alpha::CALL";
159 case AlphaISD::DivCall: return "Alpha::DivCall";
160 case AlphaISD::RET_FLAG: return "Alpha::RET_FLAG";
164 //http://www.cs.arizona.edu/computer.help/policy/DIGITAL_unix/AA-PY8AC-TET1_html/callCH3.html#BLOCK21
166 //For now, just use variable size stack frame format
168 //In a standard call, the first six items are passed in registers $16
169 //- $21 and/or registers $f16 - $f21. (See Section 4.1.2 for details
170 //of argument-to-register correspondence.) The remaining items are
171 //collected in a memory argument list that is a naturally aligned
172 //array of quadwords. In a standard call, this list, if present, must
173 //be passed at 0(SP).
174 //7 ... n 0(SP) ... (n-7)*8(SP)
182 static SDOperand LowerFORMAL_ARGUMENTS(SDOperand Op, SelectionDAG &DAG,
187 MachineFunction &MF = DAG.getMachineFunction();
188 MachineFrameInfo *MFI = MF.getFrameInfo();
189 SSARegMap *RegMap = MF.getSSARegMap();
190 std::vector<SDOperand> ArgValues;
191 SDOperand Root = Op.getOperand(0);
193 GP = AddLiveIn(MF, Alpha::R29, &Alpha::GPRCRegClass);
194 RA = AddLiveIn(MF, Alpha::R26, &Alpha::GPRCRegClass);
196 unsigned args_int[] = {
197 Alpha::R16, Alpha::R17, Alpha::R18, Alpha::R19, Alpha::R20, Alpha::R21};
198 unsigned args_float[] = {
199 Alpha::F16, Alpha::F17, Alpha::F18, Alpha::F19, Alpha::F20, Alpha::F21};
201 for (unsigned ArgNo = 0, e = Op.Val->getNumValues()-1; ArgNo != e; ++ArgNo) {
203 MVT::ValueType ObjectVT = Op.getValue(ArgNo).getValueType();
210 std::cerr << "Unknown Type " << ObjectVT << "\n";
214 args_float[ArgNo] = AddLiveIn(MF, args_float[ArgNo],
215 &Alpha::F8RCRegClass);
216 ArgVal = DAG.getCopyFromReg(Root, args_float[ArgNo], ObjectVT);
219 args_int[ArgNo] = AddLiveIn(MF, args_int[ArgNo],
220 &Alpha::GPRCRegClass);
221 ArgVal = DAG.getCopyFromReg(Root, args_int[ArgNo], MVT::i64);
225 // Create the frame index object for this incoming parameter...
226 int FI = MFI->CreateFixedObject(8, 8 * (ArgNo - 6));
228 // Create the SelectionDAG nodes corresponding to a load
229 //from this parameter
230 SDOperand FIN = DAG.getFrameIndex(FI, MVT::i64);
231 ArgVal = DAG.getLoad(ObjectVT, Root, FIN, DAG.getSrcValue(NULL));
233 ArgValues.push_back(ArgVal);
236 // If the functions takes variable number of arguments, copy all regs to stack
237 bool isVarArg = cast<ConstantSDNode>(Op.getOperand(2))->getValue() != 0;
239 VarArgsOffset = (Op.Val->getNumValues()-1) * 8;
240 std::vector<SDOperand> LS;
241 for (int i = 0; i < 6; ++i) {
242 if (MRegisterInfo::isPhysicalRegister(args_int[i]))
243 args_int[i] = AddLiveIn(MF, args_int[i], &Alpha::GPRCRegClass);
244 SDOperand argt = DAG.getCopyFromReg(Root, args_int[i], MVT::i64);
245 int FI = MFI->CreateFixedObject(8, -8 * (6 - i));
246 if (i == 0) VarArgsBase = FI;
247 SDOperand SDFI = DAG.getFrameIndex(FI, MVT::i64);
248 LS.push_back(DAG.getNode(ISD::STORE, MVT::Other, Root, argt,
249 SDFI, DAG.getSrcValue(NULL)));
251 if (MRegisterInfo::isPhysicalRegister(args_float[i]))
252 args_float[i] = AddLiveIn(MF, args_float[i], &Alpha::F8RCRegClass);
253 argt = DAG.getCopyFromReg(Root, args_float[i], MVT::f64);
254 FI = MFI->CreateFixedObject(8, - 8 * (12 - i));
255 SDFI = DAG.getFrameIndex(FI, MVT::i64);
256 LS.push_back(DAG.getNode(ISD::STORE, MVT::Other, Root, argt,
257 SDFI, DAG.getSrcValue(NULL)));
260 //Set up a token factor with all the stack traffic
261 Root = DAG.getNode(ISD::TokenFactor, MVT::Other, LS);
264 ArgValues.push_back(Root);
266 // Return the new list of results.
267 std::vector<MVT::ValueType> RetVT(Op.Val->value_begin(),
268 Op.Val->value_end());
269 return DAG.getNode(ISD::MERGE_VALUES, RetVT, ArgValues);
272 static SDOperand LowerRET(SDOperand Op, SelectionDAG &DAG, unsigned int RA) {
273 SDOperand Copy = DAG.getCopyToReg(Op.getOperand(0), Alpha::R26,
274 DAG.getNode(AlphaISD::GlobalRetAddr, MVT::i64),
276 switch (Op.getNumOperands()) {
278 assert(0 && "Do not know how to return this many arguments!");
282 //return SDOperand(); // ret void is legal
284 MVT::ValueType ArgVT = Op.getOperand(1).getValueType();
286 if (MVT::isInteger(ArgVT))
289 assert(MVT::isFloatingPoint(ArgVT));
292 Copy = DAG.getCopyToReg(Copy, ArgReg, Op.getOperand(1), Copy.getValue(1));
293 if(DAG.getMachineFunction().liveout_empty())
294 DAG.getMachineFunction().addLiveOut(ArgReg);
298 return DAG.getNode(AlphaISD::RET_FLAG, MVT::Other, Copy, Copy.getValue(1));
301 std::pair<SDOperand, SDOperand>
302 AlphaTargetLowering::LowerCallTo(SDOperand Chain,
303 const Type *RetTy, bool isVarArg,
304 unsigned CallingConv, bool isTailCall,
305 SDOperand Callee, ArgListTy &Args,
309 NumBytes = (Args.size() - 6) * 8;
311 Chain = DAG.getCALLSEQ_START(Chain,
312 DAG.getConstant(NumBytes, getPointerTy()));
313 std::vector<SDOperand> args_to_use;
314 for (unsigned i = 0, e = Args.size(); i != e; ++i)
316 switch (getValueType(Args[i].second)) {
317 default: assert(0 && "Unexpected ValueType for argument!");
322 // Promote the integer to 64 bits. If the input type is signed use a
323 // sign extend, otherwise use a zero extend.
324 if (Args[i].second->isSigned())
325 Args[i].first = DAG.getNode(ISD::SIGN_EXTEND, MVT::i64, Args[i].first);
327 Args[i].first = DAG.getNode(ISD::ZERO_EXTEND, MVT::i64, Args[i].first);
334 args_to_use.push_back(Args[i].first);
337 std::vector<MVT::ValueType> RetVals;
338 MVT::ValueType RetTyVT = getValueType(RetTy);
339 MVT::ValueType ActualRetTyVT = RetTyVT;
340 if (RetTyVT >= MVT::i1 && RetTyVT <= MVT::i32)
341 ActualRetTyVT = MVT::i64;
343 if (RetTyVT != MVT::isVoid)
344 RetVals.push_back(ActualRetTyVT);
345 RetVals.push_back(MVT::Other);
347 std::vector<SDOperand> Ops;
348 Ops.push_back(Chain);
349 Ops.push_back(Callee);
350 Ops.insert(Ops.end(), args_to_use.begin(), args_to_use.end());
351 SDOperand TheCall = DAG.getNode(AlphaISD::CALL, RetVals, Ops);
352 Chain = TheCall.getValue(RetTyVT != MVT::isVoid);
353 Chain = DAG.getNode(ISD::CALLSEQ_END, MVT::Other, Chain,
354 DAG.getConstant(NumBytes, getPointerTy()));
355 SDOperand RetVal = TheCall;
357 if (RetTyVT != ActualRetTyVT) {
358 RetVal = DAG.getNode(RetTy->isSigned() ? ISD::AssertSext : ISD::AssertZext,
359 MVT::i64, RetVal, DAG.getValueType(RetTyVT));
360 RetVal = DAG.getNode(ISD::TRUNCATE, RetTyVT, RetVal);
363 return std::make_pair(RetVal, Chain);
366 void AlphaTargetLowering::restoreGP(MachineBasicBlock* BB)
368 BuildMI(BB, Alpha::BIS, 2, Alpha::R29).addReg(GP).addReg(GP);
370 void AlphaTargetLowering::restoreRA(MachineBasicBlock* BB)
372 BuildMI(BB, Alpha::BIS, 2, Alpha::R26).addReg(RA).addReg(RA);
381 /// LowerOperation - Provide custom lowering hooks for some operations.
383 SDOperand AlphaTargetLowering::LowerOperation(SDOperand Op, SelectionDAG &DAG) {
384 switch (Op.getOpcode()) {
385 default: assert(0 && "Wasn't expecting to be able to lower this!");
386 case ISD::FORMAL_ARGUMENTS: return LowerFORMAL_ARGUMENTS(Op, DAG,
390 case ISD::RET: return LowerRET(Op,DAG, getVRegRA());
391 case ISD::SINT_TO_FP: {
392 assert(MVT::i64 == Op.getOperand(0).getValueType() &&
393 "Unhandled SINT_TO_FP type in custom expander!");
395 bool isDouble = MVT::f64 == Op.getValueType();
397 LD = DAG.getNode(AlphaISD::ITOFT_, MVT::f64, Op.getOperand(0));
400 DAG.getMachineFunction().getFrameInfo()->CreateStackObject(8, 8);
401 SDOperand FI = DAG.getFrameIndex(FrameIdx, MVT::i64);
402 SDOperand ST = DAG.getNode(ISD::STORE, MVT::Other, DAG.getEntryNode(),
403 Op.getOperand(0), FI, DAG.getSrcValue(0));
404 LD = DAG.getLoad(MVT::f64, ST, FI, DAG.getSrcValue(0));
406 SDOperand FP = DAG.getNode(isDouble?AlphaISD::CVTQT_:AlphaISD::CVTQS_,
407 isDouble?MVT::f64:MVT::f32, LD);
410 case ISD::FP_TO_SINT: {
411 bool isDouble = MVT::f64 == Op.getOperand(0).getValueType();
412 SDOperand src = Op.getOperand(0);
414 if (!isDouble) //Promote
415 src = DAG.getNode(ISD::FP_EXTEND, MVT::f64, src);
417 src = DAG.getNode(AlphaISD::CVTTQ_, MVT::f64, src);
420 return DAG.getNode(AlphaISD::FTOIT_, MVT::i64, src);
423 DAG.getMachineFunction().getFrameInfo()->CreateStackObject(8, 8);
424 SDOperand FI = DAG.getFrameIndex(FrameIdx, MVT::i64);
425 SDOperand ST = DAG.getNode(ISD::STORE, MVT::Other, DAG.getEntryNode(),
426 src, FI, DAG.getSrcValue(0));
427 return DAG.getLoad(MVT::i64, ST, FI, DAG.getSrcValue(0));
430 case ISD::ConstantPool: {
431 ConstantPoolSDNode *CP = cast<ConstantPoolSDNode>(Op);
432 Constant *C = CP->get();
433 SDOperand CPI = DAG.getTargetConstantPool(C, MVT::i64, CP->getAlignment());
435 SDOperand Hi = DAG.getNode(AlphaISD::GPRelHi, MVT::i64, CPI,
436 DAG.getNode(AlphaISD::GlobalBaseReg, MVT::i64));
437 SDOperand Lo = DAG.getNode(AlphaISD::GPRelLo, MVT::i64, CPI, Hi);
440 case ISD::GlobalAddress: {
441 GlobalAddressSDNode *GSDN = cast<GlobalAddressSDNode>(Op);
442 GlobalValue *GV = GSDN->getGlobal();
443 SDOperand GA = DAG.getTargetGlobalAddress(GV, MVT::i64, GSDN->getOffset());
445 // if (!GV->hasWeakLinkage() && !GV->isExternal() && !GV->hasLinkOnceLinkage()) {
446 if (GV->hasInternalLinkage()) {
447 SDOperand Hi = DAG.getNode(AlphaISD::GPRelHi, MVT::i64, GA,
448 DAG.getNode(AlphaISD::GlobalBaseReg, MVT::i64));
449 SDOperand Lo = DAG.getNode(AlphaISD::GPRelLo, MVT::i64, GA, Hi);
452 return DAG.getNode(AlphaISD::RelLit, MVT::i64, GA, DAG.getNode(AlphaISD::GlobalBaseReg, MVT::i64));
454 case ISD::ExternalSymbol: {
455 return DAG.getNode(AlphaISD::RelLit, MVT::i64,
456 DAG.getTargetExternalSymbol(cast<ExternalSymbolSDNode>(Op)->getSymbol(), MVT::i64),
457 DAG.getNode(AlphaISD::GlobalBaseReg, MVT::i64));
462 //Expand only on constant case
463 if (Op.getOperand(1).getOpcode() == ISD::Constant) {
464 MVT::ValueType VT = Op.Val->getValueType(0);
465 unsigned Opc = Op.Val->getOpcode() == ISD::UREM ? ISD::UDIV : ISD::SDIV;
466 SDOperand Tmp1 = Op.Val->getOpcode() == ISD::UREM ?
467 BuildUDIV(Op.Val, DAG, NULL) :
468 BuildSDIV(Op.Val, DAG, NULL);
469 Tmp1 = DAG.getNode(ISD::MUL, VT, Tmp1, Op.getOperand(1));
470 Tmp1 = DAG.getNode(ISD::SUB, VT, Op.getOperand(0), Tmp1);
476 if (MVT::isInteger(Op.getValueType())) {
477 if (Op.getOperand(1).getOpcode() == ISD::Constant)
478 return Op.getOpcode() == ISD::SDIV ? BuildSDIV(Op.Val, DAG, NULL)
479 : BuildUDIV(Op.Val, DAG, NULL);
480 const char* opstr = 0;
481 switch(Op.getOpcode()) {
482 case ISD::UREM: opstr = "__remqu"; break;
483 case ISD::SREM: opstr = "__remq"; break;
484 case ISD::UDIV: opstr = "__divqu"; break;
485 case ISD::SDIV: opstr = "__divq"; break;
487 SDOperand Tmp1 = Op.getOperand(0),
488 Tmp2 = Op.getOperand(1),
489 Addr = DAG.getExternalSymbol(opstr, MVT::i64);
490 return DAG.getNode(AlphaISD::DivCall, MVT::i64, Addr, Tmp1, Tmp2);
495 SDOperand Chain = Op.getOperand(0);
496 SDOperand VAListP = Op.getOperand(1);
497 SDOperand VAListS = Op.getOperand(2);
499 SDOperand Base = DAG.getLoad(MVT::i64, Chain, VAListP, VAListS);
500 SDOperand Tmp = DAG.getNode(ISD::ADD, MVT::i64, VAListP,
501 DAG.getConstant(8, MVT::i64));
502 SDOperand Offset = DAG.getExtLoad(ISD::SEXTLOAD, MVT::i64, Base.getValue(1),
503 Tmp, DAG.getSrcValue(0), MVT::i32);
504 SDOperand DataPtr = DAG.getNode(ISD::ADD, MVT::i64, Base, Offset);
505 if (MVT::isFloatingPoint(Op.getValueType()))
507 //if fp && Offset < 6*8, then subtract 6*8 from DataPtr
508 SDOperand FPDataPtr = DAG.getNode(ISD::SUB, MVT::i64, DataPtr,
509 DAG.getConstant(8*6, MVT::i64));
510 SDOperand CC = DAG.getSetCC(MVT::i64, Offset,
511 DAG.getConstant(8*6, MVT::i64), ISD::SETLT);
512 DataPtr = DAG.getNode(ISD::SELECT, MVT::i64, CC, FPDataPtr, DataPtr);
515 SDOperand NewOffset = DAG.getNode(ISD::ADD, MVT::i64, Offset,
516 DAG.getConstant(8, MVT::i64));
517 SDOperand Update = DAG.getNode(ISD::TRUNCSTORE, MVT::Other,
518 Offset.getValue(1), NewOffset,
519 Tmp, DAG.getSrcValue(0),
520 DAG.getValueType(MVT::i32));
523 if (Op.getValueType() == MVT::i32)
524 Result = DAG.getExtLoad(ISD::SEXTLOAD, MVT::i64, Update, DataPtr,
525 DAG.getSrcValue(0), MVT::i32);
527 Result = DAG.getLoad(Op.getValueType(), Update, DataPtr,
532 SDOperand Chain = Op.getOperand(0);
533 SDOperand DestP = Op.getOperand(1);
534 SDOperand SrcP = Op.getOperand(2);
535 SDOperand DestS = Op.getOperand(3);
536 SDOperand SrcS = Op.getOperand(4);
538 SDOperand Val = DAG.getLoad(getPointerTy(), Chain, SrcP, SrcS);
539 SDOperand Result = DAG.getNode(ISD::STORE, MVT::Other, Val.getValue(1), Val,
541 SDOperand NP = DAG.getNode(ISD::ADD, MVT::i64, SrcP,
542 DAG.getConstant(8, MVT::i64));
543 Val = DAG.getExtLoad(ISD::SEXTLOAD, MVT::i64, Result, NP,
544 DAG.getSrcValue(0), MVT::i32);
545 SDOperand NPD = DAG.getNode(ISD::ADD, MVT::i64, DestP,
546 DAG.getConstant(8, MVT::i64));
547 return DAG.getNode(ISD::TRUNCSTORE, MVT::Other, Val.getValue(1),
548 Val, NPD, DAG.getSrcValue(0),DAG.getValueType(MVT::i32));
551 SDOperand Chain = Op.getOperand(0);
552 SDOperand VAListP = Op.getOperand(1);
553 SDOperand VAListS = Op.getOperand(2);
555 // vastart stores the address of the VarArgsBase and VarArgsOffset
556 SDOperand FR = DAG.getFrameIndex(VarArgsBase, MVT::i64);
557 SDOperand S1 = DAG.getNode(ISD::STORE, MVT::Other, Chain, FR, VAListP,
559 SDOperand SA2 = DAG.getNode(ISD::ADD, MVT::i64, VAListP,
560 DAG.getConstant(8, MVT::i64));
561 return DAG.getNode(ISD::TRUNCSTORE, MVT::Other, S1,
562 DAG.getConstant(VarArgsOffset, MVT::i64), SA2,
563 DAG.getSrcValue(0), DAG.getValueType(MVT::i32));
570 SDOperand AlphaTargetLowering::CustomPromoteOperation(SDOperand Op,
572 assert(Op.getValueType() == MVT::i32 &&
573 Op.getOpcode() == ISD::VAARG &&
574 "Unknown node to custom promote!");
576 // The code in LowerOperation already handles i32 vaarg
577 return LowerOperation(Op, DAG);