1 //===-- AlphaISelLowering.cpp - Alpha DAG Lowering Implementation ---------===//
3 // The LLVM Compiler Infrastructure
5 // This file was developed by Andrew Lenharth and is distributed under
6 // the University of Illinois Open Source License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file implements the AlphaISelLowering class.
12 //===----------------------------------------------------------------------===//
14 #include "AlphaISelLowering.h"
15 #include "AlphaTargetMachine.h"
16 #include "llvm/CodeGen/MachineFrameInfo.h"
17 #include "llvm/CodeGen/MachineFunction.h"
18 #include "llvm/CodeGen/MachineInstrBuilder.h"
19 #include "llvm/CodeGen/SelectionDAG.h"
20 #include "llvm/CodeGen/SSARegMap.h"
21 #include "llvm/Constants.h"
22 #include "llvm/Function.h"
23 #include "llvm/Support/CommandLine.h"
29 extern cl::opt<bool> EnableAlphaIDIV;
30 extern cl::opt<bool> EnableAlphaCount;
31 extern cl::opt<bool> EnableAlphaLSMark;
34 /// AddLiveIn - This helper function adds the specified physical register to the
35 /// MachineFunction as a live in value. It also creates a corresponding virtual
37 static unsigned AddLiveIn(MachineFunction &MF, unsigned PReg,
38 TargetRegisterClass *RC) {
39 assert(RC->contains(PReg) && "Not the correct regclass!");
40 unsigned VReg = MF.getSSARegMap()->createVirtualRegister(RC);
41 MF.addLiveIn(PReg, VReg);
45 AlphaTargetLowering::AlphaTargetLowering(TargetMachine &TM) : TargetLowering(TM) {
46 // Set up the TargetLowering object.
47 //I am having problems with shr n ubyte 1
48 setShiftAmountType(MVT::i64);
49 setSetCCResultType(MVT::i64);
50 setSetCCResultContents(ZeroOrOneSetCCResult);
52 addRegisterClass(MVT::i64, Alpha::GPRCRegisterClass);
53 addRegisterClass(MVT::f64, Alpha::F8RCRegisterClass);
54 addRegisterClass(MVT::f32, Alpha::F4RCRegisterClass);
56 setOperationAction(ISD::BRCONDTWOWAY, MVT::Other, Expand);
57 setOperationAction(ISD::BRTWOWAY_CC, MVT::Other, Expand);
59 setOperationAction(ISD::EXTLOAD, MVT::i1, Promote);
60 setOperationAction(ISD::EXTLOAD, MVT::f32, Expand);
62 setOperationAction(ISD::ZEXTLOAD, MVT::i1, Promote);
63 setOperationAction(ISD::ZEXTLOAD, MVT::i32, Expand);
65 setOperationAction(ISD::SEXTLOAD, MVT::i1, Promote);
66 setOperationAction(ISD::SEXTLOAD, MVT::i8, Expand);
67 setOperationAction(ISD::SEXTLOAD, MVT::i16, Expand);
69 setOperationAction(ISD::TRUNCSTORE, MVT::i1, Promote);
71 setOperationAction(ISD::FREM, MVT::f32, Expand);
72 setOperationAction(ISD::FREM, MVT::f64, Expand);
74 setOperationAction(ISD::UINT_TO_FP, MVT::i64, Expand);
75 setOperationAction(ISD::SINT_TO_FP, MVT::i64, Custom);
76 setOperationAction(ISD::FP_TO_UINT, MVT::i64, Expand);
77 setOperationAction(ISD::FP_TO_SINT, MVT::i64, Custom);
79 if (!TM.getSubtarget<AlphaSubtarget>().hasCT()) {
80 setOperationAction(ISD::CTPOP , MVT::i64 , Expand);
81 setOperationAction(ISD::CTTZ , MVT::i64 , Expand);
82 setOperationAction(ISD::CTLZ , MVT::i64 , Expand);
85 //If this didn't legalize into a div....
86 // setOperationAction(ISD::SREM , MVT::i64, Expand);
87 // setOperationAction(ISD::UREM , MVT::i64, Expand);
89 setOperationAction(ISD::MEMMOVE , MVT::Other, Expand);
90 setOperationAction(ISD::MEMSET , MVT::Other, Expand);
91 setOperationAction(ISD::MEMCPY , MVT::Other, Expand);
93 // We don't support sin/cos/sqrt
94 setOperationAction(ISD::FSIN , MVT::f64, Expand);
95 setOperationAction(ISD::FCOS , MVT::f64, Expand);
96 setOperationAction(ISD::FSQRT, MVT::f64, Expand);
97 setOperationAction(ISD::FSIN , MVT::f32, Expand);
98 setOperationAction(ISD::FCOS , MVT::f32, Expand);
99 setOperationAction(ISD::FSQRT, MVT::f32, Expand);
101 setOperationAction(ISD::SETCC, MVT::f32, Promote);
103 // We don't have line number support yet.
104 setOperationAction(ISD::LOCATION, MVT::Other, Expand);
105 setOperationAction(ISD::DEBUG_LOC, MVT::Other, Expand);
107 // We want to legalize GlobalAddress and ConstantPool nodes into the
108 // appropriate instructions to materialize the address.
109 setOperationAction(ISD::GlobalAddress, MVT::i64, Custom);
110 setOperationAction(ISD::ConstantPool, MVT::i64, Custom);
112 addLegalFPImmediate(+0.0); //F31
113 addLegalFPImmediate(-0.0); //-F31
115 computeRegisterProperties();
117 useITOF = TM.getSubtarget<AlphaSubtarget>().hasF2I();
121 //http://www.cs.arizona.edu/computer.help/policy/DIGITAL_unix/AA-PY8AC-TET1_html/callCH3.html#BLOCK21
123 //For now, just use variable size stack frame format
125 //In a standard call, the first six items are passed in registers $16
126 //- $21 and/or registers $f16 - $f21. (See Section 4.1.2 for details
127 //of argument-to-register correspondence.) The remaining items are
128 //collected in a memory argument list that is a naturally aligned
129 //array of quadwords. In a standard call, this list, if present, must
130 //be passed at 0(SP).
131 //7 ... n 0(SP) ... (n-7)*8(SP)
139 std::vector<SDOperand>
140 AlphaTargetLowering::LowerArguments(Function &F, SelectionDAG &DAG)
142 MachineFunction &MF = DAG.getMachineFunction();
143 MachineFrameInfo *MFI = MF.getFrameInfo();
144 MachineBasicBlock& BB = MF.front();
145 std::vector<SDOperand> ArgValues;
147 unsigned args_int[] = {
148 Alpha::R16, Alpha::R17, Alpha::R18, Alpha::R19, Alpha::R20, Alpha::R21};
149 unsigned args_float[] = {
150 Alpha::F16, Alpha::F17, Alpha::F18, Alpha::F19, Alpha::F20, Alpha::F21};
154 GP = AddLiveIn(MF, Alpha::R29, getRegClassFor(MVT::i64));
155 RA = AddLiveIn(MF, Alpha::R26, getRegClassFor(MVT::i64));
157 for (Function::arg_iterator I = F.arg_begin(), E = F.arg_end(); I != E; ++I)
162 MVT::ValueType VT = getValueType(I->getType());
165 std::cerr << "Unknown Type " << VT << "\n";
169 args_float[count] = AddLiveIn(MF, args_float[count], getRegClassFor(VT));
170 argt = DAG.getCopyFromReg(DAG.getRoot(), args_float[count], VT);
171 DAG.setRoot(argt.getValue(1));
178 args_int[count] = AddLiveIn(MF, args_int[count], getRegClassFor(MVT::i64));
179 argt = DAG.getCopyFromReg(DAG.getRoot(), args_int[count], MVT::i64);
180 DAG.setRoot(argt.getValue(1));
181 if (VT != MVT::i64) {
183 I->getType()->isSigned() ? ISD::AssertSext : ISD::AssertZext;
184 argt = DAG.getNode(AssertOp, MVT::i64, argt,
185 DAG.getValueType(VT));
186 argt = DAG.getNode(ISD::TRUNCATE, VT, argt);
191 // Create the frame index object for this incoming parameter...
192 int FI = MFI->CreateFixedObject(8, 8 * (count - 6));
194 // Create the SelectionDAG nodes corresponding to a load
195 //from this parameter
196 SDOperand FIN = DAG.getFrameIndex(FI, MVT::i64);
197 argt = DAG.getLoad(getValueType(I->getType()),
198 DAG.getEntryNode(), FIN, DAG.getSrcValue(NULL));
201 ArgValues.push_back(argt);
204 // If the functions takes variable number of arguments, copy all regs to stack
206 VarArgsOffset = count * 8;
207 std::vector<SDOperand> LS;
208 for (int i = 0; i < 6; ++i) {
209 if (MRegisterInfo::isPhysicalRegister(args_int[i]))
210 args_int[i] = AddLiveIn(MF, args_int[i], getRegClassFor(MVT::i64));
211 SDOperand argt = DAG.getCopyFromReg(DAG.getRoot(), args_int[i], MVT::i64);
212 int FI = MFI->CreateFixedObject(8, -8 * (6 - i));
213 if (i == 0) VarArgsBase = FI;
214 SDOperand SDFI = DAG.getFrameIndex(FI, MVT::i64);
215 LS.push_back(DAG.getNode(ISD::STORE, MVT::Other, DAG.getRoot(), argt,
216 SDFI, DAG.getSrcValue(NULL)));
218 if (MRegisterInfo::isPhysicalRegister(args_float[i]))
219 args_float[i] = AddLiveIn(MF, args_float[i], getRegClassFor(MVT::f64));
220 argt = DAG.getCopyFromReg(DAG.getRoot(), args_float[i], MVT::f64);
221 FI = MFI->CreateFixedObject(8, - 8 * (12 - i));
222 SDFI = DAG.getFrameIndex(FI, MVT::i64);
223 LS.push_back(DAG.getNode(ISD::STORE, MVT::Other, DAG.getRoot(), argt,
224 SDFI, DAG.getSrcValue(NULL)));
227 //Set up a token factor with all the stack traffic
228 DAG.setRoot(DAG.getNode(ISD::TokenFactor, MVT::Other, LS));
231 // Finally, inform the code generator which regs we return values in.
232 switch (getValueType(F.getReturnType())) {
233 default: assert(0 && "Unknown type!");
234 case MVT::isVoid: break;
240 MF.addLiveOut(Alpha::R0);
244 MF.addLiveOut(Alpha::F0);
248 //return the arguments
252 std::pair<SDOperand, SDOperand>
253 AlphaTargetLowering::LowerCallTo(SDOperand Chain,
254 const Type *RetTy, bool isVarArg,
255 unsigned CallingConv, bool isTailCall,
256 SDOperand Callee, ArgListTy &Args,
260 NumBytes = (Args.size() - 6) * 8;
262 Chain = DAG.getNode(ISD::CALLSEQ_START, MVT::Other, Chain,
263 DAG.getConstant(NumBytes, getPointerTy()));
264 std::vector<SDOperand> args_to_use;
265 for (unsigned i = 0, e = Args.size(); i != e; ++i)
267 switch (getValueType(Args[i].second)) {
268 default: assert(0 && "Unexpected ValueType for argument!");
273 // Promote the integer to 64 bits. If the input type is signed use a
274 // sign extend, otherwise use a zero extend.
275 if (Args[i].second->isSigned())
276 Args[i].first = DAG.getNode(ISD::SIGN_EXTEND, MVT::i64, Args[i].first);
278 Args[i].first = DAG.getNode(ISD::ZERO_EXTEND, MVT::i64, Args[i].first);
285 args_to_use.push_back(Args[i].first);
288 std::vector<MVT::ValueType> RetVals;
289 MVT::ValueType RetTyVT = getValueType(RetTy);
290 MVT::ValueType ActualRetTyVT = RetTyVT;
291 if (RetTyVT >= MVT::i1 && RetTyVT <= MVT::i32)
292 ActualRetTyVT = MVT::i64;
294 if (RetTyVT != MVT::isVoid)
295 RetVals.push_back(ActualRetTyVT);
296 RetVals.push_back(MVT::Other);
298 SDOperand TheCall = SDOperand(DAG.getCall(RetVals,
299 Chain, Callee, args_to_use), 0);
300 Chain = TheCall.getValue(RetTyVT != MVT::isVoid);
301 Chain = DAG.getNode(ISD::CALLSEQ_END, MVT::Other, Chain,
302 DAG.getConstant(NumBytes, getPointerTy()));
303 SDOperand RetVal = TheCall;
305 if (RetTyVT != ActualRetTyVT) {
306 RetVal = DAG.getNode(RetTy->isSigned() ? ISD::AssertSext : ISD::AssertZext,
307 MVT::i64, RetVal, DAG.getValueType(RetTyVT));
308 RetVal = DAG.getNode(ISD::TRUNCATE, RetTyVT, RetVal);
311 return std::make_pair(RetVal, Chain);
314 SDOperand AlphaTargetLowering::LowerVAStart(SDOperand Chain, SDOperand VAListP,
315 Value *VAListV, SelectionDAG &DAG) {
316 // vastart stores the address of the VarArgsBase and VarArgsOffset
317 SDOperand FR = DAG.getFrameIndex(VarArgsBase, MVT::i64);
318 SDOperand S1 = DAG.getNode(ISD::STORE, MVT::Other, Chain, FR, VAListP,
319 DAG.getSrcValue(VAListV));
320 SDOperand SA2 = DAG.getNode(ISD::ADD, MVT::i64, VAListP,
321 DAG.getConstant(8, MVT::i64));
322 return DAG.getNode(ISD::TRUNCSTORE, MVT::Other, S1,
323 DAG.getConstant(VarArgsOffset, MVT::i64), SA2,
324 DAG.getSrcValue(VAListV, 8), DAG.getValueType(MVT::i32));
327 std::pair<SDOperand,SDOperand> AlphaTargetLowering::
328 LowerVAArg(SDOperand Chain, SDOperand VAListP, Value *VAListV,
329 const Type *ArgTy, SelectionDAG &DAG) {
330 SDOperand Base = DAG.getLoad(MVT::i64, Chain, VAListP,
331 DAG.getSrcValue(VAListV));
332 SDOperand Tmp = DAG.getNode(ISD::ADD, MVT::i64, VAListP,
333 DAG.getConstant(8, MVT::i64));
334 SDOperand Offset = DAG.getExtLoad(ISD::SEXTLOAD, MVT::i64, Base.getValue(1),
335 Tmp, DAG.getSrcValue(VAListV, 8), MVT::i32);
336 SDOperand DataPtr = DAG.getNode(ISD::ADD, MVT::i64, Base, Offset);
337 if (ArgTy->isFloatingPoint())
339 //if fp && Offset < 6*8, then subtract 6*8 from DataPtr
340 SDOperand FPDataPtr = DAG.getNode(ISD::SUB, MVT::i64, DataPtr,
341 DAG.getConstant(8*6, MVT::i64));
342 SDOperand CC = DAG.getSetCC(MVT::i64, Offset,
343 DAG.getConstant(8*6, MVT::i64), ISD::SETLT);
344 DataPtr = DAG.getNode(ISD::SELECT, MVT::i64, CC, FPDataPtr, DataPtr);
348 if (ArgTy == Type::IntTy)
349 Result = DAG.getExtLoad(ISD::SEXTLOAD, MVT::i64, Offset.getValue(1),
350 DataPtr, DAG.getSrcValue(NULL), MVT::i32);
351 else if (ArgTy == Type::UIntTy)
352 Result = DAG.getExtLoad(ISD::ZEXTLOAD, MVT::i64, Offset.getValue(1),
353 DataPtr, DAG.getSrcValue(NULL), MVT::i32);
355 Result = DAG.getLoad(getValueType(ArgTy), Offset.getValue(1), DataPtr,
356 DAG.getSrcValue(NULL));
358 SDOperand NewOffset = DAG.getNode(ISD::ADD, MVT::i64, Offset,
359 DAG.getConstant(8, MVT::i64));
360 SDOperand Update = DAG.getNode(ISD::TRUNCSTORE, MVT::Other,
361 Result.getValue(1), NewOffset,
362 Tmp, DAG.getSrcValue(VAListV, 8),
363 DAG.getValueType(MVT::i32));
364 Result = DAG.getNode(ISD::TRUNCATE, getValueType(ArgTy), Result);
366 return std::make_pair(Result, Update);
370 SDOperand AlphaTargetLowering::
371 LowerVACopy(SDOperand Chain, SDOperand SrcP, Value *SrcV, SDOperand DestP,
372 Value *DestV, SelectionDAG &DAG) {
373 SDOperand Val = DAG.getLoad(getPointerTy(), Chain, SrcP,
374 DAG.getSrcValue(SrcV));
375 SDOperand Result = DAG.getNode(ISD::STORE, MVT::Other, Val.getValue(1),
376 Val, DestP, DAG.getSrcValue(DestV));
377 SDOperand NP = DAG.getNode(ISD::ADD, MVT::i64, SrcP,
378 DAG.getConstant(8, MVT::i64));
379 Val = DAG.getExtLoad(ISD::SEXTLOAD, MVT::i64, Result, NP,
380 DAG.getSrcValue(SrcV, 8), MVT::i32);
381 SDOperand NPD = DAG.getNode(ISD::ADD, MVT::i64, DestP,
382 DAG.getConstant(8, MVT::i64));
383 return DAG.getNode(ISD::TRUNCSTORE, MVT::Other, Val.getValue(1),
384 Val, NPD, DAG.getSrcValue(DestV, 8),
385 DAG.getValueType(MVT::i32));
388 void AlphaTargetLowering::restoreGP(MachineBasicBlock* BB)
390 BuildMI(BB, Alpha::BIS, 2, Alpha::R29).addReg(GP).addReg(GP);
392 void AlphaTargetLowering::restoreRA(MachineBasicBlock* BB)
394 BuildMI(BB, Alpha::BIS, 2, Alpha::R26).addReg(RA).addReg(RA);
398 /// LowerOperation - Provide custom lowering hooks for some operations.
400 SDOperand AlphaTargetLowering::LowerOperation(SDOperand Op, SelectionDAG &DAG) {
401 switch (Op.getOpcode()) {
402 default: assert(0 && "Wasn't expecting to be able to lower this!");
403 case ISD::SINT_TO_FP: {
404 assert(MVT::i64 == Op.getOperand(0).getValueType() &&
405 "Unhandled SINT_TO_FP type in custom expander!");
407 bool isDouble = MVT::f64 == Op.getValueType();
409 LD = DAG.getNode(AlphaISD::ITOFT_, MVT::f64, Op.getOperand(0));
412 DAG.getMachineFunction().getFrameInfo()->CreateStackObject(8, 8);
413 SDOperand FI = DAG.getFrameIndex(FrameIdx, MVT::i64);
414 SDOperand ST = DAG.getNode(ISD::STORE, MVT::Other, DAG.getEntryNode(),
415 Op.getOperand(0), FI, DAG.getSrcValue(0));
416 LD = DAG.getLoad(MVT::f64, ST, FI, DAG.getSrcValue(0));
418 SDOperand FP = DAG.getNode(isDouble?AlphaISD::CVTQT_:AlphaISD::CVTQS_,
419 isDouble?MVT::f64:MVT::f32, LD);
422 case ISD::FP_TO_SINT: {
423 bool isDouble = MVT::f64 == Op.getOperand(0).getValueType();
424 SDOperand src = Op.getOperand(0);
426 if (!isDouble) //Promote
427 src = DAG.getNode(ISD::FP_EXTEND, MVT::f64, src);
429 src = DAG.getNode(AlphaISD::CVTTQ_, MVT::f64, src);
432 return DAG.getNode(AlphaISD::FTOIT_, MVT::i64, src);
435 DAG.getMachineFunction().getFrameInfo()->CreateStackObject(8, 8);
436 SDOperand FI = DAG.getFrameIndex(FrameIdx, MVT::i64);
437 SDOperand ST = DAG.getNode(ISD::STORE, MVT::Other, DAG.getEntryNode(),
438 src, FI, DAG.getSrcValue(0));
439 return DAG.getLoad(MVT::i64, ST, FI, DAG.getSrcValue(0));
442 case ISD::ConstantPool: {
443 Constant *C = cast<ConstantPoolSDNode>(Op)->get();
444 SDOperand CPI = DAG.getTargetConstantPool(C, MVT::i64);
446 SDOperand Hi = DAG.getNode(AlphaISD::GPRelHi, MVT::i64, CPI,
447 DAG.getNode(AlphaISD::GlobalBaseReg, MVT::i64));
448 SDOperand Lo = DAG.getNode(AlphaISD::GPRelLo, MVT::i64, CPI, Hi);
451 case ISD::GlobalAddress: {
452 GlobalAddressSDNode *GSDN = cast<GlobalAddressSDNode>(Op);
453 GlobalValue *GV = GSDN->getGlobal();
454 SDOperand GA = DAG.getTargetGlobalAddress(GV, MVT::i64, GSDN->getOffset());
456 if (!GV->hasWeakLinkage() && !GV->isExternal()) {
457 SDOperand Hi = DAG.getNode(AlphaISD::GPRelHi, MVT::i64, GA,
458 DAG.getNode(AlphaISD::GlobalBaseReg, MVT::i64));
459 SDOperand Lo = DAG.getNode(AlphaISD::GPRelLo, MVT::i64, GA, Hi);