1 //===-- AlphaISelLowering.cpp - Alpha DAG Lowering Implementation ---------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file implements the AlphaISelLowering class.
12 //===----------------------------------------------------------------------===//
14 #include "AlphaISelLowering.h"
15 #include "AlphaTargetMachine.h"
16 #include "llvm/CodeGen/CallingConvLower.h"
17 #include "llvm/CodeGen/MachineFrameInfo.h"
18 #include "llvm/CodeGen/MachineFunction.h"
19 #include "llvm/CodeGen/MachineInstrBuilder.h"
20 #include "llvm/CodeGen/MachineRegisterInfo.h"
21 #include "llvm/CodeGen/SelectionDAG.h"
22 #include "llvm/CodeGen/MachineRegisterInfo.h"
23 #include "llvm/CodeGen/PseudoSourceValue.h"
24 #include "llvm/Target/TargetLoweringObjectFile.h"
25 #include "llvm/Constants.h"
26 #include "llvm/Function.h"
27 #include "llvm/Module.h"
28 #include "llvm/Intrinsics.h"
29 #include "llvm/Support/CommandLine.h"
30 #include "llvm/Support/ErrorHandling.h"
31 #include "llvm/Support/raw_ostream.h"
34 /// AddLiveIn - This helper function adds the specified physical register to the
35 /// MachineFunction as a live in value. It also creates a corresponding virtual
37 static unsigned AddLiveIn(MachineFunction &MF, unsigned PReg,
38 TargetRegisterClass *RC) {
39 assert(RC->contains(PReg) && "Not the correct regclass!");
40 unsigned VReg = MF.getRegInfo().createVirtualRegister(RC);
41 MF.getRegInfo().addLiveIn(PReg, VReg);
45 AlphaTargetLowering::AlphaTargetLowering(TargetMachine &TM)
46 : TargetLowering(TM, new TargetLoweringObjectFileELF()) {
47 // Set up the TargetLowering object.
48 //I am having problems with shr n i8 1
49 setShiftAmountType(MVT::i64);
50 setBooleanContents(ZeroOrOneBooleanContent);
52 setUsesGlobalOffsetTable(true);
54 addRegisterClass(MVT::i64, Alpha::GPRCRegisterClass);
55 addRegisterClass(MVT::f64, Alpha::F8RCRegisterClass);
56 addRegisterClass(MVT::f32, Alpha::F4RCRegisterClass);
58 // We want to custom lower some of our intrinsics.
59 setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::Other, Custom);
61 setLoadExtAction(ISD::EXTLOAD, MVT::i1, Promote);
62 setLoadExtAction(ISD::EXTLOAD, MVT::f32, Expand);
64 setLoadExtAction(ISD::ZEXTLOAD, MVT::i1, Promote);
65 setLoadExtAction(ISD::ZEXTLOAD, MVT::i32, Expand);
67 setLoadExtAction(ISD::SEXTLOAD, MVT::i1, Promote);
68 setLoadExtAction(ISD::SEXTLOAD, MVT::i8, Expand);
69 setLoadExtAction(ISD::SEXTLOAD, MVT::i16, Expand);
71 setTruncStoreAction(MVT::f64, MVT::f32, Expand);
73 // setOperationAction(ISD::BRIND, MVT::Other, Expand);
74 setOperationAction(ISD::BR_JT, MVT::Other, Expand);
75 setOperationAction(ISD::BR_CC, MVT::Other, Expand);
76 setOperationAction(ISD::SELECT_CC, MVT::Other, Expand);
78 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1, Expand);
80 setOperationAction(ISD::FREM, MVT::f32, Expand);
81 setOperationAction(ISD::FREM, MVT::f64, Expand);
83 setOperationAction(ISD::UINT_TO_FP, MVT::i64, Expand);
84 setOperationAction(ISD::SINT_TO_FP, MVT::i64, Custom);
85 setOperationAction(ISD::FP_TO_UINT, MVT::i64, Expand);
86 setOperationAction(ISD::FP_TO_SINT, MVT::i64, Custom);
88 if (!TM.getSubtarget<AlphaSubtarget>().hasCT()) {
89 setOperationAction(ISD::CTPOP , MVT::i64 , Expand);
90 setOperationAction(ISD::CTTZ , MVT::i64 , Expand);
91 setOperationAction(ISD::CTLZ , MVT::i64 , Expand);
93 setOperationAction(ISD::BSWAP , MVT::i64, Expand);
94 setOperationAction(ISD::ROTL , MVT::i64, Expand);
95 setOperationAction(ISD::ROTR , MVT::i64, Expand);
97 setOperationAction(ISD::SREM , MVT::i64, Custom);
98 setOperationAction(ISD::UREM , MVT::i64, Custom);
99 setOperationAction(ISD::SDIV , MVT::i64, Custom);
100 setOperationAction(ISD::UDIV , MVT::i64, Custom);
102 setOperationAction(ISD::ADDC , MVT::i64, Expand);
103 setOperationAction(ISD::ADDE , MVT::i64, Expand);
104 setOperationAction(ISD::SUBC , MVT::i64, Expand);
105 setOperationAction(ISD::SUBE , MVT::i64, Expand);
107 setOperationAction(ISD::UMUL_LOHI, MVT::i64, Expand);
108 setOperationAction(ISD::SMUL_LOHI, MVT::i64, Expand);
110 setOperationAction(ISD::SRL_PARTS, MVT::i64, Custom);
111 setOperationAction(ISD::SRA_PARTS, MVT::i64, Expand);
112 setOperationAction(ISD::SHL_PARTS, MVT::i64, Expand);
114 // We don't support sin/cos/sqrt/pow
115 setOperationAction(ISD::FSIN , MVT::f64, Expand);
116 setOperationAction(ISD::FCOS , MVT::f64, Expand);
117 setOperationAction(ISD::FSIN , MVT::f32, Expand);
118 setOperationAction(ISD::FCOS , MVT::f32, Expand);
120 setOperationAction(ISD::FSQRT, MVT::f64, Expand);
121 setOperationAction(ISD::FSQRT, MVT::f32, Expand);
123 setOperationAction(ISD::FPOW , MVT::f32, Expand);
124 setOperationAction(ISD::FPOW , MVT::f64, Expand);
126 setOperationAction(ISD::SETCC, MVT::f32, Promote);
128 setOperationAction(ISD::BIT_CONVERT, MVT::f32, Promote);
130 setOperationAction(ISD::EH_LABEL, MVT::Other, Expand);
132 // Not implemented yet.
133 setOperationAction(ISD::STACKSAVE, MVT::Other, Expand);
134 setOperationAction(ISD::STACKRESTORE, MVT::Other, Expand);
135 setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i64, Expand);
137 // We want to legalize GlobalAddress and ConstantPool and
138 // ExternalSymbols nodes into the appropriate instructions to
139 // materialize the address.
140 setOperationAction(ISD::GlobalAddress, MVT::i64, Custom);
141 setOperationAction(ISD::ConstantPool, MVT::i64, Custom);
142 setOperationAction(ISD::ExternalSymbol, MVT::i64, Custom);
143 setOperationAction(ISD::GlobalTLSAddress, MVT::i64, Custom);
145 setOperationAction(ISD::VASTART, MVT::Other, Custom);
146 setOperationAction(ISD::VAEND, MVT::Other, Expand);
147 setOperationAction(ISD::VACOPY, MVT::Other, Custom);
148 setOperationAction(ISD::VAARG, MVT::Other, Custom);
149 setOperationAction(ISD::VAARG, MVT::i32, Custom);
151 setOperationAction(ISD::JumpTable, MVT::i64, Custom);
152 setOperationAction(ISD::JumpTable, MVT::i32, Custom);
154 setStackPointerRegisterToSaveRestore(Alpha::R30);
157 setJumpBufAlignment(16);
159 computeRegisterProperties();
162 MVT::SimpleValueType AlphaTargetLowering::getSetCCResultType(EVT VT) const {
166 const char *AlphaTargetLowering::getTargetNodeName(unsigned Opcode) const {
169 case AlphaISD::CVTQT_: return "Alpha::CVTQT_";
170 case AlphaISD::CVTQS_: return "Alpha::CVTQS_";
171 case AlphaISD::CVTTQ_: return "Alpha::CVTTQ_";
172 case AlphaISD::GPRelHi: return "Alpha::GPRelHi";
173 case AlphaISD::GPRelLo: return "Alpha::GPRelLo";
174 case AlphaISD::RelLit: return "Alpha::RelLit";
175 case AlphaISD::GlobalRetAddr: return "Alpha::GlobalRetAddr";
176 case AlphaISD::CALL: return "Alpha::CALL";
177 case AlphaISD::DivCall: return "Alpha::DivCall";
178 case AlphaISD::RET_FLAG: return "Alpha::RET_FLAG";
179 case AlphaISD::COND_BRANCH_I: return "Alpha::COND_BRANCH_I";
180 case AlphaISD::COND_BRANCH_F: return "Alpha::COND_BRANCH_F";
184 /// getFunctionAlignment - Return the Log2 alignment of this function.
185 unsigned AlphaTargetLowering::getFunctionAlignment(const Function *F) const {
189 static SDValue LowerJumpTable(SDValue Op, SelectionDAG &DAG) {
190 EVT PtrVT = Op.getValueType();
191 JumpTableSDNode *JT = cast<JumpTableSDNode>(Op);
192 SDValue JTI = DAG.getTargetJumpTable(JT->getIndex(), PtrVT);
193 SDValue Zero = DAG.getConstant(0, PtrVT);
194 // FIXME there isn't really any debug info here
195 DebugLoc dl = Op.getDebugLoc();
197 SDValue Hi = DAG.getNode(AlphaISD::GPRelHi, dl, MVT::i64, JTI,
198 DAG.getGLOBAL_OFFSET_TABLE(MVT::i64));
199 SDValue Lo = DAG.getNode(AlphaISD::GPRelLo, dl, MVT::i64, JTI, Hi);
203 //http://www.cs.arizona.edu/computer.help/policy/DIGITAL_unix/
204 //AA-PY8AC-TET1_html/callCH3.html#BLOCK21
206 //For now, just use variable size stack frame format
208 //In a standard call, the first six items are passed in registers $16
209 //- $21 and/or registers $f16 - $f21. (See Section 4.1.2 for details
210 //of argument-to-register correspondence.) The remaining items are
211 //collected in a memory argument list that is a naturally aligned
212 //array of quadwords. In a standard call, this list, if present, must
213 //be passed at 0(SP).
214 //7 ... n 0(SP) ... (n-7)*8(SP)
222 #include "AlphaGenCallingConv.inc"
225 AlphaTargetLowering::LowerCall(SDValue Chain, SDValue Callee,
226 CallingConv::ID CallConv, bool isVarArg,
228 const SmallVectorImpl<ISD::OutputArg> &Outs,
229 const SmallVectorImpl<ISD::InputArg> &Ins,
230 DebugLoc dl, SelectionDAG &DAG,
231 SmallVectorImpl<SDValue> &InVals) {
233 // Analyze operands of the call, assigning locations to each operand.
234 SmallVector<CCValAssign, 16> ArgLocs;
235 CCState CCInfo(CallConv, isVarArg, getTargetMachine(),
236 ArgLocs, *DAG.getContext());
238 CCInfo.AnalyzeCallOperands(Outs, CC_Alpha);
240 // Get a count of how many bytes are to be pushed on the stack.
241 unsigned NumBytes = CCInfo.getNextStackOffset();
243 Chain = DAG.getCALLSEQ_START(Chain, DAG.getConstant(NumBytes,
244 getPointerTy(), true));
246 SmallVector<std::pair<unsigned, SDValue>, 4> RegsToPass;
247 SmallVector<SDValue, 12> MemOpChains;
250 // Walk the register/memloc assignments, inserting copies/loads.
251 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
252 CCValAssign &VA = ArgLocs[i];
254 SDValue Arg = Outs[i].Val;
256 // Promote the value if needed.
257 switch (VA.getLocInfo()) {
258 default: assert(0 && "Unknown loc info!");
259 case CCValAssign::Full: break;
260 case CCValAssign::SExt:
261 Arg = DAG.getNode(ISD::SIGN_EXTEND, dl, VA.getLocVT(), Arg);
263 case CCValAssign::ZExt:
264 Arg = DAG.getNode(ISD::ZERO_EXTEND, dl, VA.getLocVT(), Arg);
266 case CCValAssign::AExt:
267 Arg = DAG.getNode(ISD::ANY_EXTEND, dl, VA.getLocVT(), Arg);
271 // Arguments that can be passed on register must be kept at RegsToPass
274 RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg));
276 assert(VA.isMemLoc());
278 if (StackPtr.getNode() == 0)
279 StackPtr = DAG.getCopyFromReg(Chain, dl, Alpha::R30, MVT::i64);
281 SDValue PtrOff = DAG.getNode(ISD::ADD, dl, getPointerTy(),
283 DAG.getIntPtrConstant(VA.getLocMemOffset()));
285 MemOpChains.push_back(DAG.getStore(Chain, dl, Arg, PtrOff,
286 PseudoSourceValue::getStack(), 0));
290 // Transform all store nodes into one single node because all store nodes are
291 // independent of each other.
292 if (!MemOpChains.empty())
293 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
294 &MemOpChains[0], MemOpChains.size());
296 // Build a sequence of copy-to-reg nodes chained together with token chain and
297 // flag operands which copy the outgoing args into registers. The InFlag in
298 // necessary since all emited instructions must be stuck together.
300 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) {
301 Chain = DAG.getCopyToReg(Chain, dl, RegsToPass[i].first,
302 RegsToPass[i].second, InFlag);
303 InFlag = Chain.getValue(1);
306 // Returns a chain & a flag for retval copy to use.
307 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Flag);
308 SmallVector<SDValue, 8> Ops;
309 Ops.push_back(Chain);
310 Ops.push_back(Callee);
312 // Add argument registers to the end of the list so that they are
313 // known live into the call.
314 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i)
315 Ops.push_back(DAG.getRegister(RegsToPass[i].first,
316 RegsToPass[i].second.getValueType()));
318 if (InFlag.getNode())
319 Ops.push_back(InFlag);
321 Chain = DAG.getNode(AlphaISD::CALL, dl, NodeTys, &Ops[0], Ops.size());
322 InFlag = Chain.getValue(1);
324 // Create the CALLSEQ_END node.
325 Chain = DAG.getCALLSEQ_END(Chain,
326 DAG.getConstant(NumBytes, getPointerTy(), true),
327 DAG.getConstant(0, getPointerTy(), true),
329 InFlag = Chain.getValue(1);
331 // Handle result values, copying them out of physregs into vregs that we
333 return LowerCallResult(Chain, InFlag, CallConv, isVarArg,
334 Ins, dl, DAG, InVals);
337 /// LowerCallResult - Lower the result values of a call into the
338 /// appropriate copies out of appropriate physical registers.
341 AlphaTargetLowering::LowerCallResult(SDValue Chain, SDValue InFlag,
342 CallingConv::ID CallConv, bool isVarArg,
343 const SmallVectorImpl<ISD::InputArg> &Ins,
344 DebugLoc dl, SelectionDAG &DAG,
345 SmallVectorImpl<SDValue> &InVals) {
347 // Assign locations to each value returned by this call.
348 SmallVector<CCValAssign, 16> RVLocs;
349 CCState CCInfo(CallConv, isVarArg, getTargetMachine(), RVLocs,
352 CCInfo.AnalyzeCallResult(Ins, RetCC_Alpha);
354 // Copy all of the result registers out of their specified physreg.
355 for (unsigned i = 0; i != RVLocs.size(); ++i) {
356 CCValAssign &VA = RVLocs[i];
358 Chain = DAG.getCopyFromReg(Chain, dl, VA.getLocReg(),
359 VA.getLocVT(), InFlag).getValue(1);
360 SDValue RetValue = Chain.getValue(0);
361 InFlag = Chain.getValue(2);
363 // If this is an 8/16/32-bit value, it is really passed promoted to 64
364 // bits. Insert an assert[sz]ext to capture this, then truncate to the
366 if (VA.getLocInfo() == CCValAssign::SExt)
367 RetValue = DAG.getNode(ISD::AssertSext, dl, VA.getLocVT(), RetValue,
368 DAG.getValueType(VA.getValVT()));
369 else if (VA.getLocInfo() == CCValAssign::ZExt)
370 RetValue = DAG.getNode(ISD::AssertZext, dl, VA.getLocVT(), RetValue,
371 DAG.getValueType(VA.getValVT()));
373 if (VA.getLocInfo() != CCValAssign::Full)
374 RetValue = DAG.getNode(ISD::TRUNCATE, dl, VA.getValVT(), RetValue);
376 InVals.push_back(RetValue);
383 AlphaTargetLowering::LowerFormalArguments(SDValue Chain,
384 CallingConv::ID CallConv, bool isVarArg,
385 const SmallVectorImpl<ISD::InputArg>
387 DebugLoc dl, SelectionDAG &DAG,
388 SmallVectorImpl<SDValue> &InVals) {
390 MachineFunction &MF = DAG.getMachineFunction();
391 MachineFrameInfo *MFI = MF.getFrameInfo();
393 unsigned args_int[] = {
394 Alpha::R16, Alpha::R17, Alpha::R18, Alpha::R19, Alpha::R20, Alpha::R21};
395 unsigned args_float[] = {
396 Alpha::F16, Alpha::F17, Alpha::F18, Alpha::F19, Alpha::F20, Alpha::F21};
398 for (unsigned ArgNo = 0, e = Ins.size(); ArgNo != e; ++ArgNo) {
400 EVT ObjectVT = Ins[ArgNo].VT;
404 switch (ObjectVT.getSimpleVT().SimpleTy) {
406 assert(false && "Invalid value type!");
408 args_float[ArgNo] = AddLiveIn(MF, args_float[ArgNo],
409 &Alpha::F8RCRegClass);
410 ArgVal = DAG.getCopyFromReg(Chain, dl, args_float[ArgNo], ObjectVT);
413 args_float[ArgNo] = AddLiveIn(MF, args_float[ArgNo],
414 &Alpha::F4RCRegClass);
415 ArgVal = DAG.getCopyFromReg(Chain, dl, args_float[ArgNo], ObjectVT);
418 args_int[ArgNo] = AddLiveIn(MF, args_int[ArgNo],
419 &Alpha::GPRCRegClass);
420 ArgVal = DAG.getCopyFromReg(Chain, dl, args_int[ArgNo], MVT::i64);
424 // Create the frame index object for this incoming parameter...
425 int FI = MFI->CreateFixedObject(8, 8 * (ArgNo - 6), true, false);
427 // Create the SelectionDAG nodes corresponding to a load
428 //from this parameter
429 SDValue FIN = DAG.getFrameIndex(FI, MVT::i64);
430 ArgVal = DAG.getLoad(ObjectVT, dl, Chain, FIN, NULL, 0);
432 InVals.push_back(ArgVal);
435 // If the functions takes variable number of arguments, copy all regs to stack
437 VarArgsOffset = Ins.size() * 8;
438 std::vector<SDValue> LS;
439 for (int i = 0; i < 6; ++i) {
440 if (TargetRegisterInfo::isPhysicalRegister(args_int[i]))
441 args_int[i] = AddLiveIn(MF, args_int[i], &Alpha::GPRCRegClass);
442 SDValue argt = DAG.getCopyFromReg(Chain, dl, args_int[i], MVT::i64);
443 int FI = MFI->CreateFixedObject(8, -8 * (6 - i), true, false);
444 if (i == 0) VarArgsBase = FI;
445 SDValue SDFI = DAG.getFrameIndex(FI, MVT::i64);
446 LS.push_back(DAG.getStore(Chain, dl, argt, SDFI, NULL, 0));
448 if (TargetRegisterInfo::isPhysicalRegister(args_float[i]))
449 args_float[i] = AddLiveIn(MF, args_float[i], &Alpha::F8RCRegClass);
450 argt = DAG.getCopyFromReg(Chain, dl, args_float[i], MVT::f64);
451 FI = MFI->CreateFixedObject(8, - 8 * (12 - i), true, false);
452 SDFI = DAG.getFrameIndex(FI, MVT::i64);
453 LS.push_back(DAG.getStore(Chain, dl, argt, SDFI, NULL, 0));
456 //Set up a token factor with all the stack traffic
457 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, &LS[0], LS.size());
464 AlphaTargetLowering::LowerReturn(SDValue Chain,
465 CallingConv::ID CallConv, bool isVarArg,
466 const SmallVectorImpl<ISD::OutputArg> &Outs,
467 DebugLoc dl, SelectionDAG &DAG) {
469 SDValue Copy = DAG.getCopyToReg(Chain, dl, Alpha::R26,
470 DAG.getNode(AlphaISD::GlobalRetAddr,
471 DebugLoc::getUnknownLoc(),
474 switch (Outs.size()) {
476 llvm_unreachable("Do not know how to return this many arguments!");
479 //return SDValue(); // ret void is legal
481 EVT ArgVT = Outs[0].Val.getValueType();
483 if (ArgVT.isInteger())
486 assert(ArgVT.isFloatingPoint());
489 Copy = DAG.getCopyToReg(Copy, dl, ArgReg,
490 Outs[0].Val, Copy.getValue(1));
491 if (DAG.getMachineFunction().getRegInfo().liveout_empty())
492 DAG.getMachineFunction().getRegInfo().addLiveOut(ArgReg);
496 EVT ArgVT = Outs[0].Val.getValueType();
497 unsigned ArgReg1, ArgReg2;
498 if (ArgVT.isInteger()) {
502 assert(ArgVT.isFloatingPoint());
506 Copy = DAG.getCopyToReg(Copy, dl, ArgReg1,
507 Outs[0].Val, Copy.getValue(1));
508 if (std::find(DAG.getMachineFunction().getRegInfo().liveout_begin(),
509 DAG.getMachineFunction().getRegInfo().liveout_end(), ArgReg1)
510 == DAG.getMachineFunction().getRegInfo().liveout_end())
511 DAG.getMachineFunction().getRegInfo().addLiveOut(ArgReg1);
512 Copy = DAG.getCopyToReg(Copy, dl, ArgReg2,
513 Outs[1].Val, Copy.getValue(1));
514 if (std::find(DAG.getMachineFunction().getRegInfo().liveout_begin(),
515 DAG.getMachineFunction().getRegInfo().liveout_end(), ArgReg2)
516 == DAG.getMachineFunction().getRegInfo().liveout_end())
517 DAG.getMachineFunction().getRegInfo().addLiveOut(ArgReg2);
521 return DAG.getNode(AlphaISD::RET_FLAG, dl,
522 MVT::Other, Copy, Copy.getValue(1));
525 void AlphaTargetLowering::LowerVAARG(SDNode *N, SDValue &Chain,
526 SDValue &DataPtr, SelectionDAG &DAG) {
527 Chain = N->getOperand(0);
528 SDValue VAListP = N->getOperand(1);
529 const Value *VAListS = cast<SrcValueSDNode>(N->getOperand(2))->getValue();
530 DebugLoc dl = N->getDebugLoc();
532 SDValue Base = DAG.getLoad(MVT::i64, dl, Chain, VAListP, VAListS, 0);
533 SDValue Tmp = DAG.getNode(ISD::ADD, dl, MVT::i64, VAListP,
534 DAG.getConstant(8, MVT::i64));
535 SDValue Offset = DAG.getExtLoad(ISD::SEXTLOAD, dl, MVT::i64, Base.getValue(1),
536 Tmp, NULL, 0, MVT::i32);
537 DataPtr = DAG.getNode(ISD::ADD, dl, MVT::i64, Base, Offset);
538 if (N->getValueType(0).isFloatingPoint())
540 //if fp && Offset < 6*8, then subtract 6*8 from DataPtr
541 SDValue FPDataPtr = DAG.getNode(ISD::SUB, dl, MVT::i64, DataPtr,
542 DAG.getConstant(8*6, MVT::i64));
543 SDValue CC = DAG.getSetCC(dl, MVT::i64, Offset,
544 DAG.getConstant(8*6, MVT::i64), ISD::SETLT);
545 DataPtr = DAG.getNode(ISD::SELECT, dl, MVT::i64, CC, FPDataPtr, DataPtr);
548 SDValue NewOffset = DAG.getNode(ISD::ADD, dl, MVT::i64, Offset,
549 DAG.getConstant(8, MVT::i64));
550 Chain = DAG.getTruncStore(Offset.getValue(1), dl, NewOffset, Tmp, NULL, 0,
554 /// LowerOperation - Provide custom lowering hooks for some operations.
556 SDValue AlphaTargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) {
557 DebugLoc dl = Op.getDebugLoc();
558 switch (Op.getOpcode()) {
559 default: llvm_unreachable("Wasn't expecting to be able to lower this!");
560 case ISD::JumpTable: return LowerJumpTable(Op, DAG);
562 case ISD::INTRINSIC_WO_CHAIN: {
563 unsigned IntNo = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
565 default: break; // Don't custom lower most intrinsics.
566 case Intrinsic::alpha_umulh:
567 return DAG.getNode(ISD::MULHU, dl, MVT::i64,
568 Op.getOperand(1), Op.getOperand(2));
572 case ISD::SRL_PARTS: {
573 SDValue ShOpLo = Op.getOperand(0);
574 SDValue ShOpHi = Op.getOperand(1);
575 SDValue ShAmt = Op.getOperand(2);
576 SDValue bm = DAG.getNode(ISD::SUB, dl, MVT::i64,
577 DAG.getConstant(64, MVT::i64), ShAmt);
578 SDValue BMCC = DAG.getSetCC(dl, MVT::i64, bm,
579 DAG.getConstant(0, MVT::i64), ISD::SETLE);
580 // if 64 - shAmt <= 0
581 SDValue Hi_Neg = DAG.getConstant(0, MVT::i64);
582 SDValue ShAmt_Neg = DAG.getNode(ISD::SUB, dl, MVT::i64,
583 DAG.getConstant(0, MVT::i64), bm);
584 SDValue Lo_Neg = DAG.getNode(ISD::SRL, dl, MVT::i64, ShOpHi, ShAmt_Neg);
586 SDValue carries = DAG.getNode(ISD::SHL, dl, MVT::i64, ShOpHi, bm);
587 SDValue Hi_Pos = DAG.getNode(ISD::SRL, dl, MVT::i64, ShOpHi, ShAmt);
588 SDValue Lo_Pos = DAG.getNode(ISD::SRL, dl, MVT::i64, ShOpLo, ShAmt);
589 Lo_Pos = DAG.getNode(ISD::OR, dl, MVT::i64, Lo_Pos, carries);
591 SDValue Hi = DAG.getNode(ISD::SELECT, dl, MVT::i64, BMCC, Hi_Neg, Hi_Pos);
592 SDValue Lo = DAG.getNode(ISD::SELECT, dl, MVT::i64, BMCC, Lo_Neg, Lo_Pos);
593 SDValue Ops[2] = { Lo, Hi };
594 return DAG.getMergeValues(Ops, 2, dl);
596 // case ISD::SRA_PARTS:
598 // case ISD::SHL_PARTS:
601 case ISD::SINT_TO_FP: {
602 assert(Op.getOperand(0).getValueType() == MVT::i64 &&
603 "Unhandled SINT_TO_FP type in custom expander!");
605 bool isDouble = Op.getValueType() == MVT::f64;
606 LD = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::f64, Op.getOperand(0));
607 SDValue FP = DAG.getNode(isDouble?AlphaISD::CVTQT_:AlphaISD::CVTQS_, dl,
608 isDouble?MVT::f64:MVT::f32, LD);
611 case ISD::FP_TO_SINT: {
612 bool isDouble = Op.getOperand(0).getValueType() == MVT::f64;
613 SDValue src = Op.getOperand(0);
615 if (!isDouble) //Promote
616 src = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, src);
618 src = DAG.getNode(AlphaISD::CVTTQ_, dl, MVT::f64, src);
620 return DAG.getNode(ISD::BIT_CONVERT, dl, MVT::i64, src);
622 case ISD::ConstantPool: {
623 ConstantPoolSDNode *CP = cast<ConstantPoolSDNode>(Op);
624 Constant *C = CP->getConstVal();
625 SDValue CPI = DAG.getTargetConstantPool(C, MVT::i64, CP->getAlignment());
626 // FIXME there isn't really any debug info here
628 SDValue Hi = DAG.getNode(AlphaISD::GPRelHi, dl, MVT::i64, CPI,
629 DAG.getGLOBAL_OFFSET_TABLE(MVT::i64));
630 SDValue Lo = DAG.getNode(AlphaISD::GPRelLo, dl, MVT::i64, CPI, Hi);
633 case ISD::GlobalTLSAddress:
634 llvm_unreachable("TLS not implemented for Alpha.");
635 case ISD::GlobalAddress: {
636 GlobalAddressSDNode *GSDN = cast<GlobalAddressSDNode>(Op);
637 GlobalValue *GV = GSDN->getGlobal();
638 SDValue GA = DAG.getTargetGlobalAddress(GV, MVT::i64, GSDN->getOffset());
639 // FIXME there isn't really any debug info here
641 // if (!GV->hasWeakLinkage() && !GV->isDeclaration() && !GV->hasLinkOnceLinkage()) {
642 if (GV->hasLocalLinkage()) {
643 SDValue Hi = DAG.getNode(AlphaISD::GPRelHi, dl, MVT::i64, GA,
644 DAG.getGLOBAL_OFFSET_TABLE(MVT::i64));
645 SDValue Lo = DAG.getNode(AlphaISD::GPRelLo, dl, MVT::i64, GA, Hi);
648 return DAG.getNode(AlphaISD::RelLit, dl, MVT::i64, GA,
649 DAG.getGLOBAL_OFFSET_TABLE(MVT::i64));
651 case ISD::ExternalSymbol: {
652 return DAG.getNode(AlphaISD::RelLit, dl, MVT::i64,
653 DAG.getTargetExternalSymbol(cast<ExternalSymbolSDNode>(Op)
654 ->getSymbol(), MVT::i64),
655 DAG.getGLOBAL_OFFSET_TABLE(MVT::i64));
660 //Expand only on constant case
661 if (Op.getOperand(1).getOpcode() == ISD::Constant) {
662 EVT VT = Op.getNode()->getValueType(0);
663 SDValue Tmp1 = Op.getNode()->getOpcode() == ISD::UREM ?
664 BuildUDIV(Op.getNode(), DAG, NULL) :
665 BuildSDIV(Op.getNode(), DAG, NULL);
666 Tmp1 = DAG.getNode(ISD::MUL, dl, VT, Tmp1, Op.getOperand(1));
667 Tmp1 = DAG.getNode(ISD::SUB, dl, VT, Op.getOperand(0), Tmp1);
673 if (Op.getValueType().isInteger()) {
674 if (Op.getOperand(1).getOpcode() == ISD::Constant)
675 return Op.getOpcode() == ISD::SDIV ? BuildSDIV(Op.getNode(), DAG, NULL)
676 : BuildUDIV(Op.getNode(), DAG, NULL);
677 const char* opstr = 0;
678 switch (Op.getOpcode()) {
679 case ISD::UREM: opstr = "__remqu"; break;
680 case ISD::SREM: opstr = "__remq"; break;
681 case ISD::UDIV: opstr = "__divqu"; break;
682 case ISD::SDIV: opstr = "__divq"; break;
684 SDValue Tmp1 = Op.getOperand(0),
685 Tmp2 = Op.getOperand(1),
686 Addr = DAG.getExternalSymbol(opstr, MVT::i64);
687 return DAG.getNode(AlphaISD::DivCall, dl, MVT::i64, Addr, Tmp1, Tmp2);
692 SDValue Chain, DataPtr;
693 LowerVAARG(Op.getNode(), Chain, DataPtr, DAG);
696 if (Op.getValueType() == MVT::i32)
697 Result = DAG.getExtLoad(ISD::SEXTLOAD, dl, MVT::i64, Chain, DataPtr,
700 Result = DAG.getLoad(Op.getValueType(), dl, Chain, DataPtr, NULL, 0);
704 SDValue Chain = Op.getOperand(0);
705 SDValue DestP = Op.getOperand(1);
706 SDValue SrcP = Op.getOperand(2);
707 const Value *DestS = cast<SrcValueSDNode>(Op.getOperand(3))->getValue();
708 const Value *SrcS = cast<SrcValueSDNode>(Op.getOperand(4))->getValue();
710 SDValue Val = DAG.getLoad(getPointerTy(), dl, Chain, SrcP, SrcS, 0);
711 SDValue Result = DAG.getStore(Val.getValue(1), dl, Val, DestP, DestS, 0);
712 SDValue NP = DAG.getNode(ISD::ADD, dl, MVT::i64, SrcP,
713 DAG.getConstant(8, MVT::i64));
714 Val = DAG.getExtLoad(ISD::SEXTLOAD, dl, MVT::i64, Result,
715 NP, NULL,0, MVT::i32);
716 SDValue NPD = DAG.getNode(ISD::ADD, dl, MVT::i64, DestP,
717 DAG.getConstant(8, MVT::i64));
718 return DAG.getTruncStore(Val.getValue(1), dl, Val, NPD, NULL, 0, MVT::i32);
721 SDValue Chain = Op.getOperand(0);
722 SDValue VAListP = Op.getOperand(1);
723 const Value *VAListS = cast<SrcValueSDNode>(Op.getOperand(2))->getValue();
725 // vastart stores the address of the VarArgsBase and VarArgsOffset
726 SDValue FR = DAG.getFrameIndex(VarArgsBase, MVT::i64);
727 SDValue S1 = DAG.getStore(Chain, dl, FR, VAListP, VAListS, 0);
728 SDValue SA2 = DAG.getNode(ISD::ADD, dl, MVT::i64, VAListP,
729 DAG.getConstant(8, MVT::i64));
730 return DAG.getTruncStore(S1, dl, DAG.getConstant(VarArgsOffset, MVT::i64),
731 SA2, NULL, 0, MVT::i32);
733 case ISD::RETURNADDR:
734 return DAG.getNode(AlphaISD::GlobalRetAddr, DebugLoc::getUnknownLoc(),
737 case ISD::FRAMEADDR: break;
743 void AlphaTargetLowering::ReplaceNodeResults(SDNode *N,
744 SmallVectorImpl<SDValue>&Results,
746 DebugLoc dl = N->getDebugLoc();
747 assert(N->getValueType(0) == MVT::i32 &&
748 N->getOpcode() == ISD::VAARG &&
749 "Unknown node to custom promote!");
751 SDValue Chain, DataPtr;
752 LowerVAARG(N, Chain, DataPtr, DAG);
753 SDValue Res = DAG.getLoad(N->getValueType(0), dl, Chain, DataPtr, NULL, 0);
754 Results.push_back(Res);
755 Results.push_back(SDValue(Res.getNode(), 1));
761 /// getConstraintType - Given a constraint letter, return the type of
762 /// constraint it is for this target.
763 AlphaTargetLowering::ConstraintType
764 AlphaTargetLowering::getConstraintType(const std::string &Constraint) const {
765 if (Constraint.size() == 1) {
766 switch (Constraint[0]) {
770 return C_RegisterClass;
773 return TargetLowering::getConstraintType(Constraint);
776 std::vector<unsigned> AlphaTargetLowering::
777 getRegClassForInlineAsmConstraint(const std::string &Constraint,
779 if (Constraint.size() == 1) {
780 switch (Constraint[0]) {
781 default: break; // Unknown constriant letter
783 return make_vector<unsigned>(Alpha::F0 , Alpha::F1 , Alpha::F2 ,
784 Alpha::F3 , Alpha::F4 , Alpha::F5 ,
785 Alpha::F6 , Alpha::F7 , Alpha::F8 ,
786 Alpha::F9 , Alpha::F10, Alpha::F11,
787 Alpha::F12, Alpha::F13, Alpha::F14,
788 Alpha::F15, Alpha::F16, Alpha::F17,
789 Alpha::F18, Alpha::F19, Alpha::F20,
790 Alpha::F21, Alpha::F22, Alpha::F23,
791 Alpha::F24, Alpha::F25, Alpha::F26,
792 Alpha::F27, Alpha::F28, Alpha::F29,
793 Alpha::F30, Alpha::F31, 0);
795 return make_vector<unsigned>(Alpha::R0 , Alpha::R1 , Alpha::R2 ,
796 Alpha::R3 , Alpha::R4 , Alpha::R5 ,
797 Alpha::R6 , Alpha::R7 , Alpha::R8 ,
798 Alpha::R9 , Alpha::R10, Alpha::R11,
799 Alpha::R12, Alpha::R13, Alpha::R14,
800 Alpha::R15, Alpha::R16, Alpha::R17,
801 Alpha::R18, Alpha::R19, Alpha::R20,
802 Alpha::R21, Alpha::R22, Alpha::R23,
803 Alpha::R24, Alpha::R25, Alpha::R26,
804 Alpha::R27, Alpha::R28, Alpha::R29,
805 Alpha::R30, Alpha::R31, 0);
809 return std::vector<unsigned>();
811 //===----------------------------------------------------------------------===//
812 // Other Lowering Code
813 //===----------------------------------------------------------------------===//
816 AlphaTargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI,
817 MachineBasicBlock *BB,
818 DenseMap<MachineBasicBlock*, MachineBasicBlock*> *EM) const {
819 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
820 assert((MI->getOpcode() == Alpha::CAS32 ||
821 MI->getOpcode() == Alpha::CAS64 ||
822 MI->getOpcode() == Alpha::LAS32 ||
823 MI->getOpcode() == Alpha::LAS64 ||
824 MI->getOpcode() == Alpha::SWAP32 ||
825 MI->getOpcode() == Alpha::SWAP64) &&
826 "Unexpected instr type to insert");
828 bool is32 = MI->getOpcode() == Alpha::CAS32 ||
829 MI->getOpcode() == Alpha::LAS32 ||
830 MI->getOpcode() == Alpha::SWAP32;
832 //Load locked store conditional for atomic ops take on the same form
835 //do stuff (maybe branch to exit)
837 //test sc and maybe branck to start
839 const BasicBlock *LLVM_BB = BB->getBasicBlock();
840 DebugLoc dl = MI->getDebugLoc();
841 MachineFunction::iterator It = BB;
844 MachineBasicBlock *thisMBB = BB;
845 MachineFunction *F = BB->getParent();
846 MachineBasicBlock *llscMBB = F->CreateMachineBasicBlock(LLVM_BB);
847 MachineBasicBlock *sinkMBB = F->CreateMachineBasicBlock(LLVM_BB);
849 // Inform sdisel of the edge changes.
850 for (MachineBasicBlock::succ_iterator I = BB->succ_begin(),
851 E = BB->succ_end(); I != E; ++I)
852 EM->insert(std::make_pair(*I, sinkMBB));
854 sinkMBB->transferSuccessors(thisMBB);
856 F->insert(It, llscMBB);
857 F->insert(It, sinkMBB);
859 BuildMI(thisMBB, dl, TII->get(Alpha::BR)).addMBB(llscMBB);
861 unsigned reg_res = MI->getOperand(0).getReg(),
862 reg_ptr = MI->getOperand(1).getReg(),
863 reg_v2 = MI->getOperand(2).getReg(),
864 reg_store = F->getRegInfo().createVirtualRegister(&Alpha::GPRCRegClass);
866 BuildMI(llscMBB, dl, TII->get(is32 ? Alpha::LDL_L : Alpha::LDQ_L),
867 reg_res).addImm(0).addReg(reg_ptr);
868 switch (MI->getOpcode()) {
872 = F->getRegInfo().createVirtualRegister(&Alpha::GPRCRegClass);
873 BuildMI(llscMBB, dl, TII->get(Alpha::CMPEQ), reg_cmp)
874 .addReg(reg_v2).addReg(reg_res);
875 BuildMI(llscMBB, dl, TII->get(Alpha::BEQ))
876 .addImm(0).addReg(reg_cmp).addMBB(sinkMBB);
877 BuildMI(llscMBB, dl, TII->get(Alpha::BISr), reg_store)
878 .addReg(Alpha::R31).addReg(MI->getOperand(3).getReg());
883 BuildMI(llscMBB, dl,TII->get(is32 ? Alpha::ADDLr : Alpha::ADDQr), reg_store)
884 .addReg(reg_res).addReg(reg_v2);
888 case Alpha::SWAP64: {
889 BuildMI(llscMBB, dl, TII->get(Alpha::BISr), reg_store)
890 .addReg(reg_v2).addReg(reg_v2);
894 BuildMI(llscMBB, dl, TII->get(is32 ? Alpha::STL_C : Alpha::STQ_C), reg_store)
895 .addReg(reg_store).addImm(0).addReg(reg_ptr);
896 BuildMI(llscMBB, dl, TII->get(Alpha::BEQ))
897 .addImm(0).addReg(reg_store).addMBB(llscMBB);
898 BuildMI(llscMBB, dl, TII->get(Alpha::BR)).addMBB(sinkMBB);
900 thisMBB->addSuccessor(llscMBB);
901 llscMBB->addSuccessor(llscMBB);
902 llscMBB->addSuccessor(sinkMBB);
903 F->DeleteMachineInstr(MI); // The pseudo instruction is gone now.
909 AlphaTargetLowering::isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const {
910 // The Alpha target isn't yet aware of offsets.
914 bool AlphaTargetLowering::isFPImmLegal(const APFloat &Imm, EVT VT) const {
915 if (VT != MVT::f32 && VT != MVT::f64)
921 return Imm.isZero() || Imm.isNegZero();