1 //===-- AlphaISelLowering.cpp - Alpha DAG Lowering Implementation ---------===//
3 // The LLVM Compiler Infrastructure
5 // This file was developed by Andrew Lenharth and is distributed under
6 // the University of Illinois Open Source License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file implements the AlphaISelLowering class.
12 //===----------------------------------------------------------------------===//
14 #include "AlphaISelLowering.h"
15 #include "AlphaTargetMachine.h"
16 #include "llvm/CodeGen/MachineFrameInfo.h"
17 #include "llvm/CodeGen/MachineFunction.h"
18 #include "llvm/CodeGen/MachineInstrBuilder.h"
19 #include "llvm/CodeGen/SelectionDAG.h"
20 #include "llvm/CodeGen/SSARegMap.h"
21 #include "llvm/Constants.h"
22 #include "llvm/Function.h"
23 #include "llvm/Module.h"
24 #include "llvm/Support/CommandLine.h"
29 /// AddLiveIn - This helper function adds the specified physical register to the
30 /// MachineFunction as a live in value. It also creates a corresponding virtual
32 static unsigned AddLiveIn(MachineFunction &MF, unsigned PReg,
33 TargetRegisterClass *RC) {
34 assert(RC->contains(PReg) && "Not the correct regclass!");
35 unsigned VReg = MF.getSSARegMap()->createVirtualRegister(RC);
36 MF.addLiveIn(PReg, VReg);
40 AlphaTargetLowering::AlphaTargetLowering(TargetMachine &TM) : TargetLowering(TM) {
41 // Set up the TargetLowering object.
42 //I am having problems with shr n ubyte 1
43 setShiftAmountType(MVT::i64);
44 setSetCCResultType(MVT::i64);
45 setSetCCResultContents(ZeroOrOneSetCCResult);
47 setUsesGlobalOffsetTable(true);
49 addRegisterClass(MVT::i64, Alpha::GPRCRegisterClass);
50 addRegisterClass(MVT::f64, Alpha::F8RCRegisterClass);
51 addRegisterClass(MVT::f32, Alpha::F4RCRegisterClass);
53 setLoadXAction(ISD::EXTLOAD, MVT::i1, Promote);
54 setLoadXAction(ISD::EXTLOAD, MVT::f32, Expand);
56 setLoadXAction(ISD::ZEXTLOAD, MVT::i1, Promote);
57 setLoadXAction(ISD::ZEXTLOAD, MVT::i32, Expand);
59 setLoadXAction(ISD::SEXTLOAD, MVT::i1, Promote);
60 setLoadXAction(ISD::SEXTLOAD, MVT::i8, Expand);
61 setLoadXAction(ISD::SEXTLOAD, MVT::i16, Expand);
63 // setOperationAction(ISD::BRIND, MVT::i64, Expand);
64 setOperationAction(ISD::BR_CC, MVT::Other, Expand);
65 setOperationAction(ISD::SELECT_CC, MVT::Other, Expand);
67 setOperationAction(ISD::TRUNCSTORE, MVT::i1, Promote);
69 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1, Expand);
71 setOperationAction(ISD::FREM, MVT::f32, Expand);
72 setOperationAction(ISD::FREM, MVT::f64, Expand);
74 setOperationAction(ISD::UINT_TO_FP, MVT::i64, Expand);
75 setOperationAction(ISD::SINT_TO_FP, MVT::i64, Custom);
76 setOperationAction(ISD::FP_TO_UINT, MVT::i64, Expand);
77 setOperationAction(ISD::FP_TO_SINT, MVT::i64, Custom);
79 if (!TM.getSubtarget<AlphaSubtarget>().hasCT()) {
80 setOperationAction(ISD::CTPOP , MVT::i64 , Expand);
81 setOperationAction(ISD::CTTZ , MVT::i64 , Expand);
82 setOperationAction(ISD::CTLZ , MVT::i64 , Expand);
84 setOperationAction(ISD::BSWAP , MVT::i64, Expand);
85 setOperationAction(ISD::ROTL , MVT::i64, Expand);
86 setOperationAction(ISD::ROTR , MVT::i64, Expand);
88 setOperationAction(ISD::SREM , MVT::i64, Custom);
89 setOperationAction(ISD::UREM , MVT::i64, Custom);
90 setOperationAction(ISD::SDIV , MVT::i64, Custom);
91 setOperationAction(ISD::UDIV , MVT::i64, Custom);
93 setOperationAction(ISD::MEMMOVE , MVT::Other, Expand);
94 setOperationAction(ISD::MEMSET , MVT::Other, Expand);
95 setOperationAction(ISD::MEMCPY , MVT::Other, Expand);
97 // We don't support sin/cos/sqrt
98 setOperationAction(ISD::FSIN , MVT::f64, Expand);
99 setOperationAction(ISD::FCOS , MVT::f64, Expand);
100 setOperationAction(ISD::FSIN , MVT::f32, Expand);
101 setOperationAction(ISD::FCOS , MVT::f32, Expand);
103 setOperationAction(ISD::FSQRT, MVT::f64, Expand);
104 setOperationAction(ISD::FSQRT, MVT::f32, Expand);
106 setOperationAction(ISD::SETCC, MVT::f32, Promote);
108 // We don't have line number support yet.
109 setOperationAction(ISD::LOCATION, MVT::Other, Expand);
110 setOperationAction(ISD::DEBUG_LOC, MVT::Other, Expand);
111 setOperationAction(ISD::DEBUG_LABEL, MVT::Other, Expand);
113 // Not implemented yet.
114 setOperationAction(ISD::STACKSAVE, MVT::Other, Expand);
115 setOperationAction(ISD::STACKRESTORE, MVT::Other, Expand);
116 setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i64, Expand);
118 // We want to legalize GlobalAddress and ConstantPool and
119 // ExternalSymbols nodes into the appropriate instructions to
120 // materialize the address.
121 setOperationAction(ISD::GlobalAddress, MVT::i64, Custom);
122 setOperationAction(ISD::ConstantPool, MVT::i64, Custom);
123 setOperationAction(ISD::ExternalSymbol, MVT::i64, Custom);
125 setOperationAction(ISD::VASTART, MVT::Other, Custom);
126 setOperationAction(ISD::VAEND, MVT::Other, Expand);
127 setOperationAction(ISD::VACOPY, MVT::Other, Custom);
128 setOperationAction(ISD::VAARG, MVT::Other, Custom);
129 setOperationAction(ISD::VAARG, MVT::i32, Custom);
131 setOperationAction(ISD::RET, MVT::Other, Custom);
133 setOperationAction(ISD::JumpTable, MVT::i64, Custom);
134 setOperationAction(ISD::JumpTable, MVT::i32, Custom);
136 setStackPointerRegisterToSaveRestore(Alpha::R30);
138 setOperationAction(ISD::ConstantFP, MVT::f64, Expand);
139 setOperationAction(ISD::ConstantFP, MVT::f32, Expand);
140 addLegalFPImmediate(+0.0); //F31
141 addLegalFPImmediate(-0.0); //-F31
144 setJumpBufAlignment(16);
146 computeRegisterProperties();
148 useITOF = TM.getSubtarget<AlphaSubtarget>().hasF2I();
151 const char *AlphaTargetLowering::getTargetNodeName(unsigned Opcode) const {
154 case AlphaISD::ITOFT_: return "Alpha::ITOFT_";
155 case AlphaISD::FTOIT_: return "Alpha::FTOIT_";
156 case AlphaISD::CVTQT_: return "Alpha::CVTQT_";
157 case AlphaISD::CVTQS_: return "Alpha::CVTQS_";
158 case AlphaISD::CVTTQ_: return "Alpha::CVTTQ_";
159 case AlphaISD::GPRelHi: return "Alpha::GPRelHi";
160 case AlphaISD::GPRelLo: return "Alpha::GPRelLo";
161 case AlphaISD::RelLit: return "Alpha::RelLit";
162 case AlphaISD::GlobalRetAddr: return "Alpha::GlobalRetAddr";
163 case AlphaISD::CALL: return "Alpha::CALL";
164 case AlphaISD::DivCall: return "Alpha::DivCall";
165 case AlphaISD::RET_FLAG: return "Alpha::RET_FLAG";
169 static SDOperand LowerJumpTable(SDOperand Op, SelectionDAG &DAG) {
170 MVT::ValueType PtrVT = Op.getValueType();
171 JumpTableSDNode *JT = cast<JumpTableSDNode>(Op);
172 SDOperand JTI = DAG.getTargetJumpTable(JT->getIndex(), PtrVT);
173 SDOperand Zero = DAG.getConstant(0, PtrVT);
175 const TargetMachine &TM = DAG.getTarget();
177 SDOperand Hi = DAG.getNode(AlphaISD::GPRelHi, MVT::i64, JTI,
178 DAG.getNode(ISD::GLOBAL_OFFSET_TABLE, MVT::i64));
179 SDOperand Lo = DAG.getNode(AlphaISD::GPRelLo, MVT::i64, JTI, Hi);
183 //http://www.cs.arizona.edu/computer.help/policy/DIGITAL_unix/
184 //AA-PY8AC-TET1_html/callCH3.html#BLOCK21
186 //For now, just use variable size stack frame format
188 //In a standard call, the first six items are passed in registers $16
189 //- $21 and/or registers $f16 - $f21. (See Section 4.1.2 for details
190 //of argument-to-register correspondence.) The remaining items are
191 //collected in a memory argument list that is a naturally aligned
192 //array of quadwords. In a standard call, this list, if present, must
193 //be passed at 0(SP).
194 //7 ... n 0(SP) ... (n-7)*8(SP)
202 static SDOperand LowerFORMAL_ARGUMENTS(SDOperand Op, SelectionDAG &DAG,
207 MachineFunction &MF = DAG.getMachineFunction();
208 MachineFrameInfo *MFI = MF.getFrameInfo();
209 SSARegMap *RegMap = MF.getSSARegMap();
210 std::vector<SDOperand> ArgValues;
211 SDOperand Root = Op.getOperand(0);
213 GP = AddLiveIn(MF, Alpha::R29, &Alpha::GPRCRegClass);
214 RA = AddLiveIn(MF, Alpha::R26, &Alpha::GPRCRegClass);
216 unsigned args_int[] = {
217 Alpha::R16, Alpha::R17, Alpha::R18, Alpha::R19, Alpha::R20, Alpha::R21};
218 unsigned args_float[] = {
219 Alpha::F16, Alpha::F17, Alpha::F18, Alpha::F19, Alpha::F20, Alpha::F21};
221 for (unsigned ArgNo = 0, e = Op.Val->getNumValues()-1; ArgNo != e; ++ArgNo) {
223 MVT::ValueType ObjectVT = Op.getValue(ArgNo).getValueType();
230 std::cerr << "Unknown Type " << ObjectVT << "\n";
233 args_float[ArgNo] = AddLiveIn(MF, args_float[ArgNo],
234 &Alpha::F8RCRegClass);
235 ArgVal = DAG.getCopyFromReg(Root, args_float[ArgNo], ObjectVT);
238 args_float[ArgNo] = AddLiveIn(MF, args_float[ArgNo],
239 &Alpha::F4RCRegClass);
240 ArgVal = DAG.getCopyFromReg(Root, args_float[ArgNo], ObjectVT);
243 args_int[ArgNo] = AddLiveIn(MF, args_int[ArgNo],
244 &Alpha::GPRCRegClass);
245 ArgVal = DAG.getCopyFromReg(Root, args_int[ArgNo], MVT::i64);
249 // Create the frame index object for this incoming parameter...
250 int FI = MFI->CreateFixedObject(8, 8 * (ArgNo - 6));
252 // Create the SelectionDAG nodes corresponding to a load
253 //from this parameter
254 SDOperand FIN = DAG.getFrameIndex(FI, MVT::i64);
255 ArgVal = DAG.getLoad(ObjectVT, Root, FIN, NULL, 0);
257 ArgValues.push_back(ArgVal);
260 // If the functions takes variable number of arguments, copy all regs to stack
261 bool isVarArg = cast<ConstantSDNode>(Op.getOperand(2))->getValue() != 0;
263 VarArgsOffset = (Op.Val->getNumValues()-1) * 8;
264 std::vector<SDOperand> LS;
265 for (int i = 0; i < 6; ++i) {
266 if (MRegisterInfo::isPhysicalRegister(args_int[i]))
267 args_int[i] = AddLiveIn(MF, args_int[i], &Alpha::GPRCRegClass);
268 SDOperand argt = DAG.getCopyFromReg(Root, args_int[i], MVT::i64);
269 int FI = MFI->CreateFixedObject(8, -8 * (6 - i));
270 if (i == 0) VarArgsBase = FI;
271 SDOperand SDFI = DAG.getFrameIndex(FI, MVT::i64);
272 LS.push_back(DAG.getStore(Root, argt, SDFI, DAG.getSrcValue(NULL)));
274 if (MRegisterInfo::isPhysicalRegister(args_float[i]))
275 args_float[i] = AddLiveIn(MF, args_float[i], &Alpha::F8RCRegClass);
276 argt = DAG.getCopyFromReg(Root, args_float[i], MVT::f64);
277 FI = MFI->CreateFixedObject(8, - 8 * (12 - i));
278 SDFI = DAG.getFrameIndex(FI, MVT::i64);
279 LS.push_back(DAG.getStore(Root, argt, SDFI, DAG.getSrcValue(NULL)));
282 //Set up a token factor with all the stack traffic
283 Root = DAG.getNode(ISD::TokenFactor, MVT::Other, &LS[0], LS.size());
286 ArgValues.push_back(Root);
288 // Return the new list of results.
289 std::vector<MVT::ValueType> RetVT(Op.Val->value_begin(),
290 Op.Val->value_end());
291 return DAG.getNode(ISD::MERGE_VALUES, RetVT, &ArgValues[0], ArgValues.size());
294 static SDOperand LowerRET(SDOperand Op, SelectionDAG &DAG, unsigned int RA) {
295 SDOperand Copy = DAG.getCopyToReg(Op.getOperand(0), Alpha::R26,
296 DAG.getNode(AlphaISD::GlobalRetAddr,
299 switch (Op.getNumOperands()) {
301 assert(0 && "Do not know how to return this many arguments!");
305 //return SDOperand(); // ret void is legal
307 MVT::ValueType ArgVT = Op.getOperand(1).getValueType();
309 if (MVT::isInteger(ArgVT))
312 assert(MVT::isFloatingPoint(ArgVT));
315 Copy = DAG.getCopyToReg(Copy, ArgReg, Op.getOperand(1), Copy.getValue(1));
316 if(DAG.getMachineFunction().liveout_empty())
317 DAG.getMachineFunction().addLiveOut(ArgReg);
321 return DAG.getNode(AlphaISD::RET_FLAG, MVT::Other, Copy, Copy.getValue(1));
324 std::pair<SDOperand, SDOperand>
325 AlphaTargetLowering::LowerCallTo(SDOperand Chain,
326 const Type *RetTy, bool isVarArg,
327 unsigned CallingConv, bool isTailCall,
328 SDOperand Callee, ArgListTy &Args,
332 NumBytes = (Args.size() - 6) * 8;
334 Chain = DAG.getCALLSEQ_START(Chain,
335 DAG.getConstant(NumBytes, getPointerTy()));
336 std::vector<SDOperand> args_to_use;
337 for (unsigned i = 0, e = Args.size(); i != e; ++i)
339 switch (getValueType(Args[i].second)) {
340 default: assert(0 && "Unexpected ValueType for argument!");
345 // Promote the integer to 64 bits. If the input type is signed use a
346 // sign extend, otherwise use a zero extend.
347 if (Args[i].second->isSigned())
348 Args[i].first = DAG.getNode(ISD::SIGN_EXTEND, MVT::i64, Args[i].first);
350 Args[i].first = DAG.getNode(ISD::ZERO_EXTEND, MVT::i64, Args[i].first);
357 args_to_use.push_back(Args[i].first);
360 std::vector<MVT::ValueType> RetVals;
361 MVT::ValueType RetTyVT = getValueType(RetTy);
362 MVT::ValueType ActualRetTyVT = RetTyVT;
363 if (RetTyVT >= MVT::i1 && RetTyVT <= MVT::i32)
364 ActualRetTyVT = MVT::i64;
366 if (RetTyVT != MVT::isVoid)
367 RetVals.push_back(ActualRetTyVT);
368 RetVals.push_back(MVT::Other);
370 std::vector<SDOperand> Ops;
371 Ops.push_back(Chain);
372 Ops.push_back(Callee);
373 Ops.insert(Ops.end(), args_to_use.begin(), args_to_use.end());
374 SDOperand TheCall = DAG.getNode(AlphaISD::CALL, RetVals, &Ops[0], Ops.size());
375 Chain = TheCall.getValue(RetTyVT != MVT::isVoid);
376 Chain = DAG.getNode(ISD::CALLSEQ_END, MVT::Other, Chain,
377 DAG.getConstant(NumBytes, getPointerTy()));
378 SDOperand RetVal = TheCall;
380 if (RetTyVT != ActualRetTyVT) {
381 RetVal = DAG.getNode(RetTy->isSigned() ? ISD::AssertSext : ISD::AssertZext,
382 MVT::i64, RetVal, DAG.getValueType(RetTyVT));
383 RetVal = DAG.getNode(ISD::TRUNCATE, RetTyVT, RetVal);
386 return std::make_pair(RetVal, Chain);
389 void AlphaTargetLowering::restoreGP(MachineBasicBlock* BB)
391 BuildMI(BB, Alpha::BIS, 2, Alpha::R29).addReg(GP).addReg(GP);
393 void AlphaTargetLowering::restoreRA(MachineBasicBlock* BB)
395 BuildMI(BB, Alpha::BIS, 2, Alpha::R26).addReg(RA).addReg(RA);
404 /// LowerOperation - Provide custom lowering hooks for some operations.
406 SDOperand AlphaTargetLowering::LowerOperation(SDOperand Op, SelectionDAG &DAG) {
407 switch (Op.getOpcode()) {
408 default: assert(0 && "Wasn't expecting to be able to lower this!");
409 case ISD::FORMAL_ARGUMENTS: return LowerFORMAL_ARGUMENTS(Op, DAG,
413 case ISD::RET: return LowerRET(Op,DAG, getVRegRA());
414 case ISD::JumpTable: return LowerJumpTable(Op, DAG);
416 case ISD::SINT_TO_FP: {
417 assert(MVT::i64 == Op.getOperand(0).getValueType() &&
418 "Unhandled SINT_TO_FP type in custom expander!");
420 bool isDouble = MVT::f64 == Op.getValueType();
422 LD = DAG.getNode(AlphaISD::ITOFT_, MVT::f64, Op.getOperand(0));
425 DAG.getMachineFunction().getFrameInfo()->CreateStackObject(8, 8);
426 SDOperand FI = DAG.getFrameIndex(FrameIdx, MVT::i64);
427 SDOperand ST = DAG.getStore(DAG.getEntryNode(),
428 Op.getOperand(0), FI, DAG.getSrcValue(0));
429 LD = DAG.getLoad(MVT::f64, ST, FI, NULL, 0);
431 SDOperand FP = DAG.getNode(isDouble?AlphaISD::CVTQT_:AlphaISD::CVTQS_,
432 isDouble?MVT::f64:MVT::f32, LD);
435 case ISD::FP_TO_SINT: {
436 bool isDouble = MVT::f64 == Op.getOperand(0).getValueType();
437 SDOperand src = Op.getOperand(0);
439 if (!isDouble) //Promote
440 src = DAG.getNode(ISD::FP_EXTEND, MVT::f64, src);
442 src = DAG.getNode(AlphaISD::CVTTQ_, MVT::f64, src);
445 return DAG.getNode(AlphaISD::FTOIT_, MVT::i64, src);
448 DAG.getMachineFunction().getFrameInfo()->CreateStackObject(8, 8);
449 SDOperand FI = DAG.getFrameIndex(FrameIdx, MVT::i64);
450 SDOperand ST = DAG.getStore(DAG.getEntryNode(),
451 src, FI, DAG.getSrcValue(0));
452 return DAG.getLoad(MVT::i64, ST, FI, NULL, 0);
455 case ISD::ConstantPool: {
456 ConstantPoolSDNode *CP = cast<ConstantPoolSDNode>(Op);
457 Constant *C = CP->getConstVal();
458 SDOperand CPI = DAG.getTargetConstantPool(C, MVT::i64, CP->getAlignment());
460 SDOperand Hi = DAG.getNode(AlphaISD::GPRelHi, MVT::i64, CPI,
461 DAG.getNode(ISD::GLOBAL_OFFSET_TABLE, MVT::i64));
462 SDOperand Lo = DAG.getNode(AlphaISD::GPRelLo, MVT::i64, CPI, Hi);
465 case ISD::GlobalAddress: {
466 GlobalAddressSDNode *GSDN = cast<GlobalAddressSDNode>(Op);
467 GlobalValue *GV = GSDN->getGlobal();
468 SDOperand GA = DAG.getTargetGlobalAddress(GV, MVT::i64, GSDN->getOffset());
470 // if (!GV->hasWeakLinkage() && !GV->isExternal() && !GV->hasLinkOnceLinkage()) {
471 if (GV->hasInternalLinkage()) {
472 SDOperand Hi = DAG.getNode(AlphaISD::GPRelHi, MVT::i64, GA,
473 DAG.getNode(ISD::GLOBAL_OFFSET_TABLE, MVT::i64));
474 SDOperand Lo = DAG.getNode(AlphaISD::GPRelLo, MVT::i64, GA, Hi);
477 return DAG.getNode(AlphaISD::RelLit, MVT::i64, GA,
478 DAG.getNode(ISD::GLOBAL_OFFSET_TABLE, MVT::i64));
480 case ISD::ExternalSymbol: {
481 return DAG.getNode(AlphaISD::RelLit, MVT::i64,
482 DAG.getTargetExternalSymbol(cast<ExternalSymbolSDNode>(Op)
483 ->getSymbol(), MVT::i64),
484 DAG.getNode(ISD::GLOBAL_OFFSET_TABLE, MVT::i64));
489 //Expand only on constant case
490 if (Op.getOperand(1).getOpcode() == ISD::Constant) {
491 MVT::ValueType VT = Op.Val->getValueType(0);
492 unsigned Opc = Op.Val->getOpcode() == ISD::UREM ? ISD::UDIV : ISD::SDIV;
493 SDOperand Tmp1 = Op.Val->getOpcode() == ISD::UREM ?
494 BuildUDIV(Op.Val, DAG, NULL) :
495 BuildSDIV(Op.Val, DAG, NULL);
496 Tmp1 = DAG.getNode(ISD::MUL, VT, Tmp1, Op.getOperand(1));
497 Tmp1 = DAG.getNode(ISD::SUB, VT, Op.getOperand(0), Tmp1);
503 if (MVT::isInteger(Op.getValueType())) {
504 if (Op.getOperand(1).getOpcode() == ISD::Constant)
505 return Op.getOpcode() == ISD::SDIV ? BuildSDIV(Op.Val, DAG, NULL)
506 : BuildUDIV(Op.Val, DAG, NULL);
507 const char* opstr = 0;
508 switch(Op.getOpcode()) {
509 case ISD::UREM: opstr = "__remqu"; break;
510 case ISD::SREM: opstr = "__remq"; break;
511 case ISD::UDIV: opstr = "__divqu"; break;
512 case ISD::SDIV: opstr = "__divq"; break;
514 SDOperand Tmp1 = Op.getOperand(0),
515 Tmp2 = Op.getOperand(1),
516 Addr = DAG.getExternalSymbol(opstr, MVT::i64);
517 return DAG.getNode(AlphaISD::DivCall, MVT::i64, Addr, Tmp1, Tmp2);
522 SDOperand Chain = Op.getOperand(0);
523 SDOperand VAListP = Op.getOperand(1);
524 SrcValueSDNode *VAListS = cast<SrcValueSDNode>(Op.getOperand(2));
526 SDOperand Base = DAG.getLoad(MVT::i64, Chain, VAListP, VAListS->getValue(),
527 VAListS->getOffset());
528 SDOperand Tmp = DAG.getNode(ISD::ADD, MVT::i64, VAListP,
529 DAG.getConstant(8, MVT::i64));
530 SDOperand Offset = DAG.getExtLoad(ISD::SEXTLOAD, MVT::i64, Base.getValue(1),
531 Tmp, NULL, 0, MVT::i32);
532 SDOperand DataPtr = DAG.getNode(ISD::ADD, MVT::i64, Base, Offset);
533 if (MVT::isFloatingPoint(Op.getValueType()))
535 //if fp && Offset < 6*8, then subtract 6*8 from DataPtr
536 SDOperand FPDataPtr = DAG.getNode(ISD::SUB, MVT::i64, DataPtr,
537 DAG.getConstant(8*6, MVT::i64));
538 SDOperand CC = DAG.getSetCC(MVT::i64, Offset,
539 DAG.getConstant(8*6, MVT::i64), ISD::SETLT);
540 DataPtr = DAG.getNode(ISD::SELECT, MVT::i64, CC, FPDataPtr, DataPtr);
543 SDOperand NewOffset = DAG.getNode(ISD::ADD, MVT::i64, Offset,
544 DAG.getConstant(8, MVT::i64));
545 SDOperand Update = DAG.getNode(ISD::TRUNCSTORE, MVT::Other,
546 Offset.getValue(1), NewOffset,
547 Tmp, DAG.getSrcValue(0),
548 DAG.getValueType(MVT::i32));
551 if (Op.getValueType() == MVT::i32)
552 Result = DAG.getExtLoad(ISD::SEXTLOAD, MVT::i64, Update, DataPtr,
555 Result = DAG.getLoad(Op.getValueType(), Update, DataPtr, NULL, 0);
559 SDOperand Chain = Op.getOperand(0);
560 SDOperand DestP = Op.getOperand(1);
561 SDOperand SrcP = Op.getOperand(2);
562 SDOperand DestS = Op.getOperand(3);
563 SrcValueSDNode *SrcS = cast<SrcValueSDNode>(Op.getOperand(4));
565 SDOperand Val = DAG.getLoad(getPointerTy(), Chain, SrcP,
566 SrcS->getValue(), SrcS->getOffset());
567 SDOperand Result = DAG.getStore(Val.getValue(1), Val, DestP, DestS);
568 SDOperand NP = DAG.getNode(ISD::ADD, MVT::i64, SrcP,
569 DAG.getConstant(8, MVT::i64));
570 Val = DAG.getExtLoad(ISD::SEXTLOAD, MVT::i64, Result, NP, NULL,0, MVT::i32);
571 SDOperand NPD = DAG.getNode(ISD::ADD, MVT::i64, DestP,
572 DAG.getConstant(8, MVT::i64));
573 return DAG.getNode(ISD::TRUNCSTORE, MVT::Other, Val.getValue(1),
574 Val, NPD, DAG.getSrcValue(0),DAG.getValueType(MVT::i32));
577 SDOperand Chain = Op.getOperand(0);
578 SDOperand VAListP = Op.getOperand(1);
579 SDOperand VAListS = Op.getOperand(2);
581 // vastart stores the address of the VarArgsBase and VarArgsOffset
582 SDOperand FR = DAG.getFrameIndex(VarArgsBase, MVT::i64);
583 SDOperand S1 = DAG.getStore(Chain, FR, VAListP, VAListS);
584 SDOperand SA2 = DAG.getNode(ISD::ADD, MVT::i64, VAListP,
585 DAG.getConstant(8, MVT::i64));
586 return DAG.getNode(ISD::TRUNCSTORE, MVT::Other, S1,
587 DAG.getConstant(VarArgsOffset, MVT::i64), SA2,
588 DAG.getSrcValue(0), DAG.getValueType(MVT::i32));
595 SDOperand AlphaTargetLowering::CustomPromoteOperation(SDOperand Op,
597 assert(Op.getValueType() == MVT::i32 &&
598 Op.getOpcode() == ISD::VAARG &&
599 "Unknown node to custom promote!");
601 // The code in LowerOperation already handles i32 vaarg
602 return LowerOperation(Op, DAG);
608 /// getConstraintType - Given a constraint letter, return the type of
609 /// constraint it is for this target.
610 AlphaTargetLowering::ConstraintType
611 AlphaTargetLowering::getConstraintType(char ConstraintLetter) const {
612 switch (ConstraintLetter) {
616 return C_RegisterClass;
618 return TargetLowering::getConstraintType(ConstraintLetter);
621 std::vector<unsigned> AlphaTargetLowering::
622 getRegClassForInlineAsmConstraint(const std::string &Constraint,
623 MVT::ValueType VT) const {
624 if (Constraint.size() == 1) {
625 switch (Constraint[0]) {
626 default: break; // Unknown constriant letter
628 return make_vector<unsigned>(Alpha::F0 , Alpha::F1 , Alpha::F2 ,
629 Alpha::F3 , Alpha::F4 , Alpha::F5 ,
630 Alpha::F6 , Alpha::F7 , Alpha::F8 ,
631 Alpha::F9 , Alpha::F10, Alpha::F11,
632 Alpha::F12, Alpha::F13, Alpha::F14,
633 Alpha::F15, Alpha::F16, Alpha::F17,
634 Alpha::F18, Alpha::F19, Alpha::F20,
635 Alpha::F21, Alpha::F22, Alpha::F23,
636 Alpha::F24, Alpha::F25, Alpha::F26,
637 Alpha::F27, Alpha::F28, Alpha::F29,
638 Alpha::F30, Alpha::F31, 0);
640 return make_vector<unsigned>(Alpha::R0 , Alpha::R1 , Alpha::R2 ,
641 Alpha::R3 , Alpha::R4 , Alpha::R5 ,
642 Alpha::R6 , Alpha::R7 , Alpha::R8 ,
643 Alpha::R9 , Alpha::R10, Alpha::R11,
644 Alpha::R12, Alpha::R13, Alpha::R14,
645 Alpha::R15, Alpha::R16, Alpha::R17,
646 Alpha::R18, Alpha::R19, Alpha::R20,
647 Alpha::R21, Alpha::R22, Alpha::R23,
648 Alpha::R24, Alpha::R25, Alpha::R26,
649 Alpha::R27, Alpha::R28, Alpha::R29,
650 Alpha::R30, Alpha::R31, 0);
655 return std::vector<unsigned>();