1 //===-- AlphaISelLowering.cpp - Alpha DAG Lowering Implementation ---------===//
3 // The LLVM Compiler Infrastructure
5 // This file was developed by Andrew Lenharth and is distributed under
6 // the University of Illinois Open Source License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file implements the AlphaISelLowering class.
12 //===----------------------------------------------------------------------===//
14 #include "AlphaISelLowering.h"
15 #include "AlphaTargetMachine.h"
16 #include "llvm/CodeGen/MachineFrameInfo.h"
17 #include "llvm/CodeGen/MachineFunction.h"
18 #include "llvm/CodeGen/MachineInstrBuilder.h"
19 #include "llvm/CodeGen/SelectionDAG.h"
20 #include "llvm/CodeGen/SSARegMap.h"
21 #include "llvm/Constants.h"
22 #include "llvm/Function.h"
23 #include "llvm/Module.h"
24 #include "llvm/Support/CommandLine.h"
29 /// AddLiveIn - This helper function adds the specified physical register to the
30 /// MachineFunction as a live in value. It also creates a corresponding virtual
32 static unsigned AddLiveIn(MachineFunction &MF, unsigned PReg,
33 TargetRegisterClass *RC) {
34 assert(RC->contains(PReg) && "Not the correct regclass!");
35 unsigned VReg = MF.getSSARegMap()->createVirtualRegister(RC);
36 MF.addLiveIn(PReg, VReg);
40 AlphaTargetLowering::AlphaTargetLowering(TargetMachine &TM) : TargetLowering(TM) {
41 // Set up the TargetLowering object.
42 //I am having problems with shr n ubyte 1
43 setShiftAmountType(MVT::i64);
44 setSetCCResultType(MVT::i64);
45 setSetCCResultContents(ZeroOrOneSetCCResult);
47 addRegisterClass(MVT::i64, Alpha::GPRCRegisterClass);
48 addRegisterClass(MVT::f64, Alpha::F8RCRegisterClass);
49 addRegisterClass(MVT::f32, Alpha::F4RCRegisterClass);
51 setOperationAction(ISD::BRIND, MVT::i64, Expand);
52 setOperationAction(ISD::BR_CC, MVT::Other, Expand);
53 setOperationAction(ISD::SELECT_CC, MVT::Other, Expand);
55 setOperationAction(ISD::EXTLOAD, MVT::i1, Promote);
56 setOperationAction(ISD::EXTLOAD, MVT::f32, Expand);
58 setOperationAction(ISD::ZEXTLOAD, MVT::i1, Promote);
59 setOperationAction(ISD::ZEXTLOAD, MVT::i32, Expand);
61 setOperationAction(ISD::SEXTLOAD, MVT::i1, Promote);
62 setOperationAction(ISD::SEXTLOAD, MVT::i8, Expand);
63 setOperationAction(ISD::SEXTLOAD, MVT::i16, Expand);
65 setOperationAction(ISD::TRUNCSTORE, MVT::i1, Promote);
67 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1, Expand);
69 setOperationAction(ISD::FREM, MVT::f32, Expand);
70 setOperationAction(ISD::FREM, MVT::f64, Expand);
72 setOperationAction(ISD::UINT_TO_FP, MVT::i64, Expand);
73 setOperationAction(ISD::SINT_TO_FP, MVT::i64, Custom);
74 setOperationAction(ISD::FP_TO_UINT, MVT::i64, Expand);
75 setOperationAction(ISD::FP_TO_SINT, MVT::i64, Custom);
77 if (!TM.getSubtarget<AlphaSubtarget>().hasCT()) {
78 setOperationAction(ISD::CTPOP , MVT::i64 , Expand);
79 setOperationAction(ISD::CTTZ , MVT::i64 , Expand);
80 setOperationAction(ISD::CTLZ , MVT::i64 , Expand);
82 setOperationAction(ISD::BSWAP , MVT::i64, Expand);
83 setOperationAction(ISD::ROTL , MVT::i64, Expand);
84 setOperationAction(ISD::ROTR , MVT::i64, Expand);
86 setOperationAction(ISD::SREM , MVT::i64, Custom);
87 setOperationAction(ISD::UREM , MVT::i64, Custom);
88 setOperationAction(ISD::SDIV , MVT::i64, Custom);
89 setOperationAction(ISD::UDIV , MVT::i64, Custom);
91 setOperationAction(ISD::MEMMOVE , MVT::Other, Expand);
92 setOperationAction(ISD::MEMSET , MVT::Other, Expand);
93 setOperationAction(ISD::MEMCPY , MVT::Other, Expand);
95 // We don't support sin/cos/sqrt
96 setOperationAction(ISD::FSIN , MVT::f64, Expand);
97 setOperationAction(ISD::FCOS , MVT::f64, Expand);
98 setOperationAction(ISD::FSIN , MVT::f32, Expand);
99 setOperationAction(ISD::FCOS , MVT::f32, Expand);
101 setOperationAction(ISD::FSQRT, MVT::f64, Expand);
102 setOperationAction(ISD::FSQRT, MVT::f32, Expand);
104 setOperationAction(ISD::SETCC, MVT::f32, Promote);
106 // We don't have line number support yet.
107 setOperationAction(ISD::LOCATION, MVT::Other, Expand);
108 setOperationAction(ISD::DEBUG_LOC, MVT::Other, Expand);
109 setOperationAction(ISD::DEBUG_LABEL, MVT::Other, Expand);
111 // Not implemented yet.
112 setOperationAction(ISD::STACKSAVE, MVT::Other, Expand);
113 setOperationAction(ISD::STACKRESTORE, MVT::Other, Expand);
114 setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i64, Expand);
116 // We want to legalize GlobalAddress and ConstantPool and
117 // ExternalSymbols nodes into the appropriate instructions to
118 // materialize the address.
119 setOperationAction(ISD::GlobalAddress, MVT::i64, Custom);
120 setOperationAction(ISD::ConstantPool, MVT::i64, Custom);
121 setOperationAction(ISD::ExternalSymbol, MVT::i64, Custom);
123 setOperationAction(ISD::VASTART, MVT::Other, Custom);
124 setOperationAction(ISD::VAEND, MVT::Other, Expand);
125 setOperationAction(ISD::VACOPY, MVT::Other, Custom);
126 setOperationAction(ISD::VAARG, MVT::Other, Custom);
127 setOperationAction(ISD::VAARG, MVT::i32, Custom);
129 setOperationAction(ISD::RET, MVT::Other, Custom);
131 setStackPointerRegisterToSaveRestore(Alpha::R30);
133 setOperationAction(ISD::ConstantFP, MVT::f64, Expand);
134 setOperationAction(ISD::ConstantFP, MVT::f32, Expand);
135 addLegalFPImmediate(+0.0); //F31
136 addLegalFPImmediate(-0.0); //-F31
139 setJumpBufAlignment(16);
141 computeRegisterProperties();
143 useITOF = TM.getSubtarget<AlphaSubtarget>().hasF2I();
146 const char *AlphaTargetLowering::getTargetNodeName(unsigned Opcode) const {
149 case AlphaISD::ITOFT_: return "Alpha::ITOFT_";
150 case AlphaISD::FTOIT_: return "Alpha::FTOIT_";
151 case AlphaISD::CVTQT_: return "Alpha::CVTQT_";
152 case AlphaISD::CVTQS_: return "Alpha::CVTQS_";
153 case AlphaISD::CVTTQ_: return "Alpha::CVTTQ_";
154 case AlphaISD::GPRelHi: return "Alpha::GPRelHi";
155 case AlphaISD::GPRelLo: return "Alpha::GPRelLo";
156 case AlphaISD::RelLit: return "Alpha::RelLit";
157 case AlphaISD::GlobalBaseReg: return "Alpha::GlobalBaseReg";
158 case AlphaISD::GlobalRetAddr: return "Alpha::GlobalRetAddr";
159 case AlphaISD::CALL: return "Alpha::CALL";
160 case AlphaISD::DivCall: return "Alpha::DivCall";
161 case AlphaISD::RET_FLAG: return "Alpha::RET_FLAG";
165 //http://www.cs.arizona.edu/computer.help/policy/DIGITAL_unix/
166 //AA-PY8AC-TET1_html/callCH3.html#BLOCK21
168 //For now, just use variable size stack frame format
170 //In a standard call, the first six items are passed in registers $16
171 //- $21 and/or registers $f16 - $f21. (See Section 4.1.2 for details
172 //of argument-to-register correspondence.) The remaining items are
173 //collected in a memory argument list that is a naturally aligned
174 //array of quadwords. In a standard call, this list, if present, must
175 //be passed at 0(SP).
176 //7 ... n 0(SP) ... (n-7)*8(SP)
184 static SDOperand LowerFORMAL_ARGUMENTS(SDOperand Op, SelectionDAG &DAG,
189 MachineFunction &MF = DAG.getMachineFunction();
190 MachineFrameInfo *MFI = MF.getFrameInfo();
191 SSARegMap *RegMap = MF.getSSARegMap();
192 std::vector<SDOperand> ArgValues;
193 SDOperand Root = Op.getOperand(0);
195 GP = AddLiveIn(MF, Alpha::R29, &Alpha::GPRCRegClass);
196 RA = AddLiveIn(MF, Alpha::R26, &Alpha::GPRCRegClass);
198 unsigned args_int[] = {
199 Alpha::R16, Alpha::R17, Alpha::R18, Alpha::R19, Alpha::R20, Alpha::R21};
200 unsigned args_float[] = {
201 Alpha::F16, Alpha::F17, Alpha::F18, Alpha::F19, Alpha::F20, Alpha::F21};
203 for (unsigned ArgNo = 0, e = Op.Val->getNumValues()-1; ArgNo != e; ++ArgNo) {
205 MVT::ValueType ObjectVT = Op.getValue(ArgNo).getValueType();
212 std::cerr << "Unknown Type " << ObjectVT << "\n";
215 args_float[ArgNo] = AddLiveIn(MF, args_float[ArgNo],
216 &Alpha::F8RCRegClass);
217 ArgVal = DAG.getCopyFromReg(Root, args_float[ArgNo], ObjectVT);
220 args_float[ArgNo] = AddLiveIn(MF, args_float[ArgNo],
221 &Alpha::F4RCRegClass);
222 ArgVal = DAG.getCopyFromReg(Root, args_float[ArgNo], ObjectVT);
225 args_int[ArgNo] = AddLiveIn(MF, args_int[ArgNo],
226 &Alpha::GPRCRegClass);
227 ArgVal = DAG.getCopyFromReg(Root, args_int[ArgNo], MVT::i64);
231 // Create the frame index object for this incoming parameter...
232 int FI = MFI->CreateFixedObject(8, 8 * (ArgNo - 6));
234 // Create the SelectionDAG nodes corresponding to a load
235 //from this parameter
236 SDOperand FIN = DAG.getFrameIndex(FI, MVT::i64);
237 ArgVal = DAG.getLoad(ObjectVT, Root, FIN, DAG.getSrcValue(NULL));
239 ArgValues.push_back(ArgVal);
242 // If the functions takes variable number of arguments, copy all regs to stack
243 bool isVarArg = cast<ConstantSDNode>(Op.getOperand(2))->getValue() != 0;
245 VarArgsOffset = (Op.Val->getNumValues()-1) * 8;
246 std::vector<SDOperand> LS;
247 for (int i = 0; i < 6; ++i) {
248 if (MRegisterInfo::isPhysicalRegister(args_int[i]))
249 args_int[i] = AddLiveIn(MF, args_int[i], &Alpha::GPRCRegClass);
250 SDOperand argt = DAG.getCopyFromReg(Root, args_int[i], MVT::i64);
251 int FI = MFI->CreateFixedObject(8, -8 * (6 - i));
252 if (i == 0) VarArgsBase = FI;
253 SDOperand SDFI = DAG.getFrameIndex(FI, MVT::i64);
254 LS.push_back(DAG.getNode(ISD::STORE, MVT::Other, Root, argt,
255 SDFI, DAG.getSrcValue(NULL)));
257 if (MRegisterInfo::isPhysicalRegister(args_float[i]))
258 args_float[i] = AddLiveIn(MF, args_float[i], &Alpha::F8RCRegClass);
259 argt = DAG.getCopyFromReg(Root, args_float[i], MVT::f64);
260 FI = MFI->CreateFixedObject(8, - 8 * (12 - i));
261 SDFI = DAG.getFrameIndex(FI, MVT::i64);
262 LS.push_back(DAG.getNode(ISD::STORE, MVT::Other, Root, argt,
263 SDFI, DAG.getSrcValue(NULL)));
266 //Set up a token factor with all the stack traffic
267 Root = DAG.getNode(ISD::TokenFactor, MVT::Other, &LS[0], LS.size());
270 ArgValues.push_back(Root);
272 // Return the new list of results.
273 std::vector<MVT::ValueType> RetVT(Op.Val->value_begin(),
274 Op.Val->value_end());
275 return DAG.getNode(ISD::MERGE_VALUES, RetVT, &ArgValues[0], ArgValues.size());
278 static SDOperand LowerRET(SDOperand Op, SelectionDAG &DAG, unsigned int RA) {
279 SDOperand Copy = DAG.getCopyToReg(Op.getOperand(0), Alpha::R26,
280 DAG.getNode(AlphaISD::GlobalRetAddr,
283 switch (Op.getNumOperands()) {
285 assert(0 && "Do not know how to return this many arguments!");
289 //return SDOperand(); // ret void is legal
291 MVT::ValueType ArgVT = Op.getOperand(1).getValueType();
293 if (MVT::isInteger(ArgVT))
296 assert(MVT::isFloatingPoint(ArgVT));
299 Copy = DAG.getCopyToReg(Copy, ArgReg, Op.getOperand(1), Copy.getValue(1));
300 if(DAG.getMachineFunction().liveout_empty())
301 DAG.getMachineFunction().addLiveOut(ArgReg);
305 return DAG.getNode(AlphaISD::RET_FLAG, MVT::Other, Copy, Copy.getValue(1));
308 std::pair<SDOperand, SDOperand>
309 AlphaTargetLowering::LowerCallTo(SDOperand Chain,
310 const Type *RetTy, bool isVarArg,
311 unsigned CallingConv, bool isTailCall,
312 SDOperand Callee, ArgListTy &Args,
316 NumBytes = (Args.size() - 6) * 8;
318 Chain = DAG.getCALLSEQ_START(Chain,
319 DAG.getConstant(NumBytes, getPointerTy()));
320 std::vector<SDOperand> args_to_use;
321 for (unsigned i = 0, e = Args.size(); i != e; ++i)
323 switch (getValueType(Args[i].second)) {
324 default: assert(0 && "Unexpected ValueType for argument!");
329 // Promote the integer to 64 bits. If the input type is signed use a
330 // sign extend, otherwise use a zero extend.
331 if (Args[i].second->isSigned())
332 Args[i].first = DAG.getNode(ISD::SIGN_EXTEND, MVT::i64, Args[i].first);
334 Args[i].first = DAG.getNode(ISD::ZERO_EXTEND, MVT::i64, Args[i].first);
341 args_to_use.push_back(Args[i].first);
344 std::vector<MVT::ValueType> RetVals;
345 MVT::ValueType RetTyVT = getValueType(RetTy);
346 MVT::ValueType ActualRetTyVT = RetTyVT;
347 if (RetTyVT >= MVT::i1 && RetTyVT <= MVT::i32)
348 ActualRetTyVT = MVT::i64;
350 if (RetTyVT != MVT::isVoid)
351 RetVals.push_back(ActualRetTyVT);
352 RetVals.push_back(MVT::Other);
354 std::vector<SDOperand> Ops;
355 Ops.push_back(Chain);
356 Ops.push_back(Callee);
357 Ops.insert(Ops.end(), args_to_use.begin(), args_to_use.end());
358 SDOperand TheCall = DAG.getNode(AlphaISD::CALL, RetVals, &Ops[0], Ops.size());
359 Chain = TheCall.getValue(RetTyVT != MVT::isVoid);
360 Chain = DAG.getNode(ISD::CALLSEQ_END, MVT::Other, Chain,
361 DAG.getConstant(NumBytes, getPointerTy()));
362 SDOperand RetVal = TheCall;
364 if (RetTyVT != ActualRetTyVT) {
365 RetVal = DAG.getNode(RetTy->isSigned() ? ISD::AssertSext : ISD::AssertZext,
366 MVT::i64, RetVal, DAG.getValueType(RetTyVT));
367 RetVal = DAG.getNode(ISD::TRUNCATE, RetTyVT, RetVal);
370 return std::make_pair(RetVal, Chain);
373 void AlphaTargetLowering::restoreGP(MachineBasicBlock* BB)
375 BuildMI(BB, Alpha::BIS, 2, Alpha::R29).addReg(GP).addReg(GP);
377 void AlphaTargetLowering::restoreRA(MachineBasicBlock* BB)
379 BuildMI(BB, Alpha::BIS, 2, Alpha::R26).addReg(RA).addReg(RA);
388 /// LowerOperation - Provide custom lowering hooks for some operations.
390 SDOperand AlphaTargetLowering::LowerOperation(SDOperand Op, SelectionDAG &DAG) {
391 switch (Op.getOpcode()) {
392 default: assert(0 && "Wasn't expecting to be able to lower this!");
393 case ISD::FORMAL_ARGUMENTS: return LowerFORMAL_ARGUMENTS(Op, DAG,
397 case ISD::RET: return LowerRET(Op,DAG, getVRegRA());
398 case ISD::SINT_TO_FP: {
399 assert(MVT::i64 == Op.getOperand(0).getValueType() &&
400 "Unhandled SINT_TO_FP type in custom expander!");
402 bool isDouble = MVT::f64 == Op.getValueType();
404 LD = DAG.getNode(AlphaISD::ITOFT_, MVT::f64, Op.getOperand(0));
407 DAG.getMachineFunction().getFrameInfo()->CreateStackObject(8, 8);
408 SDOperand FI = DAG.getFrameIndex(FrameIdx, MVT::i64);
409 SDOperand ST = DAG.getNode(ISD::STORE, MVT::Other, DAG.getEntryNode(),
410 Op.getOperand(0), FI, DAG.getSrcValue(0));
411 LD = DAG.getLoad(MVT::f64, ST, FI, DAG.getSrcValue(0));
413 SDOperand FP = DAG.getNode(isDouble?AlphaISD::CVTQT_:AlphaISD::CVTQS_,
414 isDouble?MVT::f64:MVT::f32, LD);
417 case ISD::FP_TO_SINT: {
418 bool isDouble = MVT::f64 == Op.getOperand(0).getValueType();
419 SDOperand src = Op.getOperand(0);
421 if (!isDouble) //Promote
422 src = DAG.getNode(ISD::FP_EXTEND, MVT::f64, src);
424 src = DAG.getNode(AlphaISD::CVTTQ_, MVT::f64, src);
427 return DAG.getNode(AlphaISD::FTOIT_, MVT::i64, src);
430 DAG.getMachineFunction().getFrameInfo()->CreateStackObject(8, 8);
431 SDOperand FI = DAG.getFrameIndex(FrameIdx, MVT::i64);
432 SDOperand ST = DAG.getNode(ISD::STORE, MVT::Other, DAG.getEntryNode(),
433 src, FI, DAG.getSrcValue(0));
434 return DAG.getLoad(MVT::i64, ST, FI, DAG.getSrcValue(0));
437 case ISD::ConstantPool: {
438 ConstantPoolSDNode *CP = cast<ConstantPoolSDNode>(Op);
439 Constant *C = CP->get();
440 SDOperand CPI = DAG.getTargetConstantPool(C, MVT::i64, CP->getAlignment());
442 SDOperand Hi = DAG.getNode(AlphaISD::GPRelHi, MVT::i64, CPI,
443 DAG.getNode(AlphaISD::GlobalBaseReg, MVT::i64));
444 SDOperand Lo = DAG.getNode(AlphaISD::GPRelLo, MVT::i64, CPI, Hi);
447 case ISD::GlobalAddress: {
448 GlobalAddressSDNode *GSDN = cast<GlobalAddressSDNode>(Op);
449 GlobalValue *GV = GSDN->getGlobal();
450 SDOperand GA = DAG.getTargetGlobalAddress(GV, MVT::i64, GSDN->getOffset());
452 // if (!GV->hasWeakLinkage() && !GV->isExternal() && !GV->hasLinkOnceLinkage()) {
453 if (GV->hasInternalLinkage()) {
454 SDOperand Hi = DAG.getNode(AlphaISD::GPRelHi, MVT::i64, GA,
455 DAG.getNode(AlphaISD::GlobalBaseReg, MVT::i64));
456 SDOperand Lo = DAG.getNode(AlphaISD::GPRelLo, MVT::i64, GA, Hi);
459 return DAG.getNode(AlphaISD::RelLit, MVT::i64, GA, DAG.getNode(AlphaISD::GlobalBaseReg, MVT::i64));
461 case ISD::ExternalSymbol: {
462 return DAG.getNode(AlphaISD::RelLit, MVT::i64,
463 DAG.getTargetExternalSymbol(cast<ExternalSymbolSDNode>(Op)->getSymbol(), MVT::i64),
464 DAG.getNode(AlphaISD::GlobalBaseReg, MVT::i64));
469 //Expand only on constant case
470 if (Op.getOperand(1).getOpcode() == ISD::Constant) {
471 MVT::ValueType VT = Op.Val->getValueType(0);
472 unsigned Opc = Op.Val->getOpcode() == ISD::UREM ? ISD::UDIV : ISD::SDIV;
473 SDOperand Tmp1 = Op.Val->getOpcode() == ISD::UREM ?
474 BuildUDIV(Op.Val, DAG, NULL) :
475 BuildSDIV(Op.Val, DAG, NULL);
476 Tmp1 = DAG.getNode(ISD::MUL, VT, Tmp1, Op.getOperand(1));
477 Tmp1 = DAG.getNode(ISD::SUB, VT, Op.getOperand(0), Tmp1);
483 if (MVT::isInteger(Op.getValueType())) {
484 if (Op.getOperand(1).getOpcode() == ISD::Constant)
485 return Op.getOpcode() == ISD::SDIV ? BuildSDIV(Op.Val, DAG, NULL)
486 : BuildUDIV(Op.Val, DAG, NULL);
487 const char* opstr = 0;
488 switch(Op.getOpcode()) {
489 case ISD::UREM: opstr = "__remqu"; break;
490 case ISD::SREM: opstr = "__remq"; break;
491 case ISD::UDIV: opstr = "__divqu"; break;
492 case ISD::SDIV: opstr = "__divq"; break;
494 SDOperand Tmp1 = Op.getOperand(0),
495 Tmp2 = Op.getOperand(1),
496 Addr = DAG.getExternalSymbol(opstr, MVT::i64);
497 return DAG.getNode(AlphaISD::DivCall, MVT::i64, Addr, Tmp1, Tmp2);
502 SDOperand Chain = Op.getOperand(0);
503 SDOperand VAListP = Op.getOperand(1);
504 SDOperand VAListS = Op.getOperand(2);
506 SDOperand Base = DAG.getLoad(MVT::i64, Chain, VAListP, VAListS);
507 SDOperand Tmp = DAG.getNode(ISD::ADD, MVT::i64, VAListP,
508 DAG.getConstant(8, MVT::i64));
509 SDOperand Offset = DAG.getExtLoad(ISD::SEXTLOAD, MVT::i64, Base.getValue(1),
510 Tmp, DAG.getSrcValue(0), MVT::i32);
511 SDOperand DataPtr = DAG.getNode(ISD::ADD, MVT::i64, Base, Offset);
512 if (MVT::isFloatingPoint(Op.getValueType()))
514 //if fp && Offset < 6*8, then subtract 6*8 from DataPtr
515 SDOperand FPDataPtr = DAG.getNode(ISD::SUB, MVT::i64, DataPtr,
516 DAG.getConstant(8*6, MVT::i64));
517 SDOperand CC = DAG.getSetCC(MVT::i64, Offset,
518 DAG.getConstant(8*6, MVT::i64), ISD::SETLT);
519 DataPtr = DAG.getNode(ISD::SELECT, MVT::i64, CC, FPDataPtr, DataPtr);
522 SDOperand NewOffset = DAG.getNode(ISD::ADD, MVT::i64, Offset,
523 DAG.getConstant(8, MVT::i64));
524 SDOperand Update = DAG.getNode(ISD::TRUNCSTORE, MVT::Other,
525 Offset.getValue(1), NewOffset,
526 Tmp, DAG.getSrcValue(0),
527 DAG.getValueType(MVT::i32));
530 if (Op.getValueType() == MVT::i32)
531 Result = DAG.getExtLoad(ISD::SEXTLOAD, MVT::i64, Update, DataPtr,
532 DAG.getSrcValue(0), MVT::i32);
534 Result = DAG.getLoad(Op.getValueType(), Update, DataPtr,
539 SDOperand Chain = Op.getOperand(0);
540 SDOperand DestP = Op.getOperand(1);
541 SDOperand SrcP = Op.getOperand(2);
542 SDOperand DestS = Op.getOperand(3);
543 SDOperand SrcS = Op.getOperand(4);
545 SDOperand Val = DAG.getLoad(getPointerTy(), Chain, SrcP, SrcS);
546 SDOperand Result = DAG.getNode(ISD::STORE, MVT::Other, Val.getValue(1), Val,
548 SDOperand NP = DAG.getNode(ISD::ADD, MVT::i64, SrcP,
549 DAG.getConstant(8, MVT::i64));
550 Val = DAG.getExtLoad(ISD::SEXTLOAD, MVT::i64, Result, NP,
551 DAG.getSrcValue(0), MVT::i32);
552 SDOperand NPD = DAG.getNode(ISD::ADD, MVT::i64, DestP,
553 DAG.getConstant(8, MVT::i64));
554 return DAG.getNode(ISD::TRUNCSTORE, MVT::Other, Val.getValue(1),
555 Val, NPD, DAG.getSrcValue(0),DAG.getValueType(MVT::i32));
558 SDOperand Chain = Op.getOperand(0);
559 SDOperand VAListP = Op.getOperand(1);
560 SDOperand VAListS = Op.getOperand(2);
562 // vastart stores the address of the VarArgsBase and VarArgsOffset
563 SDOperand FR = DAG.getFrameIndex(VarArgsBase, MVT::i64);
564 SDOperand S1 = DAG.getNode(ISD::STORE, MVT::Other, Chain, FR, VAListP,
566 SDOperand SA2 = DAG.getNode(ISD::ADD, MVT::i64, VAListP,
567 DAG.getConstant(8, MVT::i64));
568 return DAG.getNode(ISD::TRUNCSTORE, MVT::Other, S1,
569 DAG.getConstant(VarArgsOffset, MVT::i64), SA2,
570 DAG.getSrcValue(0), DAG.getValueType(MVT::i32));
577 SDOperand AlphaTargetLowering::CustomPromoteOperation(SDOperand Op,
579 assert(Op.getValueType() == MVT::i32 &&
580 Op.getOpcode() == ISD::VAARG &&
581 "Unknown node to custom promote!");
583 // The code in LowerOperation already handles i32 vaarg
584 return LowerOperation(Op, DAG);
590 /// getConstraintType - Given a constraint letter, return the type of
591 /// constraint it is for this target.
592 AlphaTargetLowering::ConstraintType
593 AlphaTargetLowering::getConstraintType(char ConstraintLetter) const {
594 switch (ConstraintLetter) {
598 return C_RegisterClass;
600 return TargetLowering::getConstraintType(ConstraintLetter);
603 std::vector<unsigned> AlphaTargetLowering::
604 getRegClassForInlineAsmConstraint(const std::string &Constraint,
605 MVT::ValueType VT) const {
606 if (Constraint.size() == 1) {
607 switch (Constraint[0]) {
608 default: break; // Unknown constriant letter
610 return make_vector<unsigned>(Alpha::F0 , Alpha::F1 , Alpha::F2 ,
611 Alpha::F3 , Alpha::F4 , Alpha::F5 ,
612 Alpha::F6 , Alpha::F7 , Alpha::F8 ,
613 Alpha::F9 , Alpha::F10, Alpha::F11,
614 Alpha::F12, Alpha::F13, Alpha::F14,
615 Alpha::F15, Alpha::F16, Alpha::F17,
616 Alpha::F18, Alpha::F19, Alpha::F20,
617 Alpha::F21, Alpha::F22, Alpha::F23,
618 Alpha::F24, Alpha::F25, Alpha::F26,
619 Alpha::F27, Alpha::F28, Alpha::F29,
620 Alpha::F30, Alpha::F31, 0);
622 return make_vector<unsigned>(Alpha::R0 , Alpha::R1 , Alpha::R2 ,
623 Alpha::R3 , Alpha::R4 , Alpha::R5 ,
624 Alpha::R6 , Alpha::R7 , Alpha::R8 ,
625 Alpha::R9 , Alpha::R10, Alpha::R11,
626 Alpha::R12, Alpha::R13, Alpha::R14,
627 Alpha::R15, Alpha::R16, Alpha::R17,
628 Alpha::R18, Alpha::R19, Alpha::R20,
629 Alpha::R21, Alpha::R22, Alpha::R23,
630 Alpha::R24, Alpha::R25, Alpha::R26,
631 Alpha::R27, Alpha::R28, Alpha::R29,
632 Alpha::R30, Alpha::R31, 0);
637 return std::vector<unsigned>();