1 //===-- AlphaISelLowering.cpp - Alpha DAG Lowering Implementation ---------===//
3 // The LLVM Compiler Infrastructure
5 // This file was developed by Andrew Lenharth and is distributed under
6 // the University of Illinois Open Source License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file implements the AlphaISelLowering class.
12 //===----------------------------------------------------------------------===//
14 #include "AlphaISelLowering.h"
15 #include "AlphaTargetMachine.h"
16 #include "llvm/CodeGen/MachineFrameInfo.h"
17 #include "llvm/CodeGen/MachineFunction.h"
18 #include "llvm/CodeGen/MachineInstrBuilder.h"
19 #include "llvm/CodeGen/SelectionDAG.h"
20 #include "llvm/CodeGen/SSARegMap.h"
21 #include "llvm/Constants.h"
22 #include "llvm/Function.h"
23 #include "llvm/Module.h"
24 #include "llvm/Support/CommandLine.h"
27 /// AddLiveIn - This helper function adds the specified physical register to the
28 /// MachineFunction as a live in value. It also creates a corresponding virtual
30 static unsigned AddLiveIn(MachineFunction &MF, unsigned PReg,
31 TargetRegisterClass *RC) {
32 assert(RC->contains(PReg) && "Not the correct regclass!");
33 unsigned VReg = MF.getSSARegMap()->createVirtualRegister(RC);
34 MF.addLiveIn(PReg, VReg);
38 AlphaTargetLowering::AlphaTargetLowering(TargetMachine &TM) : TargetLowering(TM) {
39 // Set up the TargetLowering object.
40 //I am having problems with shr n ubyte 1
41 setShiftAmountType(MVT::i64);
42 setSetCCResultType(MVT::i64);
43 setSetCCResultContents(ZeroOrOneSetCCResult);
45 setUsesGlobalOffsetTable(true);
47 addRegisterClass(MVT::i64, Alpha::GPRCRegisterClass);
48 addRegisterClass(MVT::f64, Alpha::F8RCRegisterClass);
49 addRegisterClass(MVT::f32, Alpha::F4RCRegisterClass);
51 setLoadXAction(ISD::EXTLOAD, MVT::i1, Promote);
52 setLoadXAction(ISD::EXTLOAD, MVT::f32, Expand);
54 setLoadXAction(ISD::ZEXTLOAD, MVT::i1, Promote);
55 setLoadXAction(ISD::ZEXTLOAD, MVT::i32, Expand);
57 setLoadXAction(ISD::SEXTLOAD, MVT::i1, Promote);
58 setLoadXAction(ISD::SEXTLOAD, MVT::i8, Expand);
59 setLoadXAction(ISD::SEXTLOAD, MVT::i16, Expand);
61 setStoreXAction(MVT::i1, Promote);
63 // setOperationAction(ISD::BRIND, MVT::Other, Expand);
64 setOperationAction(ISD::BR_JT, MVT::Other, Expand);
65 setOperationAction(ISD::BR_CC, MVT::Other, Expand);
66 setOperationAction(ISD::SELECT_CC, MVT::Other, Expand);
68 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1, Expand);
70 setOperationAction(ISD::FREM, MVT::f32, Expand);
71 setOperationAction(ISD::FREM, MVT::f64, Expand);
73 setOperationAction(ISD::UINT_TO_FP, MVT::i64, Expand);
74 setOperationAction(ISD::SINT_TO_FP, MVT::i64, Custom);
75 setOperationAction(ISD::FP_TO_UINT, MVT::i64, Expand);
76 setOperationAction(ISD::FP_TO_SINT, MVT::i64, Custom);
78 if (!TM.getSubtarget<AlphaSubtarget>().hasCT()) {
79 setOperationAction(ISD::CTPOP , MVT::i64 , Expand);
80 setOperationAction(ISD::CTTZ , MVT::i64 , Expand);
81 setOperationAction(ISD::CTLZ , MVT::i64 , Expand);
83 setOperationAction(ISD::BSWAP , MVT::i64, Expand);
84 setOperationAction(ISD::ROTL , MVT::i64, Expand);
85 setOperationAction(ISD::ROTR , MVT::i64, Expand);
87 setOperationAction(ISD::SREM , MVT::i64, Custom);
88 setOperationAction(ISD::UREM , MVT::i64, Custom);
89 setOperationAction(ISD::SDIV , MVT::i64, Custom);
90 setOperationAction(ISD::UDIV , MVT::i64, Custom);
92 setOperationAction(ISD::MEMMOVE , MVT::Other, Expand);
93 setOperationAction(ISD::MEMSET , MVT::Other, Expand);
94 setOperationAction(ISD::MEMCPY , MVT::Other, Expand);
96 // We don't support sin/cos/sqrt
97 setOperationAction(ISD::FSIN , MVT::f64, Expand);
98 setOperationAction(ISD::FCOS , MVT::f64, Expand);
99 setOperationAction(ISD::FSIN , MVT::f32, Expand);
100 setOperationAction(ISD::FCOS , MVT::f32, Expand);
102 setOperationAction(ISD::FSQRT, MVT::f64, Expand);
103 setOperationAction(ISD::FSQRT, MVT::f32, Expand);
105 setOperationAction(ISD::SETCC, MVT::f32, Promote);
107 setOperationAction(ISD::BIT_CONVERT, MVT::f32, Promote);
109 // We don't have line number support yet.
110 setOperationAction(ISD::LOCATION, MVT::Other, Expand);
111 setOperationAction(ISD::DEBUG_LOC, MVT::Other, Expand);
112 setOperationAction(ISD::LABEL, MVT::Other, Expand);
114 // Not implemented yet.
115 setOperationAction(ISD::STACKSAVE, MVT::Other, Expand);
116 setOperationAction(ISD::STACKRESTORE, MVT::Other, Expand);
117 setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i64, Expand);
119 // We want to legalize GlobalAddress and ConstantPool and
120 // ExternalSymbols nodes into the appropriate instructions to
121 // materialize the address.
122 setOperationAction(ISD::GlobalAddress, MVT::i64, Custom);
123 setOperationAction(ISD::ConstantPool, MVT::i64, Custom);
124 setOperationAction(ISD::ExternalSymbol, MVT::i64, Custom);
126 setOperationAction(ISD::VASTART, MVT::Other, Custom);
127 setOperationAction(ISD::VAEND, MVT::Other, Expand);
128 setOperationAction(ISD::VACOPY, MVT::Other, Custom);
129 setOperationAction(ISD::VAARG, MVT::Other, Custom);
130 setOperationAction(ISD::VAARG, MVT::i32, Custom);
132 setOperationAction(ISD::RET, MVT::Other, Custom);
134 setOperationAction(ISD::JumpTable, MVT::i64, Custom);
135 setOperationAction(ISD::JumpTable, MVT::i32, Custom);
137 setStackPointerRegisterToSaveRestore(Alpha::R30);
139 setOperationAction(ISD::ConstantFP, MVT::f64, Expand);
140 setOperationAction(ISD::ConstantFP, MVT::f32, Expand);
141 addLegalFPImmediate(+0.0); //F31
142 addLegalFPImmediate(-0.0); //-F31
145 setJumpBufAlignment(16);
147 computeRegisterProperties();
150 const char *AlphaTargetLowering::getTargetNodeName(unsigned Opcode) const {
153 case AlphaISD::CVTQT_: return "Alpha::CVTQT_";
154 case AlphaISD::CVTQS_: return "Alpha::CVTQS_";
155 case AlphaISD::CVTTQ_: return "Alpha::CVTTQ_";
156 case AlphaISD::GPRelHi: return "Alpha::GPRelHi";
157 case AlphaISD::GPRelLo: return "Alpha::GPRelLo";
158 case AlphaISD::RelLit: return "Alpha::RelLit";
159 case AlphaISD::GlobalRetAddr: return "Alpha::GlobalRetAddr";
160 case AlphaISD::CALL: return "Alpha::CALL";
161 case AlphaISD::DivCall: return "Alpha::DivCall";
162 case AlphaISD::RET_FLAG: return "Alpha::RET_FLAG";
163 case AlphaISD::COND_BRANCH_I: return "Alpha::COND_BRANCH_I";
164 case AlphaISD::COND_BRANCH_F: return "Alpha::COND_BRANCH_F";
168 static SDOperand LowerJumpTable(SDOperand Op, SelectionDAG &DAG) {
169 MVT::ValueType PtrVT = Op.getValueType();
170 JumpTableSDNode *JT = cast<JumpTableSDNode>(Op);
171 SDOperand JTI = DAG.getTargetJumpTable(JT->getIndex(), PtrVT);
172 SDOperand Zero = DAG.getConstant(0, PtrVT);
174 SDOperand Hi = DAG.getNode(AlphaISD::GPRelHi, MVT::i64, JTI,
175 DAG.getNode(ISD::GLOBAL_OFFSET_TABLE, MVT::i64));
176 SDOperand Lo = DAG.getNode(AlphaISD::GPRelLo, MVT::i64, JTI, Hi);
180 //http://www.cs.arizona.edu/computer.help/policy/DIGITAL_unix/
181 //AA-PY8AC-TET1_html/callCH3.html#BLOCK21
183 //For now, just use variable size stack frame format
185 //In a standard call, the first six items are passed in registers $16
186 //- $21 and/or registers $f16 - $f21. (See Section 4.1.2 for details
187 //of argument-to-register correspondence.) The remaining items are
188 //collected in a memory argument list that is a naturally aligned
189 //array of quadwords. In a standard call, this list, if present, must
190 //be passed at 0(SP).
191 //7 ... n 0(SP) ... (n-7)*8(SP)
199 static SDOperand LowerFORMAL_ARGUMENTS(SDOperand Op, SelectionDAG &DAG,
201 int &VarArgsOffset) {
202 MachineFunction &MF = DAG.getMachineFunction();
203 MachineFrameInfo *MFI = MF.getFrameInfo();
204 std::vector<SDOperand> ArgValues;
205 SDOperand Root = Op.getOperand(0);
207 AddLiveIn(MF, Alpha::R29, &Alpha::GPRCRegClass); //GP
208 AddLiveIn(MF, Alpha::R26, &Alpha::GPRCRegClass); //RA
210 unsigned args_int[] = {
211 Alpha::R16, Alpha::R17, Alpha::R18, Alpha::R19, Alpha::R20, Alpha::R21};
212 unsigned args_float[] = {
213 Alpha::F16, Alpha::F17, Alpha::F18, Alpha::F19, Alpha::F20, Alpha::F21};
215 for (unsigned ArgNo = 0, e = Op.Val->getNumValues()-1; ArgNo != e; ++ArgNo) {
217 MVT::ValueType ObjectVT = Op.getValue(ArgNo).getValueType();
223 cerr << "Unknown Type " << ObjectVT << "\n";
226 args_float[ArgNo] = AddLiveIn(MF, args_float[ArgNo],
227 &Alpha::F8RCRegClass);
228 ArgVal = DAG.getCopyFromReg(Root, args_float[ArgNo], ObjectVT);
231 args_float[ArgNo] = AddLiveIn(MF, args_float[ArgNo],
232 &Alpha::F4RCRegClass);
233 ArgVal = DAG.getCopyFromReg(Root, args_float[ArgNo], ObjectVT);
236 args_int[ArgNo] = AddLiveIn(MF, args_int[ArgNo],
237 &Alpha::GPRCRegClass);
238 ArgVal = DAG.getCopyFromReg(Root, args_int[ArgNo], MVT::i64);
242 // Create the frame index object for this incoming parameter...
243 int FI = MFI->CreateFixedObject(8, 8 * (ArgNo - 6));
245 // Create the SelectionDAG nodes corresponding to a load
246 //from this parameter
247 SDOperand FIN = DAG.getFrameIndex(FI, MVT::i64);
248 ArgVal = DAG.getLoad(ObjectVT, Root, FIN, NULL, 0);
250 ArgValues.push_back(ArgVal);
253 // If the functions takes variable number of arguments, copy all regs to stack
254 bool isVarArg = cast<ConstantSDNode>(Op.getOperand(2))->getValue() != 0;
256 VarArgsOffset = (Op.Val->getNumValues()-1) * 8;
257 std::vector<SDOperand> LS;
258 for (int i = 0; i < 6; ++i) {
259 if (MRegisterInfo::isPhysicalRegister(args_int[i]))
260 args_int[i] = AddLiveIn(MF, args_int[i], &Alpha::GPRCRegClass);
261 SDOperand argt = DAG.getCopyFromReg(Root, args_int[i], MVT::i64);
262 int FI = MFI->CreateFixedObject(8, -8 * (6 - i));
263 if (i == 0) VarArgsBase = FI;
264 SDOperand SDFI = DAG.getFrameIndex(FI, MVT::i64);
265 LS.push_back(DAG.getStore(Root, argt, SDFI, NULL, 0));
267 if (MRegisterInfo::isPhysicalRegister(args_float[i]))
268 args_float[i] = AddLiveIn(MF, args_float[i], &Alpha::F8RCRegClass);
269 argt = DAG.getCopyFromReg(Root, args_float[i], MVT::f64);
270 FI = MFI->CreateFixedObject(8, - 8 * (12 - i));
271 SDFI = DAG.getFrameIndex(FI, MVT::i64);
272 LS.push_back(DAG.getStore(Root, argt, SDFI, NULL, 0));
275 //Set up a token factor with all the stack traffic
276 Root = DAG.getNode(ISD::TokenFactor, MVT::Other, &LS[0], LS.size());
279 ArgValues.push_back(Root);
281 // Return the new list of results.
282 std::vector<MVT::ValueType> RetVT(Op.Val->value_begin(),
283 Op.Val->value_end());
284 return DAG.getNode(ISD::MERGE_VALUES, RetVT, &ArgValues[0], ArgValues.size());
287 static SDOperand LowerRET(SDOperand Op, SelectionDAG &DAG) {
288 SDOperand Copy = DAG.getCopyToReg(Op.getOperand(0), Alpha::R26,
289 DAG.getNode(AlphaISD::GlobalRetAddr,
292 switch (Op.getNumOperands()) {
294 assert(0 && "Do not know how to return this many arguments!");
298 //return SDOperand(); // ret void is legal
300 MVT::ValueType ArgVT = Op.getOperand(1).getValueType();
302 if (MVT::isInteger(ArgVT))
305 assert(MVT::isFloatingPoint(ArgVT));
308 Copy = DAG.getCopyToReg(Copy, ArgReg, Op.getOperand(1), Copy.getValue(1));
309 if (DAG.getMachineFunction().liveout_empty())
310 DAG.getMachineFunction().addLiveOut(ArgReg);
314 return DAG.getNode(AlphaISD::RET_FLAG, MVT::Other, Copy, Copy.getValue(1));
317 std::pair<SDOperand, SDOperand>
318 AlphaTargetLowering::LowerCallTo(SDOperand Chain, const Type *RetTy,
319 bool RetTyIsSigned, bool isVarArg,
320 unsigned CallingConv, bool isTailCall,
321 SDOperand Callee, ArgListTy &Args,
325 NumBytes = (Args.size() - 6) * 8;
327 Chain = DAG.getCALLSEQ_START(Chain,
328 DAG.getConstant(NumBytes, getPointerTy()));
329 std::vector<SDOperand> args_to_use;
330 for (unsigned i = 0, e = Args.size(); i != e; ++i)
332 switch (getValueType(Args[i].Ty)) {
333 default: assert(0 && "Unexpected ValueType for argument!");
338 // Promote the integer to 64 bits. If the input type is signed use a
339 // sign extend, otherwise use a zero extend.
341 Args[i].Node = DAG.getNode(ISD::SIGN_EXTEND, MVT::i64, Args[i].Node);
342 else if (Args[i].isZExt)
343 Args[i].Node = DAG.getNode(ISD::ZERO_EXTEND, MVT::i64, Args[i].Node);
345 Args[i].Node = DAG.getNode(ISD::ANY_EXTEND, MVT::i64, Args[i].Node);
352 args_to_use.push_back(Args[i].Node);
355 std::vector<MVT::ValueType> RetVals;
356 MVT::ValueType RetTyVT = getValueType(RetTy);
357 MVT::ValueType ActualRetTyVT = RetTyVT;
358 if (RetTyVT >= MVT::i1 && RetTyVT <= MVT::i32)
359 ActualRetTyVT = MVT::i64;
361 if (RetTyVT != MVT::isVoid)
362 RetVals.push_back(ActualRetTyVT);
363 RetVals.push_back(MVT::Other);
365 std::vector<SDOperand> Ops;
366 Ops.push_back(Chain);
367 Ops.push_back(Callee);
368 Ops.insert(Ops.end(), args_to_use.begin(), args_to_use.end());
369 SDOperand TheCall = DAG.getNode(AlphaISD::CALL, RetVals, &Ops[0], Ops.size());
370 Chain = TheCall.getValue(RetTyVT != MVT::isVoid);
371 Chain = DAG.getNode(ISD::CALLSEQ_END, MVT::Other, Chain,
372 DAG.getConstant(NumBytes, getPointerTy()));
373 SDOperand RetVal = TheCall;
375 if (RetTyVT != ActualRetTyVT) {
376 RetVal = DAG.getNode(RetTyIsSigned ? ISD::AssertSext : ISD::AssertZext,
377 MVT::i64, RetVal, DAG.getValueType(RetTyVT));
378 RetVal = DAG.getNode(ISD::TRUNCATE, RetTyVT, RetVal);
381 return std::make_pair(RetVal, Chain);
384 /// LowerOperation - Provide custom lowering hooks for some operations.
386 SDOperand AlphaTargetLowering::LowerOperation(SDOperand Op, SelectionDAG &DAG) {
387 switch (Op.getOpcode()) {
388 default: assert(0 && "Wasn't expecting to be able to lower this!");
389 case ISD::FORMAL_ARGUMENTS: return LowerFORMAL_ARGUMENTS(Op, DAG,
393 case ISD::RET: return LowerRET(Op,DAG);
394 case ISD::JumpTable: return LowerJumpTable(Op, DAG);
396 case ISD::SINT_TO_FP: {
397 assert(MVT::i64 == Op.getOperand(0).getValueType() &&
398 "Unhandled SINT_TO_FP type in custom expander!");
400 bool isDouble = MVT::f64 == Op.getValueType();
401 LD = DAG.getNode(ISD::BIT_CONVERT, MVT::f64, Op.getOperand(0));
402 SDOperand FP = DAG.getNode(isDouble?AlphaISD::CVTQT_:AlphaISD::CVTQS_,
403 isDouble?MVT::f64:MVT::f32, LD);
406 case ISD::FP_TO_SINT: {
407 bool isDouble = MVT::f64 == Op.getOperand(0).getValueType();
408 SDOperand src = Op.getOperand(0);
410 if (!isDouble) //Promote
411 src = DAG.getNode(ISD::FP_EXTEND, MVT::f64, src);
413 src = DAG.getNode(AlphaISD::CVTTQ_, MVT::f64, src);
415 return DAG.getNode(ISD::BIT_CONVERT, MVT::i64, src);
417 case ISD::ConstantPool: {
418 ConstantPoolSDNode *CP = cast<ConstantPoolSDNode>(Op);
419 Constant *C = CP->getConstVal();
420 SDOperand CPI = DAG.getTargetConstantPool(C, MVT::i64, CP->getAlignment());
422 SDOperand Hi = DAG.getNode(AlphaISD::GPRelHi, MVT::i64, CPI,
423 DAG.getNode(ISD::GLOBAL_OFFSET_TABLE, MVT::i64));
424 SDOperand Lo = DAG.getNode(AlphaISD::GPRelLo, MVT::i64, CPI, Hi);
427 case ISD::GlobalAddress: {
428 GlobalAddressSDNode *GSDN = cast<GlobalAddressSDNode>(Op);
429 GlobalValue *GV = GSDN->getGlobal();
430 SDOperand GA = DAG.getTargetGlobalAddress(GV, MVT::i64, GSDN->getOffset());
432 // if (!GV->hasWeakLinkage() && !GV->isDeclaration() && !GV->hasLinkOnceLinkage()) {
433 if (GV->hasInternalLinkage()) {
434 SDOperand Hi = DAG.getNode(AlphaISD::GPRelHi, MVT::i64, GA,
435 DAG.getNode(ISD::GLOBAL_OFFSET_TABLE, MVT::i64));
436 SDOperand Lo = DAG.getNode(AlphaISD::GPRelLo, MVT::i64, GA, Hi);
439 return DAG.getNode(AlphaISD::RelLit, MVT::i64, GA,
440 DAG.getNode(ISD::GLOBAL_OFFSET_TABLE, MVT::i64));
442 case ISD::ExternalSymbol: {
443 return DAG.getNode(AlphaISD::RelLit, MVT::i64,
444 DAG.getTargetExternalSymbol(cast<ExternalSymbolSDNode>(Op)
445 ->getSymbol(), MVT::i64),
446 DAG.getNode(ISD::GLOBAL_OFFSET_TABLE, MVT::i64));
451 //Expand only on constant case
452 if (Op.getOperand(1).getOpcode() == ISD::Constant) {
453 MVT::ValueType VT = Op.Val->getValueType(0);
454 SDOperand Tmp1 = Op.Val->getOpcode() == ISD::UREM ?
455 BuildUDIV(Op.Val, DAG, NULL) :
456 BuildSDIV(Op.Val, DAG, NULL);
457 Tmp1 = DAG.getNode(ISD::MUL, VT, Tmp1, Op.getOperand(1));
458 Tmp1 = DAG.getNode(ISD::SUB, VT, Op.getOperand(0), Tmp1);
464 if (MVT::isInteger(Op.getValueType())) {
465 if (Op.getOperand(1).getOpcode() == ISD::Constant)
466 return Op.getOpcode() == ISD::SDIV ? BuildSDIV(Op.Val, DAG, NULL)
467 : BuildUDIV(Op.Val, DAG, NULL);
468 const char* opstr = 0;
469 switch (Op.getOpcode()) {
470 case ISD::UREM: opstr = "__remqu"; break;
471 case ISD::SREM: opstr = "__remq"; break;
472 case ISD::UDIV: opstr = "__divqu"; break;
473 case ISD::SDIV: opstr = "__divq"; break;
475 SDOperand Tmp1 = Op.getOperand(0),
476 Tmp2 = Op.getOperand(1),
477 Addr = DAG.getExternalSymbol(opstr, MVT::i64);
478 return DAG.getNode(AlphaISD::DivCall, MVT::i64, Addr, Tmp1, Tmp2);
483 SDOperand Chain = Op.getOperand(0);
484 SDOperand VAListP = Op.getOperand(1);
485 SrcValueSDNode *VAListS = cast<SrcValueSDNode>(Op.getOperand(2));
487 SDOperand Base = DAG.getLoad(MVT::i64, Chain, VAListP, VAListS->getValue(),
488 VAListS->getOffset());
489 SDOperand Tmp = DAG.getNode(ISD::ADD, MVT::i64, VAListP,
490 DAG.getConstant(8, MVT::i64));
491 SDOperand Offset = DAG.getExtLoad(ISD::SEXTLOAD, MVT::i64, Base.getValue(1),
492 Tmp, NULL, 0, MVT::i32);
493 SDOperand DataPtr = DAG.getNode(ISD::ADD, MVT::i64, Base, Offset);
494 if (MVT::isFloatingPoint(Op.getValueType()))
496 //if fp && Offset < 6*8, then subtract 6*8 from DataPtr
497 SDOperand FPDataPtr = DAG.getNode(ISD::SUB, MVT::i64, DataPtr,
498 DAG.getConstant(8*6, MVT::i64));
499 SDOperand CC = DAG.getSetCC(MVT::i64, Offset,
500 DAG.getConstant(8*6, MVT::i64), ISD::SETLT);
501 DataPtr = DAG.getNode(ISD::SELECT, MVT::i64, CC, FPDataPtr, DataPtr);
504 SDOperand NewOffset = DAG.getNode(ISD::ADD, MVT::i64, Offset,
505 DAG.getConstant(8, MVT::i64));
506 SDOperand Update = DAG.getTruncStore(Offset.getValue(1), NewOffset,
507 Tmp, NULL, 0, MVT::i32);
510 if (Op.getValueType() == MVT::i32)
511 Result = DAG.getExtLoad(ISD::SEXTLOAD, MVT::i64, Update, DataPtr,
514 Result = DAG.getLoad(Op.getValueType(), Update, DataPtr, NULL, 0);
518 SDOperand Chain = Op.getOperand(0);
519 SDOperand DestP = Op.getOperand(1);
520 SDOperand SrcP = Op.getOperand(2);
521 SrcValueSDNode *DestS = cast<SrcValueSDNode>(Op.getOperand(3));
522 SrcValueSDNode *SrcS = cast<SrcValueSDNode>(Op.getOperand(4));
524 SDOperand Val = DAG.getLoad(getPointerTy(), Chain, SrcP,
525 SrcS->getValue(), SrcS->getOffset());
526 SDOperand Result = DAG.getStore(Val.getValue(1), Val, DestP, DestS->getValue(),
528 SDOperand NP = DAG.getNode(ISD::ADD, MVT::i64, SrcP,
529 DAG.getConstant(8, MVT::i64));
530 Val = DAG.getExtLoad(ISD::SEXTLOAD, MVT::i64, Result, NP, NULL,0, MVT::i32);
531 SDOperand NPD = DAG.getNode(ISD::ADD, MVT::i64, DestP,
532 DAG.getConstant(8, MVT::i64));
533 return DAG.getTruncStore(Val.getValue(1), Val, NPD, NULL, 0, MVT::i32);
536 SDOperand Chain = Op.getOperand(0);
537 SDOperand VAListP = Op.getOperand(1);
538 SrcValueSDNode *VAListS = cast<SrcValueSDNode>(Op.getOperand(2));
540 // vastart stores the address of the VarArgsBase and VarArgsOffset
541 SDOperand FR = DAG.getFrameIndex(VarArgsBase, MVT::i64);
542 SDOperand S1 = DAG.getStore(Chain, FR, VAListP, VAListS->getValue(),
543 VAListS->getOffset());
544 SDOperand SA2 = DAG.getNode(ISD::ADD, MVT::i64, VAListP,
545 DAG.getConstant(8, MVT::i64));
546 return DAG.getTruncStore(S1, DAG.getConstant(VarArgsOffset, MVT::i64),
547 SA2, NULL, 0, MVT::i32);
549 case ISD::RETURNADDR:
550 return DAG.getNode(AlphaISD::GlobalRetAddr, MVT::i64);
552 case ISD::FRAMEADDR: break;
558 SDOperand AlphaTargetLowering::CustomPromoteOperation(SDOperand Op,
560 assert(Op.getValueType() == MVT::i32 &&
561 Op.getOpcode() == ISD::VAARG &&
562 "Unknown node to custom promote!");
564 // The code in LowerOperation already handles i32 vaarg
565 return LowerOperation(Op, DAG);
571 /// getConstraintType - Given a constraint letter, return the type of
572 /// constraint it is for this target.
573 AlphaTargetLowering::ConstraintType
574 AlphaTargetLowering::getConstraintType(const std::string &Constraint) const {
575 if (Constraint.size() == 1) {
576 switch (Constraint[0]) {
580 return C_RegisterClass;
583 return TargetLowering::getConstraintType(Constraint);
586 std::vector<unsigned> AlphaTargetLowering::
587 getRegClassForInlineAsmConstraint(const std::string &Constraint,
588 MVT::ValueType VT) const {
589 if (Constraint.size() == 1) {
590 switch (Constraint[0]) {
591 default: break; // Unknown constriant letter
593 return make_vector<unsigned>(Alpha::F0 , Alpha::F1 , Alpha::F2 ,
594 Alpha::F3 , Alpha::F4 , Alpha::F5 ,
595 Alpha::F6 , Alpha::F7 , Alpha::F8 ,
596 Alpha::F9 , Alpha::F10, Alpha::F11,
597 Alpha::F12, Alpha::F13, Alpha::F14,
598 Alpha::F15, Alpha::F16, Alpha::F17,
599 Alpha::F18, Alpha::F19, Alpha::F20,
600 Alpha::F21, Alpha::F22, Alpha::F23,
601 Alpha::F24, Alpha::F25, Alpha::F26,
602 Alpha::F27, Alpha::F28, Alpha::F29,
603 Alpha::F30, Alpha::F31, 0);
605 return make_vector<unsigned>(Alpha::R0 , Alpha::R1 , Alpha::R2 ,
606 Alpha::R3 , Alpha::R4 , Alpha::R5 ,
607 Alpha::R6 , Alpha::R7 , Alpha::R8 ,
608 Alpha::R9 , Alpha::R10, Alpha::R11,
609 Alpha::R12, Alpha::R13, Alpha::R14,
610 Alpha::R15, Alpha::R16, Alpha::R17,
611 Alpha::R18, Alpha::R19, Alpha::R20,
612 Alpha::R21, Alpha::R22, Alpha::R23,
613 Alpha::R24, Alpha::R25, Alpha::R26,
614 Alpha::R27, Alpha::R28, Alpha::R29,
615 Alpha::R30, Alpha::R31, 0);
619 return std::vector<unsigned>();