1 //===-- AlphaISelLowering.cpp - Alpha DAG Lowering Implementation ---------===//
3 // The LLVM Compiler Infrastructure
5 // This file was developed by Andrew Lenharth and is distributed under
6 // the University of Illinois Open Source License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file implements the AlphaISelLowering class.
12 //===----------------------------------------------------------------------===//
14 #include "AlphaISelLowering.h"
15 #include "AlphaTargetMachine.h"
16 #include "llvm/CodeGen/MachineFrameInfo.h"
17 #include "llvm/CodeGen/MachineFunction.h"
18 #include "llvm/CodeGen/MachineInstrBuilder.h"
19 #include "llvm/CodeGen/SelectionDAG.h"
20 #include "llvm/CodeGen/SSARegMap.h"
21 #include "llvm/Constants.h"
22 #include "llvm/Function.h"
23 #include "llvm/Module.h"
24 #include "llvm/Support/CommandLine.h"
29 /// AddLiveIn - This helper function adds the specified physical register to the
30 /// MachineFunction as a live in value. It also creates a corresponding virtual
32 static unsigned AddLiveIn(MachineFunction &MF, unsigned PReg,
33 TargetRegisterClass *RC) {
34 assert(RC->contains(PReg) && "Not the correct regclass!");
35 unsigned VReg = MF.getSSARegMap()->createVirtualRegister(RC);
36 MF.addLiveIn(PReg, VReg);
40 AlphaTargetLowering::AlphaTargetLowering(TargetMachine &TM) : TargetLowering(TM) {
41 // Set up the TargetLowering object.
42 //I am having problems with shr n ubyte 1
43 setShiftAmountType(MVT::i64);
44 setSetCCResultType(MVT::i64);
45 setSetCCResultContents(ZeroOrOneSetCCResult);
47 addRegisterClass(MVT::i64, Alpha::GPRCRegisterClass);
48 addRegisterClass(MVT::f64, Alpha::F8RCRegisterClass);
49 addRegisterClass(MVT::f32, Alpha::F4RCRegisterClass);
51 setOperationAction(ISD::BRIND, MVT::i64, Expand);
52 setOperationAction(ISD::BR_CC, MVT::Other, Expand);
53 setOperationAction(ISD::SELECT_CC, MVT::Other, Expand);
55 setOperationAction(ISD::EXTLOAD, MVT::i1, Promote);
56 setOperationAction(ISD::EXTLOAD, MVT::f32, Expand);
58 setOperationAction(ISD::ZEXTLOAD, MVT::i1, Promote);
59 setOperationAction(ISD::ZEXTLOAD, MVT::i32, Expand);
61 setOperationAction(ISD::SEXTLOAD, MVT::i1, Promote);
62 setOperationAction(ISD::SEXTLOAD, MVT::i8, Expand);
63 setOperationAction(ISD::SEXTLOAD, MVT::i16, Expand);
65 setOperationAction(ISD::TRUNCSTORE, MVT::i1, Promote);
67 setOperationAction(ISD::FREM, MVT::f32, Expand);
68 setOperationAction(ISD::FREM, MVT::f64, Expand);
70 setOperationAction(ISD::UINT_TO_FP, MVT::i64, Expand);
71 setOperationAction(ISD::SINT_TO_FP, MVT::i64, Custom);
72 setOperationAction(ISD::FP_TO_UINT, MVT::i64, Expand);
73 setOperationAction(ISD::FP_TO_SINT, MVT::i64, Custom);
75 if (!TM.getSubtarget<AlphaSubtarget>().hasCT()) {
76 setOperationAction(ISD::CTPOP , MVT::i64 , Expand);
77 setOperationAction(ISD::CTTZ , MVT::i64 , Expand);
78 setOperationAction(ISD::CTLZ , MVT::i64 , Expand);
80 setOperationAction(ISD::BSWAP , MVT::i64, Expand);
81 setOperationAction(ISD::ROTL , MVT::i64, Expand);
82 setOperationAction(ISD::ROTR , MVT::i64, Expand);
84 setOperationAction(ISD::SREM , MVT::i64, Custom);
85 setOperationAction(ISD::UREM , MVT::i64, Custom);
86 setOperationAction(ISD::SDIV , MVT::i64, Custom);
87 setOperationAction(ISD::UDIV , MVT::i64, Custom);
89 setOperationAction(ISD::MEMMOVE , MVT::Other, Expand);
90 setOperationAction(ISD::MEMSET , MVT::Other, Expand);
91 setOperationAction(ISD::MEMCPY , MVT::Other, Expand);
93 // We don't support sin/cos/sqrt
94 setOperationAction(ISD::FSIN , MVT::f64, Expand);
95 setOperationAction(ISD::FCOS , MVT::f64, Expand);
96 setOperationAction(ISD::FSIN , MVT::f32, Expand);
97 setOperationAction(ISD::FCOS , MVT::f32, Expand);
99 setOperationAction(ISD::FSQRT, MVT::f64, Expand);
100 setOperationAction(ISD::FSQRT, MVT::f32, Expand);
102 // FIXME: Alpha supports fcopysign natively!?
103 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Expand);
104 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Expand);
106 setOperationAction(ISD::SETCC, MVT::f32, Promote);
108 // We don't have line number support yet.
109 setOperationAction(ISD::LOCATION, MVT::Other, Expand);
110 setOperationAction(ISD::DEBUG_LOC, MVT::Other, Expand);
111 setOperationAction(ISD::DEBUG_LABEL, MVT::Other, Expand);
113 // Not implemented yet.
114 setOperationAction(ISD::STACKSAVE, MVT::Other, Expand);
115 setOperationAction(ISD::STACKRESTORE, MVT::Other, Expand);
116 setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i64, Expand);
118 // We want to legalize GlobalAddress and ConstantPool and
119 // ExternalSymbols nodes into the appropriate instructions to
120 // materialize the address.
121 setOperationAction(ISD::GlobalAddress, MVT::i64, Custom);
122 setOperationAction(ISD::ConstantPool, MVT::i64, Custom);
123 setOperationAction(ISD::ExternalSymbol, MVT::i64, Custom);
125 setOperationAction(ISD::VASTART, MVT::Other, Custom);
126 setOperationAction(ISD::VAEND, MVT::Other, Expand);
127 setOperationAction(ISD::VACOPY, MVT::Other, Custom);
128 setOperationAction(ISD::VAARG, MVT::Other, Custom);
129 setOperationAction(ISD::VAARG, MVT::i32, Custom);
131 setOperationAction(ISD::RET, MVT::Other, Custom);
133 setStackPointerRegisterToSaveRestore(Alpha::R30);
135 setOperationAction(ISD::ConstantFP, MVT::f64, Expand);
136 setOperationAction(ISD::ConstantFP, MVT::f32, Expand);
137 addLegalFPImmediate(+0.0); //F31
138 addLegalFPImmediate(-0.0); //-F31
140 computeRegisterProperties();
142 useITOF = TM.getSubtarget<AlphaSubtarget>().hasF2I();
145 const char *AlphaTargetLowering::getTargetNodeName(unsigned Opcode) const {
148 case AlphaISD::ITOFT_: return "Alpha::ITOFT_";
149 case AlphaISD::FTOIT_: return "Alpha::FTOIT_";
150 case AlphaISD::CVTQT_: return "Alpha::CVTQT_";
151 case AlphaISD::CVTQS_: return "Alpha::CVTQS_";
152 case AlphaISD::CVTTQ_: return "Alpha::CVTTQ_";
153 case AlphaISD::GPRelHi: return "Alpha::GPRelHi";
154 case AlphaISD::GPRelLo: return "Alpha::GPRelLo";
155 case AlphaISD::RelLit: return "Alpha::RelLit";
156 case AlphaISD::GlobalBaseReg: return "Alpha::GlobalBaseReg";
157 case AlphaISD::GlobalRetAddr: return "Alpha::GlobalRetAddr";
158 case AlphaISD::CALL: return "Alpha::CALL";
159 case AlphaISD::DivCall: return "Alpha::DivCall";
160 case AlphaISD::RET_FLAG: return "Alpha::RET_FLAG";
164 //http://www.cs.arizona.edu/computer.help/policy/DIGITAL_unix/AA-PY8AC-TET1_html/callCH3.html#BLOCK21
166 //For now, just use variable size stack frame format
168 //In a standard call, the first six items are passed in registers $16
169 //- $21 and/or registers $f16 - $f21. (See Section 4.1.2 for details
170 //of argument-to-register correspondence.) The remaining items are
171 //collected in a memory argument list that is a naturally aligned
172 //array of quadwords. In a standard call, this list, if present, must
173 //be passed at 0(SP).
174 //7 ... n 0(SP) ... (n-7)*8(SP)
182 static SDOperand LowerFORMAL_ARGUMENTS(SDOperand Op, SelectionDAG &DAG,
187 MachineFunction &MF = DAG.getMachineFunction();
188 MachineFrameInfo *MFI = MF.getFrameInfo();
189 SSARegMap *RegMap = MF.getSSARegMap();
190 std::vector<SDOperand> ArgValues;
191 SDOperand Root = Op.getOperand(0);
193 GP = AddLiveIn(MF, Alpha::R29, &Alpha::GPRCRegClass);
194 RA = AddLiveIn(MF, Alpha::R26, &Alpha::GPRCRegClass);
196 unsigned args_int[] = {
197 Alpha::R16, Alpha::R17, Alpha::R18, Alpha::R19, Alpha::R20, Alpha::R21};
198 unsigned args_float[] = {
199 Alpha::F16, Alpha::F17, Alpha::F18, Alpha::F19, Alpha::F20, Alpha::F21};
201 for (unsigned ArgNo = 0, e = Op.Val->getNumValues()-1; ArgNo != e; ++ArgNo) {
203 MVT::ValueType ObjectVT = Op.getValue(ArgNo).getValueType();
210 std::cerr << "Unknown Type " << ObjectVT << "\n";
213 args_float[ArgNo] = AddLiveIn(MF, args_float[ArgNo],
214 &Alpha::F8RCRegClass);
215 ArgVal = DAG.getCopyFromReg(Root, args_float[ArgNo], ObjectVT);
218 args_float[ArgNo] = AddLiveIn(MF, args_float[ArgNo],
219 &Alpha::F4RCRegClass);
220 ArgVal = DAG.getCopyFromReg(Root, args_float[ArgNo], ObjectVT);
223 args_int[ArgNo] = AddLiveIn(MF, args_int[ArgNo],
224 &Alpha::GPRCRegClass);
225 ArgVal = DAG.getCopyFromReg(Root, args_int[ArgNo], MVT::i64);
229 // Create the frame index object for this incoming parameter...
230 int FI = MFI->CreateFixedObject(8, 8 * (ArgNo - 6));
232 // Create the SelectionDAG nodes corresponding to a load
233 //from this parameter
234 SDOperand FIN = DAG.getFrameIndex(FI, MVT::i64);
235 ArgVal = DAG.getLoad(ObjectVT, Root, FIN, DAG.getSrcValue(NULL));
237 ArgValues.push_back(ArgVal);
240 // If the functions takes variable number of arguments, copy all regs to stack
241 bool isVarArg = cast<ConstantSDNode>(Op.getOperand(2))->getValue() != 0;
243 VarArgsOffset = (Op.Val->getNumValues()-1) * 8;
244 std::vector<SDOperand> LS;
245 for (int i = 0; i < 6; ++i) {
246 if (MRegisterInfo::isPhysicalRegister(args_int[i]))
247 args_int[i] = AddLiveIn(MF, args_int[i], &Alpha::GPRCRegClass);
248 SDOperand argt = DAG.getCopyFromReg(Root, args_int[i], MVT::i64);
249 int FI = MFI->CreateFixedObject(8, -8 * (6 - i));
250 if (i == 0) VarArgsBase = FI;
251 SDOperand SDFI = DAG.getFrameIndex(FI, MVT::i64);
252 LS.push_back(DAG.getNode(ISD::STORE, MVT::Other, Root, argt,
253 SDFI, DAG.getSrcValue(NULL)));
255 if (MRegisterInfo::isPhysicalRegister(args_float[i]))
256 args_float[i] = AddLiveIn(MF, args_float[i], &Alpha::F8RCRegClass);
257 argt = DAG.getCopyFromReg(Root, args_float[i], MVT::f64);
258 FI = MFI->CreateFixedObject(8, - 8 * (12 - i));
259 SDFI = DAG.getFrameIndex(FI, MVT::i64);
260 LS.push_back(DAG.getNode(ISD::STORE, MVT::Other, Root, argt,
261 SDFI, DAG.getSrcValue(NULL)));
264 //Set up a token factor with all the stack traffic
265 Root = DAG.getNode(ISD::TokenFactor, MVT::Other, LS);
268 ArgValues.push_back(Root);
270 // Return the new list of results.
271 std::vector<MVT::ValueType> RetVT(Op.Val->value_begin(),
272 Op.Val->value_end());
273 return DAG.getNode(ISD::MERGE_VALUES, RetVT, ArgValues);
276 static SDOperand LowerRET(SDOperand Op, SelectionDAG &DAG, unsigned int RA) {
277 SDOperand Copy = DAG.getCopyToReg(Op.getOperand(0), Alpha::R26,
278 DAG.getNode(AlphaISD::GlobalRetAddr, MVT::i64),
280 switch (Op.getNumOperands()) {
282 assert(0 && "Do not know how to return this many arguments!");
286 //return SDOperand(); // ret void is legal
288 MVT::ValueType ArgVT = Op.getOperand(1).getValueType();
290 if (MVT::isInteger(ArgVT))
293 assert(MVT::isFloatingPoint(ArgVT));
296 Copy = DAG.getCopyToReg(Copy, ArgReg, Op.getOperand(1), Copy.getValue(1));
297 if(DAG.getMachineFunction().liveout_empty())
298 DAG.getMachineFunction().addLiveOut(ArgReg);
302 return DAG.getNode(AlphaISD::RET_FLAG, MVT::Other, Copy, Copy.getValue(1));
305 std::pair<SDOperand, SDOperand>
306 AlphaTargetLowering::LowerCallTo(SDOperand Chain,
307 const Type *RetTy, bool isVarArg,
308 unsigned CallingConv, bool isTailCall,
309 SDOperand Callee, ArgListTy &Args,
313 NumBytes = (Args.size() - 6) * 8;
315 Chain = DAG.getCALLSEQ_START(Chain,
316 DAG.getConstant(NumBytes, getPointerTy()));
317 std::vector<SDOperand> args_to_use;
318 for (unsigned i = 0, e = Args.size(); i != e; ++i)
320 switch (getValueType(Args[i].second)) {
321 default: assert(0 && "Unexpected ValueType for argument!");
326 // Promote the integer to 64 bits. If the input type is signed use a
327 // sign extend, otherwise use a zero extend.
328 if (Args[i].second->isSigned())
329 Args[i].first = DAG.getNode(ISD::SIGN_EXTEND, MVT::i64, Args[i].first);
331 Args[i].first = DAG.getNode(ISD::ZERO_EXTEND, MVT::i64, Args[i].first);
338 args_to_use.push_back(Args[i].first);
341 std::vector<MVT::ValueType> RetVals;
342 MVT::ValueType RetTyVT = getValueType(RetTy);
343 MVT::ValueType ActualRetTyVT = RetTyVT;
344 if (RetTyVT >= MVT::i1 && RetTyVT <= MVT::i32)
345 ActualRetTyVT = MVT::i64;
347 if (RetTyVT != MVT::isVoid)
348 RetVals.push_back(ActualRetTyVT);
349 RetVals.push_back(MVT::Other);
351 std::vector<SDOperand> Ops;
352 Ops.push_back(Chain);
353 Ops.push_back(Callee);
354 Ops.insert(Ops.end(), args_to_use.begin(), args_to_use.end());
355 SDOperand TheCall = DAG.getNode(AlphaISD::CALL, RetVals, Ops);
356 Chain = TheCall.getValue(RetTyVT != MVT::isVoid);
357 Chain = DAG.getNode(ISD::CALLSEQ_END, MVT::Other, Chain,
358 DAG.getConstant(NumBytes, getPointerTy()));
359 SDOperand RetVal = TheCall;
361 if (RetTyVT != ActualRetTyVT) {
362 RetVal = DAG.getNode(RetTy->isSigned() ? ISD::AssertSext : ISD::AssertZext,
363 MVT::i64, RetVal, DAG.getValueType(RetTyVT));
364 RetVal = DAG.getNode(ISD::TRUNCATE, RetTyVT, RetVal);
367 return std::make_pair(RetVal, Chain);
370 void AlphaTargetLowering::restoreGP(MachineBasicBlock* BB)
372 BuildMI(BB, Alpha::BIS, 2, Alpha::R29).addReg(GP).addReg(GP);
374 void AlphaTargetLowering::restoreRA(MachineBasicBlock* BB)
376 BuildMI(BB, Alpha::BIS, 2, Alpha::R26).addReg(RA).addReg(RA);
385 /// LowerOperation - Provide custom lowering hooks for some operations.
387 SDOperand AlphaTargetLowering::LowerOperation(SDOperand Op, SelectionDAG &DAG) {
388 switch (Op.getOpcode()) {
389 default: assert(0 && "Wasn't expecting to be able to lower this!");
390 case ISD::FORMAL_ARGUMENTS: return LowerFORMAL_ARGUMENTS(Op, DAG,
394 case ISD::RET: return LowerRET(Op,DAG, getVRegRA());
395 case ISD::SINT_TO_FP: {
396 assert(MVT::i64 == Op.getOperand(0).getValueType() &&
397 "Unhandled SINT_TO_FP type in custom expander!");
399 bool isDouble = MVT::f64 == Op.getValueType();
401 LD = DAG.getNode(AlphaISD::ITOFT_, MVT::f64, Op.getOperand(0));
404 DAG.getMachineFunction().getFrameInfo()->CreateStackObject(8, 8);
405 SDOperand FI = DAG.getFrameIndex(FrameIdx, MVT::i64);
406 SDOperand ST = DAG.getNode(ISD::STORE, MVT::Other, DAG.getEntryNode(),
407 Op.getOperand(0), FI, DAG.getSrcValue(0));
408 LD = DAG.getLoad(MVT::f64, ST, FI, DAG.getSrcValue(0));
410 SDOperand FP = DAG.getNode(isDouble?AlphaISD::CVTQT_:AlphaISD::CVTQS_,
411 isDouble?MVT::f64:MVT::f32, LD);
414 case ISD::FP_TO_SINT: {
415 bool isDouble = MVT::f64 == Op.getOperand(0).getValueType();
416 SDOperand src = Op.getOperand(0);
418 if (!isDouble) //Promote
419 src = DAG.getNode(ISD::FP_EXTEND, MVT::f64, src);
421 src = DAG.getNode(AlphaISD::CVTTQ_, MVT::f64, src);
424 return DAG.getNode(AlphaISD::FTOIT_, MVT::i64, src);
427 DAG.getMachineFunction().getFrameInfo()->CreateStackObject(8, 8);
428 SDOperand FI = DAG.getFrameIndex(FrameIdx, MVT::i64);
429 SDOperand ST = DAG.getNode(ISD::STORE, MVT::Other, DAG.getEntryNode(),
430 src, FI, DAG.getSrcValue(0));
431 return DAG.getLoad(MVT::i64, ST, FI, DAG.getSrcValue(0));
434 case ISD::ConstantPool: {
435 ConstantPoolSDNode *CP = cast<ConstantPoolSDNode>(Op);
436 Constant *C = CP->get();
437 SDOperand CPI = DAG.getTargetConstantPool(C, MVT::i64, CP->getAlignment());
439 SDOperand Hi = DAG.getNode(AlphaISD::GPRelHi, MVT::i64, CPI,
440 DAG.getNode(AlphaISD::GlobalBaseReg, MVT::i64));
441 SDOperand Lo = DAG.getNode(AlphaISD::GPRelLo, MVT::i64, CPI, Hi);
444 case ISD::GlobalAddress: {
445 GlobalAddressSDNode *GSDN = cast<GlobalAddressSDNode>(Op);
446 GlobalValue *GV = GSDN->getGlobal();
447 SDOperand GA = DAG.getTargetGlobalAddress(GV, MVT::i64, GSDN->getOffset());
449 // if (!GV->hasWeakLinkage() && !GV->isExternal() && !GV->hasLinkOnceLinkage()) {
450 if (GV->hasInternalLinkage()) {
451 SDOperand Hi = DAG.getNode(AlphaISD::GPRelHi, MVT::i64, GA,
452 DAG.getNode(AlphaISD::GlobalBaseReg, MVT::i64));
453 SDOperand Lo = DAG.getNode(AlphaISD::GPRelLo, MVT::i64, GA, Hi);
456 return DAG.getNode(AlphaISD::RelLit, MVT::i64, GA, DAG.getNode(AlphaISD::GlobalBaseReg, MVT::i64));
458 case ISD::ExternalSymbol: {
459 return DAG.getNode(AlphaISD::RelLit, MVT::i64,
460 DAG.getTargetExternalSymbol(cast<ExternalSymbolSDNode>(Op)->getSymbol(), MVT::i64),
461 DAG.getNode(AlphaISD::GlobalBaseReg, MVT::i64));
466 //Expand only on constant case
467 if (Op.getOperand(1).getOpcode() == ISD::Constant) {
468 MVT::ValueType VT = Op.Val->getValueType(0);
469 unsigned Opc = Op.Val->getOpcode() == ISD::UREM ? ISD::UDIV : ISD::SDIV;
470 SDOperand Tmp1 = Op.Val->getOpcode() == ISD::UREM ?
471 BuildUDIV(Op.Val, DAG, NULL) :
472 BuildSDIV(Op.Val, DAG, NULL);
473 Tmp1 = DAG.getNode(ISD::MUL, VT, Tmp1, Op.getOperand(1));
474 Tmp1 = DAG.getNode(ISD::SUB, VT, Op.getOperand(0), Tmp1);
480 if (MVT::isInteger(Op.getValueType())) {
481 if (Op.getOperand(1).getOpcode() == ISD::Constant)
482 return Op.getOpcode() == ISD::SDIV ? BuildSDIV(Op.Val, DAG, NULL)
483 : BuildUDIV(Op.Val, DAG, NULL);
484 const char* opstr = 0;
485 switch(Op.getOpcode()) {
486 case ISD::UREM: opstr = "__remqu"; break;
487 case ISD::SREM: opstr = "__remq"; break;
488 case ISD::UDIV: opstr = "__divqu"; break;
489 case ISD::SDIV: opstr = "__divq"; break;
491 SDOperand Tmp1 = Op.getOperand(0),
492 Tmp2 = Op.getOperand(1),
493 Addr = DAG.getExternalSymbol(opstr, MVT::i64);
494 return DAG.getNode(AlphaISD::DivCall, MVT::i64, Addr, Tmp1, Tmp2);
499 SDOperand Chain = Op.getOperand(0);
500 SDOperand VAListP = Op.getOperand(1);
501 SDOperand VAListS = Op.getOperand(2);
503 SDOperand Base = DAG.getLoad(MVT::i64, Chain, VAListP, VAListS);
504 SDOperand Tmp = DAG.getNode(ISD::ADD, MVT::i64, VAListP,
505 DAG.getConstant(8, MVT::i64));
506 SDOperand Offset = DAG.getExtLoad(ISD::SEXTLOAD, MVT::i64, Base.getValue(1),
507 Tmp, DAG.getSrcValue(0), MVT::i32);
508 SDOperand DataPtr = DAG.getNode(ISD::ADD, MVT::i64, Base, Offset);
509 if (MVT::isFloatingPoint(Op.getValueType()))
511 //if fp && Offset < 6*8, then subtract 6*8 from DataPtr
512 SDOperand FPDataPtr = DAG.getNode(ISD::SUB, MVT::i64, DataPtr,
513 DAG.getConstant(8*6, MVT::i64));
514 SDOperand CC = DAG.getSetCC(MVT::i64, Offset,
515 DAG.getConstant(8*6, MVT::i64), ISD::SETLT);
516 DataPtr = DAG.getNode(ISD::SELECT, MVT::i64, CC, FPDataPtr, DataPtr);
519 SDOperand NewOffset = DAG.getNode(ISD::ADD, MVT::i64, Offset,
520 DAG.getConstant(8, MVT::i64));
521 SDOperand Update = DAG.getNode(ISD::TRUNCSTORE, MVT::Other,
522 Offset.getValue(1), NewOffset,
523 Tmp, DAG.getSrcValue(0),
524 DAG.getValueType(MVT::i32));
527 if (Op.getValueType() == MVT::i32)
528 Result = DAG.getExtLoad(ISD::SEXTLOAD, MVT::i64, Update, DataPtr,
529 DAG.getSrcValue(0), MVT::i32);
531 Result = DAG.getLoad(Op.getValueType(), Update, DataPtr,
536 SDOperand Chain = Op.getOperand(0);
537 SDOperand DestP = Op.getOperand(1);
538 SDOperand SrcP = Op.getOperand(2);
539 SDOperand DestS = Op.getOperand(3);
540 SDOperand SrcS = Op.getOperand(4);
542 SDOperand Val = DAG.getLoad(getPointerTy(), Chain, SrcP, SrcS);
543 SDOperand Result = DAG.getNode(ISD::STORE, MVT::Other, Val.getValue(1), Val,
545 SDOperand NP = DAG.getNode(ISD::ADD, MVT::i64, SrcP,
546 DAG.getConstant(8, MVT::i64));
547 Val = DAG.getExtLoad(ISD::SEXTLOAD, MVT::i64, Result, NP,
548 DAG.getSrcValue(0), MVT::i32);
549 SDOperand NPD = DAG.getNode(ISD::ADD, MVT::i64, DestP,
550 DAG.getConstant(8, MVT::i64));
551 return DAG.getNode(ISD::TRUNCSTORE, MVT::Other, Val.getValue(1),
552 Val, NPD, DAG.getSrcValue(0),DAG.getValueType(MVT::i32));
555 SDOperand Chain = Op.getOperand(0);
556 SDOperand VAListP = Op.getOperand(1);
557 SDOperand VAListS = Op.getOperand(2);
559 // vastart stores the address of the VarArgsBase and VarArgsOffset
560 SDOperand FR = DAG.getFrameIndex(VarArgsBase, MVT::i64);
561 SDOperand S1 = DAG.getNode(ISD::STORE, MVT::Other, Chain, FR, VAListP,
563 SDOperand SA2 = DAG.getNode(ISD::ADD, MVT::i64, VAListP,
564 DAG.getConstant(8, MVT::i64));
565 return DAG.getNode(ISD::TRUNCSTORE, MVT::Other, S1,
566 DAG.getConstant(VarArgsOffset, MVT::i64), SA2,
567 DAG.getSrcValue(0), DAG.getValueType(MVT::i32));
574 SDOperand AlphaTargetLowering::CustomPromoteOperation(SDOperand Op,
576 assert(Op.getValueType() == MVT::i32 &&
577 Op.getOpcode() == ISD::VAARG &&
578 "Unknown node to custom promote!");
580 // The code in LowerOperation already handles i32 vaarg
581 return LowerOperation(Op, DAG);