1 //===-- AlphaISelLowering.cpp - Alpha DAG Lowering Implementation ---------===//
3 // The LLVM Compiler Infrastructure
5 // This file was developed by Andrew Lenharth and is distributed under
6 // the University of Illinois Open Source License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file implements the AlphaISelLowering class.
12 //===----------------------------------------------------------------------===//
14 #include "AlphaISelLowering.h"
15 #include "AlphaTargetMachine.h"
16 #include "llvm/CodeGen/MachineFrameInfo.h"
17 #include "llvm/CodeGen/MachineFunction.h"
18 #include "llvm/CodeGen/MachineInstrBuilder.h"
19 #include "llvm/CodeGen/SelectionDAG.h"
20 #include "llvm/CodeGen/SSARegMap.h"
21 #include "llvm/Constants.h"
22 #include "llvm/Function.h"
23 #include "llvm/Support/CommandLine.h"
29 extern cl::opt<bool> EnableAlphaIDIV;
30 extern cl::opt<bool> EnableAlphaCount;
31 extern cl::opt<bool> EnableAlphaLSMark;
34 /// AddLiveIn - This helper function adds the specified physical register to the
35 /// MachineFunction as a live in value. It also creates a corresponding virtual
37 static unsigned AddLiveIn(MachineFunction &MF, unsigned PReg,
38 TargetRegisterClass *RC) {
39 assert(RC->contains(PReg) && "Not the correct regclass!");
40 unsigned VReg = MF.getSSARegMap()->createVirtualRegister(RC);
41 MF.addLiveIn(PReg, VReg);
45 AlphaTargetLowering::AlphaTargetLowering(TargetMachine &TM) : TargetLowering(TM) {
46 // Set up the TargetLowering object.
47 //I am having problems with shr n ubyte 1
48 setShiftAmountType(MVT::i64);
49 setSetCCResultType(MVT::i64);
50 setSetCCResultContents(ZeroOrOneSetCCResult);
52 addRegisterClass(MVT::i64, Alpha::GPRCRegisterClass);
53 addRegisterClass(MVT::f64, Alpha::F8RCRegisterClass);
54 addRegisterClass(MVT::f32, Alpha::F4RCRegisterClass);
56 setOperationAction(ISD::BRCONDTWOWAY, MVT::Other, Expand);
57 setOperationAction(ISD::BRTWOWAY_CC, MVT::Other, Expand);
59 setOperationAction(ISD::EXTLOAD, MVT::i1, Promote);
60 setOperationAction(ISD::EXTLOAD, MVT::f32, Expand);
62 setOperationAction(ISD::ZEXTLOAD, MVT::i1, Promote);
63 setOperationAction(ISD::ZEXTLOAD, MVT::i32, Expand);
65 setOperationAction(ISD::SEXTLOAD, MVT::i1, Promote);
66 setOperationAction(ISD::SEXTLOAD, MVT::i8, Expand);
67 setOperationAction(ISD::SEXTLOAD, MVT::i16, Expand);
69 setOperationAction(ISD::TRUNCSTORE, MVT::i1, Promote);
71 setOperationAction(ISD::FREM, MVT::f32, Expand);
72 setOperationAction(ISD::FREM, MVT::f64, Expand);
74 setOperationAction(ISD::UINT_TO_FP, MVT::i64, Expand);
75 setOperationAction(ISD::SINT_TO_FP, MVT::i64, Custom);
76 setOperationAction(ISD::FP_TO_UINT, MVT::i64, Expand);
77 setOperationAction(ISD::FP_TO_SINT, MVT::i64, Custom);
79 if (!TM.getSubtarget<AlphaSubtarget>().hasCT()) {
80 setOperationAction(ISD::CTPOP , MVT::i64 , Expand);
81 setOperationAction(ISD::CTTZ , MVT::i64 , Expand);
82 setOperationAction(ISD::CTLZ , MVT::i64 , Expand);
85 setOperationAction(ISD::SREM , MVT::i64, Custom);
86 setOperationAction(ISD::UREM , MVT::i64, Custom);
87 setOperationAction(ISD::SDIV , MVT::i64, Custom);
88 setOperationAction(ISD::UDIV , MVT::i64, Custom);
90 setOperationAction(ISD::MEMMOVE , MVT::Other, Expand);
91 setOperationAction(ISD::MEMSET , MVT::Other, Expand);
92 setOperationAction(ISD::MEMCPY , MVT::Other, Expand);
94 // We don't support sin/cos/sqrt
95 setOperationAction(ISD::FSIN , MVT::f64, Expand);
96 setOperationAction(ISD::FCOS , MVT::f64, Expand);
97 setOperationAction(ISD::FSQRT, MVT::f64, Expand);
98 setOperationAction(ISD::FSIN , MVT::f32, Expand);
99 setOperationAction(ISD::FCOS , MVT::f32, Expand);
100 setOperationAction(ISD::FSQRT, MVT::f32, Expand);
102 setOperationAction(ISD::SETCC, MVT::f32, Promote);
104 // We don't have line number support yet.
105 setOperationAction(ISD::LOCATION, MVT::Other, Expand);
106 setOperationAction(ISD::DEBUG_LOC, MVT::Other, Expand);
107 setOperationAction(ISD::DEBUG_LABEL, MVT::Other, Expand);
109 // We want to legalize GlobalAddress and ConstantPool and
110 // ExternalSymbols nodes into the appropriate instructions to
111 // materialize the address.
112 setOperationAction(ISD::GlobalAddress, MVT::i64, Custom);
113 setOperationAction(ISD::ConstantPool, MVT::i64, Custom);
114 setOperationAction(ISD::ExternalSymbol, MVT::i64, Custom);
116 addLegalFPImmediate(+0.0); //F31
117 addLegalFPImmediate(-0.0); //-F31
119 computeRegisterProperties();
121 useITOF = TM.getSubtarget<AlphaSubtarget>().hasF2I();
125 //http://www.cs.arizona.edu/computer.help/policy/DIGITAL_unix/AA-PY8AC-TET1_html/callCH3.html#BLOCK21
127 //For now, just use variable size stack frame format
129 //In a standard call, the first six items are passed in registers $16
130 //- $21 and/or registers $f16 - $f21. (See Section 4.1.2 for details
131 //of argument-to-register correspondence.) The remaining items are
132 //collected in a memory argument list that is a naturally aligned
133 //array of quadwords. In a standard call, this list, if present, must
134 //be passed at 0(SP).
135 //7 ... n 0(SP) ... (n-7)*8(SP)
143 std::vector<SDOperand>
144 AlphaTargetLowering::LowerArguments(Function &F, SelectionDAG &DAG)
146 MachineFunction &MF = DAG.getMachineFunction();
147 MachineFrameInfo *MFI = MF.getFrameInfo();
148 MachineBasicBlock& BB = MF.front();
149 std::vector<SDOperand> ArgValues;
151 unsigned args_int[] = {
152 Alpha::R16, Alpha::R17, Alpha::R18, Alpha::R19, Alpha::R20, Alpha::R21};
153 unsigned args_float[] = {
154 Alpha::F16, Alpha::F17, Alpha::F18, Alpha::F19, Alpha::F20, Alpha::F21};
158 GP = AddLiveIn(MF, Alpha::R29, getRegClassFor(MVT::i64));
159 RA = AddLiveIn(MF, Alpha::R26, getRegClassFor(MVT::i64));
161 for (Function::arg_iterator I = F.arg_begin(), E = F.arg_end(); I != E; ++I)
166 MVT::ValueType VT = getValueType(I->getType());
169 std::cerr << "Unknown Type " << VT << "\n";
173 args_float[count] = AddLiveIn(MF, args_float[count], getRegClassFor(VT));
174 argt = DAG.getCopyFromReg(DAG.getRoot(), args_float[count], VT);
175 DAG.setRoot(argt.getValue(1));
182 args_int[count] = AddLiveIn(MF, args_int[count], getRegClassFor(MVT::i64));
183 argt = DAG.getCopyFromReg(DAG.getRoot(), args_int[count], MVT::i64);
184 DAG.setRoot(argt.getValue(1));
185 if (VT != MVT::i64) {
187 I->getType()->isSigned() ? ISD::AssertSext : ISD::AssertZext;
188 argt = DAG.getNode(AssertOp, MVT::i64, argt,
189 DAG.getValueType(VT));
190 argt = DAG.getNode(ISD::TRUNCATE, VT, argt);
195 // Create the frame index object for this incoming parameter...
196 int FI = MFI->CreateFixedObject(8, 8 * (count - 6));
198 // Create the SelectionDAG nodes corresponding to a load
199 //from this parameter
200 SDOperand FIN = DAG.getFrameIndex(FI, MVT::i64);
201 argt = DAG.getLoad(getValueType(I->getType()),
202 DAG.getEntryNode(), FIN, DAG.getSrcValue(NULL));
205 ArgValues.push_back(argt);
208 // If the functions takes variable number of arguments, copy all regs to stack
210 VarArgsOffset = count * 8;
211 std::vector<SDOperand> LS;
212 for (int i = 0; i < 6; ++i) {
213 if (MRegisterInfo::isPhysicalRegister(args_int[i]))
214 args_int[i] = AddLiveIn(MF, args_int[i], getRegClassFor(MVT::i64));
215 SDOperand argt = DAG.getCopyFromReg(DAG.getRoot(), args_int[i], MVT::i64);
216 int FI = MFI->CreateFixedObject(8, -8 * (6 - i));
217 if (i == 0) VarArgsBase = FI;
218 SDOperand SDFI = DAG.getFrameIndex(FI, MVT::i64);
219 LS.push_back(DAG.getNode(ISD::STORE, MVT::Other, DAG.getRoot(), argt,
220 SDFI, DAG.getSrcValue(NULL)));
222 if (MRegisterInfo::isPhysicalRegister(args_float[i]))
223 args_float[i] = AddLiveIn(MF, args_float[i], getRegClassFor(MVT::f64));
224 argt = DAG.getCopyFromReg(DAG.getRoot(), args_float[i], MVT::f64);
225 FI = MFI->CreateFixedObject(8, - 8 * (12 - i));
226 SDFI = DAG.getFrameIndex(FI, MVT::i64);
227 LS.push_back(DAG.getNode(ISD::STORE, MVT::Other, DAG.getRoot(), argt,
228 SDFI, DAG.getSrcValue(NULL)));
231 //Set up a token factor with all the stack traffic
232 DAG.setRoot(DAG.getNode(ISD::TokenFactor, MVT::Other, LS));
235 // Finally, inform the code generator which regs we return values in.
236 switch (getValueType(F.getReturnType())) {
237 default: assert(0 && "Unknown type!");
238 case MVT::isVoid: break;
244 MF.addLiveOut(Alpha::R0);
248 MF.addLiveOut(Alpha::F0);
252 //return the arguments
256 std::pair<SDOperand, SDOperand>
257 AlphaTargetLowering::LowerCallTo(SDOperand Chain,
258 const Type *RetTy, bool isVarArg,
259 unsigned CallingConv, bool isTailCall,
260 SDOperand Callee, ArgListTy &Args,
264 NumBytes = (Args.size() - 6) * 8;
266 Chain = DAG.getNode(ISD::CALLSEQ_START, MVT::Other, Chain,
267 DAG.getConstant(NumBytes, getPointerTy()));
268 std::vector<SDOperand> args_to_use;
269 for (unsigned i = 0, e = Args.size(); i != e; ++i)
271 switch (getValueType(Args[i].second)) {
272 default: assert(0 && "Unexpected ValueType for argument!");
277 // Promote the integer to 64 bits. If the input type is signed use a
278 // sign extend, otherwise use a zero extend.
279 if (Args[i].second->isSigned())
280 Args[i].first = DAG.getNode(ISD::SIGN_EXTEND, MVT::i64, Args[i].first);
282 Args[i].first = DAG.getNode(ISD::ZERO_EXTEND, MVT::i64, Args[i].first);
289 args_to_use.push_back(Args[i].first);
292 std::vector<MVT::ValueType> RetVals;
293 MVT::ValueType RetTyVT = getValueType(RetTy);
294 MVT::ValueType ActualRetTyVT = RetTyVT;
295 if (RetTyVT >= MVT::i1 && RetTyVT <= MVT::i32)
296 ActualRetTyVT = MVT::i64;
298 if (RetTyVT != MVT::isVoid)
299 RetVals.push_back(ActualRetTyVT);
300 RetVals.push_back(MVT::Other);
302 SDOperand TheCall = SDOperand(DAG.getCall(RetVals,
303 Chain, Callee, args_to_use), 0);
304 Chain = TheCall.getValue(RetTyVT != MVT::isVoid);
305 Chain = DAG.getNode(ISD::CALLSEQ_END, MVT::Other, Chain,
306 DAG.getConstant(NumBytes, getPointerTy()));
307 SDOperand RetVal = TheCall;
309 if (RetTyVT != ActualRetTyVT) {
310 RetVal = DAG.getNode(RetTy->isSigned() ? ISD::AssertSext : ISD::AssertZext,
311 MVT::i64, RetVal, DAG.getValueType(RetTyVT));
312 RetVal = DAG.getNode(ISD::TRUNCATE, RetTyVT, RetVal);
315 return std::make_pair(RetVal, Chain);
318 SDOperand AlphaTargetLowering::LowerVAStart(SDOperand Chain, SDOperand VAListP,
319 Value *VAListV, SelectionDAG &DAG) {
320 // vastart stores the address of the VarArgsBase and VarArgsOffset
321 SDOperand FR = DAG.getFrameIndex(VarArgsBase, MVT::i64);
322 SDOperand S1 = DAG.getNode(ISD::STORE, MVT::Other, Chain, FR, VAListP,
323 DAG.getSrcValue(VAListV));
324 SDOperand SA2 = DAG.getNode(ISD::ADD, MVT::i64, VAListP,
325 DAG.getConstant(8, MVT::i64));
326 return DAG.getNode(ISD::TRUNCSTORE, MVT::Other, S1,
327 DAG.getConstant(VarArgsOffset, MVT::i64), SA2,
328 DAG.getSrcValue(VAListV, 8), DAG.getValueType(MVT::i32));
331 std::pair<SDOperand,SDOperand> AlphaTargetLowering::
332 LowerVAArg(SDOperand Chain, SDOperand VAListP, Value *VAListV,
333 const Type *ArgTy, SelectionDAG &DAG) {
334 SDOperand Base = DAG.getLoad(MVT::i64, Chain, VAListP,
335 DAG.getSrcValue(VAListV));
336 SDOperand Tmp = DAG.getNode(ISD::ADD, MVT::i64, VAListP,
337 DAG.getConstant(8, MVT::i64));
338 SDOperand Offset = DAG.getExtLoad(ISD::SEXTLOAD, MVT::i64, Base.getValue(1),
339 Tmp, DAG.getSrcValue(VAListV, 8), MVT::i32);
340 SDOperand DataPtr = DAG.getNode(ISD::ADD, MVT::i64, Base, Offset);
341 if (ArgTy->isFloatingPoint())
343 //if fp && Offset < 6*8, then subtract 6*8 from DataPtr
344 SDOperand FPDataPtr = DAG.getNode(ISD::SUB, MVT::i64, DataPtr,
345 DAG.getConstant(8*6, MVT::i64));
346 SDOperand CC = DAG.getSetCC(MVT::i64, Offset,
347 DAG.getConstant(8*6, MVT::i64), ISD::SETLT);
348 DataPtr = DAG.getNode(ISD::SELECT, MVT::i64, CC, FPDataPtr, DataPtr);
352 if (ArgTy == Type::IntTy)
353 Result = DAG.getExtLoad(ISD::SEXTLOAD, MVT::i64, Offset.getValue(1),
354 DataPtr, DAG.getSrcValue(NULL), MVT::i32);
355 else if (ArgTy == Type::UIntTy)
356 Result = DAG.getExtLoad(ISD::ZEXTLOAD, MVT::i64, Offset.getValue(1),
357 DataPtr, DAG.getSrcValue(NULL), MVT::i32);
359 Result = DAG.getLoad(getValueType(ArgTy), Offset.getValue(1), DataPtr,
360 DAG.getSrcValue(NULL));
362 SDOperand NewOffset = DAG.getNode(ISD::ADD, MVT::i64, Offset,
363 DAG.getConstant(8, MVT::i64));
364 SDOperand Update = DAG.getNode(ISD::TRUNCSTORE, MVT::Other,
365 Result.getValue(1), NewOffset,
366 Tmp, DAG.getSrcValue(VAListV, 8),
367 DAG.getValueType(MVT::i32));
368 Result = DAG.getNode(ISD::TRUNCATE, getValueType(ArgTy), Result);
370 return std::make_pair(Result, Update);
374 SDOperand AlphaTargetLowering::
375 LowerVACopy(SDOperand Chain, SDOperand SrcP, Value *SrcV, SDOperand DestP,
376 Value *DestV, SelectionDAG &DAG) {
377 SDOperand Val = DAG.getLoad(getPointerTy(), Chain, SrcP,
378 DAG.getSrcValue(SrcV));
379 SDOperand Result = DAG.getNode(ISD::STORE, MVT::Other, Val.getValue(1),
380 Val, DestP, DAG.getSrcValue(DestV));
381 SDOperand NP = DAG.getNode(ISD::ADD, MVT::i64, SrcP,
382 DAG.getConstant(8, MVT::i64));
383 Val = DAG.getExtLoad(ISD::SEXTLOAD, MVT::i64, Result, NP,
384 DAG.getSrcValue(SrcV, 8), MVT::i32);
385 SDOperand NPD = DAG.getNode(ISD::ADD, MVT::i64, DestP,
386 DAG.getConstant(8, MVT::i64));
387 return DAG.getNode(ISD::TRUNCSTORE, MVT::Other, Val.getValue(1),
388 Val, NPD, DAG.getSrcValue(DestV, 8),
389 DAG.getValueType(MVT::i32));
392 void AlphaTargetLowering::restoreGP(MachineBasicBlock* BB)
394 BuildMI(BB, Alpha::BIS, 2, Alpha::R29).addReg(GP).addReg(GP);
396 void AlphaTargetLowering::restoreRA(MachineBasicBlock* BB)
398 BuildMI(BB, Alpha::BIS, 2, Alpha::R26).addReg(RA).addReg(RA);
402 /// LowerOperation - Provide custom lowering hooks for some operations.
404 SDOperand AlphaTargetLowering::LowerOperation(SDOperand Op, SelectionDAG &DAG) {
405 switch (Op.getOpcode()) {
406 default: assert(0 && "Wasn't expecting to be able to lower this!");
407 case ISD::SINT_TO_FP: {
408 assert(MVT::i64 == Op.getOperand(0).getValueType() &&
409 "Unhandled SINT_TO_FP type in custom expander!");
411 bool isDouble = MVT::f64 == Op.getValueType();
413 LD = DAG.getNode(AlphaISD::ITOFT_, MVT::f64, Op.getOperand(0));
416 DAG.getMachineFunction().getFrameInfo()->CreateStackObject(8, 8);
417 SDOperand FI = DAG.getFrameIndex(FrameIdx, MVT::i64);
418 SDOperand ST = DAG.getNode(ISD::STORE, MVT::Other, DAG.getEntryNode(),
419 Op.getOperand(0), FI, DAG.getSrcValue(0));
420 LD = DAG.getLoad(MVT::f64, ST, FI, DAG.getSrcValue(0));
422 SDOperand FP = DAG.getNode(isDouble?AlphaISD::CVTQT_:AlphaISD::CVTQS_,
423 isDouble?MVT::f64:MVT::f32, LD);
426 case ISD::FP_TO_SINT: {
427 bool isDouble = MVT::f64 == Op.getOperand(0).getValueType();
428 SDOperand src = Op.getOperand(0);
430 if (!isDouble) //Promote
431 src = DAG.getNode(ISD::FP_EXTEND, MVT::f64, src);
433 src = DAG.getNode(AlphaISD::CVTTQ_, MVT::f64, src);
436 return DAG.getNode(AlphaISD::FTOIT_, MVT::i64, src);
439 DAG.getMachineFunction().getFrameInfo()->CreateStackObject(8, 8);
440 SDOperand FI = DAG.getFrameIndex(FrameIdx, MVT::i64);
441 SDOperand ST = DAG.getNode(ISD::STORE, MVT::Other, DAG.getEntryNode(),
442 src, FI, DAG.getSrcValue(0));
443 return DAG.getLoad(MVT::i64, ST, FI, DAG.getSrcValue(0));
446 case ISD::ConstantPool: {
447 Constant *C = cast<ConstantPoolSDNode>(Op)->get();
448 SDOperand CPI = DAG.getTargetConstantPool(C, MVT::i64);
450 SDOperand Hi = DAG.getNode(AlphaISD::GPRelHi, MVT::i64, CPI,
451 DAG.getNode(AlphaISD::GlobalBaseReg, MVT::i64));
452 SDOperand Lo = DAG.getNode(AlphaISD::GPRelLo, MVT::i64, CPI, Hi);
455 case ISD::GlobalAddress: {
456 GlobalAddressSDNode *GSDN = cast<GlobalAddressSDNode>(Op);
457 GlobalValue *GV = GSDN->getGlobal();
458 SDOperand GA = DAG.getTargetGlobalAddress(GV, MVT::i64, GSDN->getOffset());
460 if (!GV->hasWeakLinkage() && !GV->isExternal()) {
461 SDOperand Hi = DAG.getNode(AlphaISD::GPRelHi, MVT::i64, GA,
462 DAG.getNode(AlphaISD::GlobalBaseReg, MVT::i64));
463 SDOperand Lo = DAG.getNode(AlphaISD::GPRelLo, MVT::i64, GA, Hi);
466 return DAG.getNode(AlphaISD::RelLit, MVT::i64, GA, DAG.getNode(AlphaISD::GlobalBaseReg, MVT::i64));
468 case ISD::ExternalSymbol: {
469 return DAG.getNode(AlphaISD::RelLit, MVT::i64,
470 DAG.getTargetExternalSymbol(cast<ExternalSymbolSDNode>(Op)->getSymbol(), MVT::i64),
471 DAG.getNode(AlphaISD::GlobalBaseReg, MVT::i64));
478 if (MVT::isInteger(Op.getValueType())) {
479 const char* opstr = 0;
480 switch(Op.getOpcode()) {
481 case ISD::UREM: opstr = "__remqu"; break;
482 case ISD::SREM: opstr = "__remq"; break;
483 case ISD::UDIV: opstr = "__divqu"; break;
484 case ISD::SDIV: opstr = "__divq"; break;
486 SDOperand Tmp1 = Op.getOperand(0),
487 Tmp2 = Op.getOperand(1),
488 Addr = DAG.getExternalSymbol(opstr, MVT::i64);
489 return DAG.getNode(AlphaISD::DivCall, MVT::i64, Addr, Tmp1, Tmp2);