1 //===-- AlphaISelLowering.cpp - Alpha DAG Lowering Implementation ---------===//
3 // The LLVM Compiler Infrastructure
5 // This file was developed by Andrew Lenharth and is distributed under
6 // the University of Illinois Open Source License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file implements the AlphaISelLowering class.
12 //===----------------------------------------------------------------------===//
14 #include "AlphaISelLowering.h"
15 #include "AlphaTargetMachine.h"
16 #include "llvm/CodeGen/MachineFrameInfo.h"
17 #include "llvm/CodeGen/MachineFunction.h"
18 #include "llvm/CodeGen/MachineInstrBuilder.h"
19 #include "llvm/CodeGen/SelectionDAG.h"
20 #include "llvm/CodeGen/SSARegMap.h"
21 #include "llvm/Constants.h"
22 #include "llvm/Function.h"
23 #include "llvm/Module.h"
24 #include "llvm/Support/CommandLine.h"
27 /// AddLiveIn - This helper function adds the specified physical register to the
28 /// MachineFunction as a live in value. It also creates a corresponding virtual
30 static unsigned AddLiveIn(MachineFunction &MF, unsigned PReg,
31 TargetRegisterClass *RC) {
32 assert(RC->contains(PReg) && "Not the correct regclass!");
33 unsigned VReg = MF.getSSARegMap()->createVirtualRegister(RC);
34 MF.addLiveIn(PReg, VReg);
38 AlphaTargetLowering::AlphaTargetLowering(TargetMachine &TM) : TargetLowering(TM) {
39 // Set up the TargetLowering object.
40 //I am having problems with shr n ubyte 1
41 setShiftAmountType(MVT::i64);
42 setSetCCResultType(MVT::i64);
43 setSetCCResultContents(ZeroOrOneSetCCResult);
45 setUsesGlobalOffsetTable(true);
47 addRegisterClass(MVT::i64, Alpha::GPRCRegisterClass);
48 addRegisterClass(MVT::f64, Alpha::F8RCRegisterClass);
49 addRegisterClass(MVT::f32, Alpha::F4RCRegisterClass);
51 setLoadXAction(ISD::EXTLOAD, MVT::i1, Promote);
52 setLoadXAction(ISD::EXTLOAD, MVT::f32, Expand);
54 setLoadXAction(ISD::ZEXTLOAD, MVT::i1, Promote);
55 setLoadXAction(ISD::ZEXTLOAD, MVT::i32, Expand);
57 setLoadXAction(ISD::SEXTLOAD, MVT::i1, Promote);
58 setLoadXAction(ISD::SEXTLOAD, MVT::i8, Expand);
59 setLoadXAction(ISD::SEXTLOAD, MVT::i16, Expand);
61 setStoreXAction(MVT::i1, Promote);
63 // setOperationAction(ISD::BRIND, MVT::Other, Expand);
64 setOperationAction(ISD::BR_JT, MVT::Other, Expand);
65 setOperationAction(ISD::BR_CC, MVT::Other, Expand);
66 setOperationAction(ISD::SELECT_CC, MVT::Other, Expand);
68 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1, Expand);
70 setOperationAction(ISD::FREM, MVT::f32, Expand);
71 setOperationAction(ISD::FREM, MVT::f64, Expand);
73 setOperationAction(ISD::UINT_TO_FP, MVT::i64, Expand);
74 setOperationAction(ISD::SINT_TO_FP, MVT::i64, Custom);
75 setOperationAction(ISD::FP_TO_UINT, MVT::i64, Expand);
76 setOperationAction(ISD::FP_TO_SINT, MVT::i64, Custom);
78 if (!TM.getSubtarget<AlphaSubtarget>().hasCT()) {
79 setOperationAction(ISD::CTPOP , MVT::i64 , Expand);
80 setOperationAction(ISD::CTTZ , MVT::i64 , Expand);
81 setOperationAction(ISD::CTLZ , MVT::i64 , Expand);
83 setOperationAction(ISD::BSWAP , MVT::i64, Expand);
84 setOperationAction(ISD::ROTL , MVT::i64, Expand);
85 setOperationAction(ISD::ROTR , MVT::i64, Expand);
87 setOperationAction(ISD::SREM , MVT::i64, Custom);
88 setOperationAction(ISD::UREM , MVT::i64, Custom);
89 setOperationAction(ISD::SDIV , MVT::i64, Custom);
90 setOperationAction(ISD::UDIV , MVT::i64, Custom);
92 setOperationAction(ISD::MEMMOVE , MVT::Other, Expand);
93 setOperationAction(ISD::MEMSET , MVT::Other, Expand);
94 setOperationAction(ISD::MEMCPY , MVT::Other, Expand);
96 // We don't support sin/cos/sqrt
97 setOperationAction(ISD::FSIN , MVT::f64, Expand);
98 setOperationAction(ISD::FCOS , MVT::f64, Expand);
99 setOperationAction(ISD::FSIN , MVT::f32, Expand);
100 setOperationAction(ISD::FCOS , MVT::f32, Expand);
102 setOperationAction(ISD::FSQRT, MVT::f64, Expand);
103 setOperationAction(ISD::FSQRT, MVT::f32, Expand);
105 setOperationAction(ISD::SETCC, MVT::f32, Promote);
107 // We don't have line number support yet.
108 setOperationAction(ISD::LOCATION, MVT::Other, Expand);
109 setOperationAction(ISD::DEBUG_LOC, MVT::Other, Expand);
110 setOperationAction(ISD::DEBUG_LABEL, MVT::Other, Expand);
112 // Not implemented yet.
113 setOperationAction(ISD::STACKSAVE, MVT::Other, Expand);
114 setOperationAction(ISD::STACKRESTORE, MVT::Other, Expand);
115 setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i64, Expand);
117 // We want to legalize GlobalAddress and ConstantPool and
118 // ExternalSymbols nodes into the appropriate instructions to
119 // materialize the address.
120 setOperationAction(ISD::GlobalAddress, MVT::i64, Custom);
121 setOperationAction(ISD::ConstantPool, MVT::i64, Custom);
122 setOperationAction(ISD::ExternalSymbol, MVT::i64, Custom);
124 setOperationAction(ISD::VASTART, MVT::Other, Custom);
125 setOperationAction(ISD::VAEND, MVT::Other, Expand);
126 setOperationAction(ISD::VACOPY, MVT::Other, Custom);
127 setOperationAction(ISD::VAARG, MVT::Other, Custom);
128 setOperationAction(ISD::VAARG, MVT::i32, Custom);
130 setOperationAction(ISD::RET, MVT::Other, Custom);
132 setOperationAction(ISD::JumpTable, MVT::i64, Custom);
133 setOperationAction(ISD::JumpTable, MVT::i32, Custom);
135 setStackPointerRegisterToSaveRestore(Alpha::R30);
137 setOperationAction(ISD::ConstantFP, MVT::f64, Expand);
138 setOperationAction(ISD::ConstantFP, MVT::f32, Expand);
139 addLegalFPImmediate(+0.0); //F31
140 addLegalFPImmediate(-0.0); //-F31
143 setJumpBufAlignment(16);
145 computeRegisterProperties();
147 useITOF = TM.getSubtarget<AlphaSubtarget>().hasF2I();
150 const char *AlphaTargetLowering::getTargetNodeName(unsigned Opcode) const {
153 case AlphaISD::ITOFT_: return "Alpha::ITOFT_";
154 case AlphaISD::FTOIT_: return "Alpha::FTOIT_";
155 case AlphaISD::CVTQT_: return "Alpha::CVTQT_";
156 case AlphaISD::CVTQS_: return "Alpha::CVTQS_";
157 case AlphaISD::CVTTQ_: return "Alpha::CVTTQ_";
158 case AlphaISD::GPRelHi: return "Alpha::GPRelHi";
159 case AlphaISD::GPRelLo: return "Alpha::GPRelLo";
160 case AlphaISD::RelLit: return "Alpha::RelLit";
161 case AlphaISD::GlobalRetAddr: return "Alpha::GlobalRetAddr";
162 case AlphaISD::CALL: return "Alpha::CALL";
163 case AlphaISD::DivCall: return "Alpha::DivCall";
164 case AlphaISD::RET_FLAG: return "Alpha::RET_FLAG";
165 case AlphaISD::COND_BRANCH_I: return "Alpha::COND_BRANCH_I";
166 case AlphaISD::COND_BRANCH_F: return "Alpha::COND_BRANCH_F";
170 static SDOperand LowerJumpTable(SDOperand Op, SelectionDAG &DAG) {
171 MVT::ValueType PtrVT = Op.getValueType();
172 JumpTableSDNode *JT = cast<JumpTableSDNode>(Op);
173 SDOperand JTI = DAG.getTargetJumpTable(JT->getIndex(), PtrVT);
174 SDOperand Zero = DAG.getConstant(0, PtrVT);
176 SDOperand Hi = DAG.getNode(AlphaISD::GPRelHi, MVT::i64, JTI,
177 DAG.getNode(ISD::GLOBAL_OFFSET_TABLE, MVT::i64));
178 SDOperand Lo = DAG.getNode(AlphaISD::GPRelLo, MVT::i64, JTI, Hi);
182 //http://www.cs.arizona.edu/computer.help/policy/DIGITAL_unix/
183 //AA-PY8AC-TET1_html/callCH3.html#BLOCK21
185 //For now, just use variable size stack frame format
187 //In a standard call, the first six items are passed in registers $16
188 //- $21 and/or registers $f16 - $f21. (See Section 4.1.2 for details
189 //of argument-to-register correspondence.) The remaining items are
190 //collected in a memory argument list that is a naturally aligned
191 //array of quadwords. In a standard call, this list, if present, must
192 //be passed at 0(SP).
193 //7 ... n 0(SP) ... (n-7)*8(SP)
201 static SDOperand LowerFORMAL_ARGUMENTS(SDOperand Op, SelectionDAG &DAG,
203 int &VarArgsOffset) {
204 MachineFunction &MF = DAG.getMachineFunction();
205 MachineFrameInfo *MFI = MF.getFrameInfo();
206 std::vector<SDOperand> ArgValues;
207 SDOperand Root = Op.getOperand(0);
209 AddLiveIn(MF, Alpha::R29, &Alpha::GPRCRegClass); //GP
210 AddLiveIn(MF, Alpha::R26, &Alpha::GPRCRegClass); //RA
212 unsigned args_int[] = {
213 Alpha::R16, Alpha::R17, Alpha::R18, Alpha::R19, Alpha::R20, Alpha::R21};
214 unsigned args_float[] = {
215 Alpha::F16, Alpha::F17, Alpha::F18, Alpha::F19, Alpha::F20, Alpha::F21};
217 for (unsigned ArgNo = 0, e = Op.Val->getNumValues()-1; ArgNo != e; ++ArgNo) {
219 MVT::ValueType ObjectVT = Op.getValue(ArgNo).getValueType();
225 cerr << "Unknown Type " << ObjectVT << "\n";
228 args_float[ArgNo] = AddLiveIn(MF, args_float[ArgNo],
229 &Alpha::F8RCRegClass);
230 ArgVal = DAG.getCopyFromReg(Root, args_float[ArgNo], ObjectVT);
233 args_float[ArgNo] = AddLiveIn(MF, args_float[ArgNo],
234 &Alpha::F4RCRegClass);
235 ArgVal = DAG.getCopyFromReg(Root, args_float[ArgNo], ObjectVT);
238 args_int[ArgNo] = AddLiveIn(MF, args_int[ArgNo],
239 &Alpha::GPRCRegClass);
240 ArgVal = DAG.getCopyFromReg(Root, args_int[ArgNo], MVT::i64);
244 // Create the frame index object for this incoming parameter...
245 int FI = MFI->CreateFixedObject(8, 8 * (ArgNo - 6));
247 // Create the SelectionDAG nodes corresponding to a load
248 //from this parameter
249 SDOperand FIN = DAG.getFrameIndex(FI, MVT::i64);
250 ArgVal = DAG.getLoad(ObjectVT, Root, FIN, NULL, 0);
252 ArgValues.push_back(ArgVal);
255 // If the functions takes variable number of arguments, copy all regs to stack
256 bool isVarArg = cast<ConstantSDNode>(Op.getOperand(2))->getValue() != 0;
258 VarArgsOffset = (Op.Val->getNumValues()-1) * 8;
259 std::vector<SDOperand> LS;
260 for (int i = 0; i < 6; ++i) {
261 if (MRegisterInfo::isPhysicalRegister(args_int[i]))
262 args_int[i] = AddLiveIn(MF, args_int[i], &Alpha::GPRCRegClass);
263 SDOperand argt = DAG.getCopyFromReg(Root, args_int[i], MVT::i64);
264 int FI = MFI->CreateFixedObject(8, -8 * (6 - i));
265 if (i == 0) VarArgsBase = FI;
266 SDOperand SDFI = DAG.getFrameIndex(FI, MVT::i64);
267 LS.push_back(DAG.getStore(Root, argt, SDFI, NULL, 0));
269 if (MRegisterInfo::isPhysicalRegister(args_float[i]))
270 args_float[i] = AddLiveIn(MF, args_float[i], &Alpha::F8RCRegClass);
271 argt = DAG.getCopyFromReg(Root, args_float[i], MVT::f64);
272 FI = MFI->CreateFixedObject(8, - 8 * (12 - i));
273 SDFI = DAG.getFrameIndex(FI, MVT::i64);
274 LS.push_back(DAG.getStore(Root, argt, SDFI, NULL, 0));
277 //Set up a token factor with all the stack traffic
278 Root = DAG.getNode(ISD::TokenFactor, MVT::Other, &LS[0], LS.size());
281 ArgValues.push_back(Root);
283 // Return the new list of results.
284 std::vector<MVT::ValueType> RetVT(Op.Val->value_begin(),
285 Op.Val->value_end());
286 return DAG.getNode(ISD::MERGE_VALUES, RetVT, &ArgValues[0], ArgValues.size());
289 static SDOperand LowerRET(SDOperand Op, SelectionDAG &DAG) {
290 SDOperand Copy = DAG.getCopyToReg(Op.getOperand(0), Alpha::R26,
291 DAG.getNode(AlphaISD::GlobalRetAddr,
294 switch (Op.getNumOperands()) {
296 assert(0 && "Do not know how to return this many arguments!");
300 //return SDOperand(); // ret void is legal
302 MVT::ValueType ArgVT = Op.getOperand(1).getValueType();
304 if (MVT::isInteger(ArgVT))
307 assert(MVT::isFloatingPoint(ArgVT));
310 Copy = DAG.getCopyToReg(Copy, ArgReg, Op.getOperand(1), Copy.getValue(1));
311 if(DAG.getMachineFunction().liveout_empty())
312 DAG.getMachineFunction().addLiveOut(ArgReg);
316 return DAG.getNode(AlphaISD::RET_FLAG, MVT::Other, Copy, Copy.getValue(1));
319 std::pair<SDOperand, SDOperand>
320 AlphaTargetLowering::LowerCallTo(SDOperand Chain,
321 const Type *RetTy, bool isVarArg,
322 unsigned CallingConv, bool isTailCall,
323 SDOperand Callee, ArgListTy &Args,
327 NumBytes = (Args.size() - 6) * 8;
329 Chain = DAG.getCALLSEQ_START(Chain,
330 DAG.getConstant(NumBytes, getPointerTy()));
331 std::vector<SDOperand> args_to_use;
332 for (unsigned i = 0, e = Args.size(); i != e; ++i)
334 switch (getValueType(Args[i].second)) {
335 default: assert(0 && "Unexpected ValueType for argument!");
340 // Promote the integer to 64 bits. If the input type is signed use a
341 // sign extend, otherwise use a zero extend.
342 if (Args[i].second->isSigned())
343 Args[i].first = DAG.getNode(ISD::SIGN_EXTEND, MVT::i64, Args[i].first);
345 Args[i].first = DAG.getNode(ISD::ZERO_EXTEND, MVT::i64, Args[i].first);
352 args_to_use.push_back(Args[i].first);
355 std::vector<MVT::ValueType> RetVals;
356 MVT::ValueType RetTyVT = getValueType(RetTy);
357 MVT::ValueType ActualRetTyVT = RetTyVT;
358 if (RetTyVT >= MVT::i1 && RetTyVT <= MVT::i32)
359 ActualRetTyVT = MVT::i64;
361 if (RetTyVT != MVT::isVoid)
362 RetVals.push_back(ActualRetTyVT);
363 RetVals.push_back(MVT::Other);
365 std::vector<SDOperand> Ops;
366 Ops.push_back(Chain);
367 Ops.push_back(Callee);
368 Ops.insert(Ops.end(), args_to_use.begin(), args_to_use.end());
369 SDOperand TheCall = DAG.getNode(AlphaISD::CALL, RetVals, &Ops[0], Ops.size());
370 Chain = TheCall.getValue(RetTyVT != MVT::isVoid);
371 Chain = DAG.getNode(ISD::CALLSEQ_END, MVT::Other, Chain,
372 DAG.getConstant(NumBytes, getPointerTy()));
373 SDOperand RetVal = TheCall;
375 if (RetTyVT != ActualRetTyVT) {
376 RetVal = DAG.getNode(RetTy->isSigned() ? ISD::AssertSext : ISD::AssertZext,
377 MVT::i64, RetVal, DAG.getValueType(RetTyVT));
378 RetVal = DAG.getNode(ISD::TRUNCATE, RetTyVT, RetVal);
381 return std::make_pair(RetVal, Chain);
384 /// LowerOperation - Provide custom lowering hooks for some operations.
386 SDOperand AlphaTargetLowering::LowerOperation(SDOperand Op, SelectionDAG &DAG) {
387 switch (Op.getOpcode()) {
388 default: assert(0 && "Wasn't expecting to be able to lower this!");
389 case ISD::FORMAL_ARGUMENTS: return LowerFORMAL_ARGUMENTS(Op, DAG,
393 case ISD::RET: return LowerRET(Op,DAG);
394 case ISD::JumpTable: return LowerJumpTable(Op, DAG);
396 case ISD::SINT_TO_FP: {
397 assert(MVT::i64 == Op.getOperand(0).getValueType() &&
398 "Unhandled SINT_TO_FP type in custom expander!");
400 bool isDouble = MVT::f64 == Op.getValueType();
402 LD = DAG.getNode(AlphaISD::ITOFT_, MVT::f64, Op.getOperand(0));
405 DAG.getMachineFunction().getFrameInfo()->CreateStackObject(8, 8);
406 SDOperand FI = DAG.getFrameIndex(FrameIdx, MVT::i64);
407 SDOperand ST = DAG.getStore(DAG.getEntryNode(),
408 Op.getOperand(0), FI, NULL, 0);
409 LD = DAG.getLoad(MVT::f64, ST, FI, NULL, 0);
411 SDOperand FP = DAG.getNode(isDouble?AlphaISD::CVTQT_:AlphaISD::CVTQS_,
412 isDouble?MVT::f64:MVT::f32, LD);
415 case ISD::FP_TO_SINT: {
416 bool isDouble = MVT::f64 == Op.getOperand(0).getValueType();
417 SDOperand src = Op.getOperand(0);
419 if (!isDouble) //Promote
420 src = DAG.getNode(ISD::FP_EXTEND, MVT::f64, src);
422 src = DAG.getNode(AlphaISD::CVTTQ_, MVT::f64, src);
425 return DAG.getNode(AlphaISD::FTOIT_, MVT::i64, src);
428 DAG.getMachineFunction().getFrameInfo()->CreateStackObject(8, 8);
429 SDOperand FI = DAG.getFrameIndex(FrameIdx, MVT::i64);
430 SDOperand ST = DAG.getStore(DAG.getEntryNode(), src, FI, NULL, 0);
431 return DAG.getLoad(MVT::i64, ST, FI, NULL, 0);
434 case ISD::ConstantPool: {
435 ConstantPoolSDNode *CP = cast<ConstantPoolSDNode>(Op);
436 Constant *C = CP->getConstVal();
437 SDOperand CPI = DAG.getTargetConstantPool(C, MVT::i64, CP->getAlignment());
439 SDOperand Hi = DAG.getNode(AlphaISD::GPRelHi, MVT::i64, CPI,
440 DAG.getNode(ISD::GLOBAL_OFFSET_TABLE, MVT::i64));
441 SDOperand Lo = DAG.getNode(AlphaISD::GPRelLo, MVT::i64, CPI, Hi);
444 case ISD::GlobalAddress: {
445 GlobalAddressSDNode *GSDN = cast<GlobalAddressSDNode>(Op);
446 GlobalValue *GV = GSDN->getGlobal();
447 SDOperand GA = DAG.getTargetGlobalAddress(GV, MVT::i64, GSDN->getOffset());
449 // if (!GV->hasWeakLinkage() && !GV->isExternal() && !GV->hasLinkOnceLinkage()) {
450 if (GV->hasInternalLinkage()) {
451 SDOperand Hi = DAG.getNode(AlphaISD::GPRelHi, MVT::i64, GA,
452 DAG.getNode(ISD::GLOBAL_OFFSET_TABLE, MVT::i64));
453 SDOperand Lo = DAG.getNode(AlphaISD::GPRelLo, MVT::i64, GA, Hi);
456 return DAG.getNode(AlphaISD::RelLit, MVT::i64, GA,
457 DAG.getNode(ISD::GLOBAL_OFFSET_TABLE, MVT::i64));
459 case ISD::ExternalSymbol: {
460 return DAG.getNode(AlphaISD::RelLit, MVT::i64,
461 DAG.getTargetExternalSymbol(cast<ExternalSymbolSDNode>(Op)
462 ->getSymbol(), MVT::i64),
463 DAG.getNode(ISD::GLOBAL_OFFSET_TABLE, MVT::i64));
468 //Expand only on constant case
469 if (Op.getOperand(1).getOpcode() == ISD::Constant) {
470 MVT::ValueType VT = Op.Val->getValueType(0);
471 SDOperand Tmp1 = Op.Val->getOpcode() == ISD::UREM ?
472 BuildUDIV(Op.Val, DAG, NULL) :
473 BuildSDIV(Op.Val, DAG, NULL);
474 Tmp1 = DAG.getNode(ISD::MUL, VT, Tmp1, Op.getOperand(1));
475 Tmp1 = DAG.getNode(ISD::SUB, VT, Op.getOperand(0), Tmp1);
481 if (MVT::isInteger(Op.getValueType())) {
482 if (Op.getOperand(1).getOpcode() == ISD::Constant)
483 return Op.getOpcode() == ISD::SDIV ? BuildSDIV(Op.Val, DAG, NULL)
484 : BuildUDIV(Op.Val, DAG, NULL);
485 const char* opstr = 0;
486 switch(Op.getOpcode()) {
487 case ISD::UREM: opstr = "__remqu"; break;
488 case ISD::SREM: opstr = "__remq"; break;
489 case ISD::UDIV: opstr = "__divqu"; break;
490 case ISD::SDIV: opstr = "__divq"; break;
492 SDOperand Tmp1 = Op.getOperand(0),
493 Tmp2 = Op.getOperand(1),
494 Addr = DAG.getExternalSymbol(opstr, MVT::i64);
495 return DAG.getNode(AlphaISD::DivCall, MVT::i64, Addr, Tmp1, Tmp2);
500 SDOperand Chain = Op.getOperand(0);
501 SDOperand VAListP = Op.getOperand(1);
502 SrcValueSDNode *VAListS = cast<SrcValueSDNode>(Op.getOperand(2));
504 SDOperand Base = DAG.getLoad(MVT::i64, Chain, VAListP, VAListS->getValue(),
505 VAListS->getOffset());
506 SDOperand Tmp = DAG.getNode(ISD::ADD, MVT::i64, VAListP,
507 DAG.getConstant(8, MVT::i64));
508 SDOperand Offset = DAG.getExtLoad(ISD::SEXTLOAD, MVT::i64, Base.getValue(1),
509 Tmp, NULL, 0, MVT::i32);
510 SDOperand DataPtr = DAG.getNode(ISD::ADD, MVT::i64, Base, Offset);
511 if (MVT::isFloatingPoint(Op.getValueType()))
513 //if fp && Offset < 6*8, then subtract 6*8 from DataPtr
514 SDOperand FPDataPtr = DAG.getNode(ISD::SUB, MVT::i64, DataPtr,
515 DAG.getConstant(8*6, MVT::i64));
516 SDOperand CC = DAG.getSetCC(MVT::i64, Offset,
517 DAG.getConstant(8*6, MVT::i64), ISD::SETLT);
518 DataPtr = DAG.getNode(ISD::SELECT, MVT::i64, CC, FPDataPtr, DataPtr);
521 SDOperand NewOffset = DAG.getNode(ISD::ADD, MVT::i64, Offset,
522 DAG.getConstant(8, MVT::i64));
523 SDOperand Update = DAG.getTruncStore(Offset.getValue(1), NewOffset,
524 Tmp, NULL, 0, MVT::i32);
527 if (Op.getValueType() == MVT::i32)
528 Result = DAG.getExtLoad(ISD::SEXTLOAD, MVT::i64, Update, DataPtr,
531 Result = DAG.getLoad(Op.getValueType(), Update, DataPtr, NULL, 0);
535 SDOperand Chain = Op.getOperand(0);
536 SDOperand DestP = Op.getOperand(1);
537 SDOperand SrcP = Op.getOperand(2);
538 SrcValueSDNode *DestS = cast<SrcValueSDNode>(Op.getOperand(3));
539 SrcValueSDNode *SrcS = cast<SrcValueSDNode>(Op.getOperand(4));
541 SDOperand Val = DAG.getLoad(getPointerTy(), Chain, SrcP,
542 SrcS->getValue(), SrcS->getOffset());
543 SDOperand Result = DAG.getStore(Val.getValue(1), Val, DestP, DestS->getValue(),
545 SDOperand NP = DAG.getNode(ISD::ADD, MVT::i64, SrcP,
546 DAG.getConstant(8, MVT::i64));
547 Val = DAG.getExtLoad(ISD::SEXTLOAD, MVT::i64, Result, NP, NULL,0, MVT::i32);
548 SDOperand NPD = DAG.getNode(ISD::ADD, MVT::i64, DestP,
549 DAG.getConstant(8, MVT::i64));
550 return DAG.getTruncStore(Val.getValue(1), Val, NPD, NULL, 0, MVT::i32);
553 SDOperand Chain = Op.getOperand(0);
554 SDOperand VAListP = Op.getOperand(1);
555 SrcValueSDNode *VAListS = cast<SrcValueSDNode>(Op.getOperand(2));
557 // vastart stores the address of the VarArgsBase and VarArgsOffset
558 SDOperand FR = DAG.getFrameIndex(VarArgsBase, MVT::i64);
559 SDOperand S1 = DAG.getStore(Chain, FR, VAListP, VAListS->getValue(),
560 VAListS->getOffset());
561 SDOperand SA2 = DAG.getNode(ISD::ADD, MVT::i64, VAListP,
562 DAG.getConstant(8, MVT::i64));
563 return DAG.getTruncStore(S1, DAG.getConstant(VarArgsOffset, MVT::i64),
564 SA2, NULL, 0, MVT::i32);
571 SDOperand AlphaTargetLowering::CustomPromoteOperation(SDOperand Op,
573 assert(Op.getValueType() == MVT::i32 &&
574 Op.getOpcode() == ISD::VAARG &&
575 "Unknown node to custom promote!");
577 // The code in LowerOperation already handles i32 vaarg
578 return LowerOperation(Op, DAG);
584 /// getConstraintType - Given a constraint letter, return the type of
585 /// constraint it is for this target.
586 AlphaTargetLowering::ConstraintType
587 AlphaTargetLowering::getConstraintType(char ConstraintLetter) const {
588 switch (ConstraintLetter) {
592 return C_RegisterClass;
594 return TargetLowering::getConstraintType(ConstraintLetter);
597 std::vector<unsigned> AlphaTargetLowering::
598 getRegClassForInlineAsmConstraint(const std::string &Constraint,
599 MVT::ValueType VT) const {
600 if (Constraint.size() == 1) {
601 switch (Constraint[0]) {
602 default: break; // Unknown constriant letter
604 return make_vector<unsigned>(Alpha::F0 , Alpha::F1 , Alpha::F2 ,
605 Alpha::F3 , Alpha::F4 , Alpha::F5 ,
606 Alpha::F6 , Alpha::F7 , Alpha::F8 ,
607 Alpha::F9 , Alpha::F10, Alpha::F11,
608 Alpha::F12, Alpha::F13, Alpha::F14,
609 Alpha::F15, Alpha::F16, Alpha::F17,
610 Alpha::F18, Alpha::F19, Alpha::F20,
611 Alpha::F21, Alpha::F22, Alpha::F23,
612 Alpha::F24, Alpha::F25, Alpha::F26,
613 Alpha::F27, Alpha::F28, Alpha::F29,
614 Alpha::F30, Alpha::F31, 0);
616 return make_vector<unsigned>(Alpha::R0 , Alpha::R1 , Alpha::R2 ,
617 Alpha::R3 , Alpha::R4 , Alpha::R5 ,
618 Alpha::R6 , Alpha::R7 , Alpha::R8 ,
619 Alpha::R9 , Alpha::R10, Alpha::R11,
620 Alpha::R12, Alpha::R13, Alpha::R14,
621 Alpha::R15, Alpha::R16, Alpha::R17,
622 Alpha::R18, Alpha::R19, Alpha::R20,
623 Alpha::R21, Alpha::R22, Alpha::R23,
624 Alpha::R24, Alpha::R25, Alpha::R26,
625 Alpha::R27, Alpha::R28, Alpha::R29,
626 Alpha::R30, Alpha::R31, 0);
631 return std::vector<unsigned>();