1 //===-- AlphaISelLowering.cpp - Alpha DAG Lowering Implementation ---------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file implements the AlphaISelLowering class.
12 //===----------------------------------------------------------------------===//
14 #include "AlphaISelLowering.h"
15 #include "AlphaTargetMachine.h"
16 #include "llvm/CodeGen/MachineFrameInfo.h"
17 #include "llvm/CodeGen/MachineFunction.h"
18 #include "llvm/CodeGen/MachineInstrBuilder.h"
19 #include "llvm/CodeGen/MachineRegisterInfo.h"
20 #include "llvm/CodeGen/SelectionDAG.h"
21 #include "llvm/CodeGen/MachineRegisterInfo.h"
22 #include "llvm/Constants.h"
23 #include "llvm/Function.h"
24 #include "llvm/Module.h"
25 #include "llvm/Support/CommandLine.h"
28 /// AddLiveIn - This helper function adds the specified physical register to the
29 /// MachineFunction as a live in value. It also creates a corresponding virtual
31 static unsigned AddLiveIn(MachineFunction &MF, unsigned PReg,
32 TargetRegisterClass *RC) {
33 assert(RC->contains(PReg) && "Not the correct regclass!");
34 unsigned VReg = MF.getRegInfo().createVirtualRegister(RC);
35 MF.getRegInfo().addLiveIn(PReg, VReg);
39 AlphaTargetLowering::AlphaTargetLowering(TargetMachine &TM) : TargetLowering(TM) {
40 // Set up the TargetLowering object.
41 //I am having problems with shr n ubyte 1
42 setShiftAmountType(MVT::i64);
43 setSetCCResultContents(ZeroOrOneSetCCResult);
45 setUsesGlobalOffsetTable(true);
47 addRegisterClass(MVT::i64, Alpha::GPRCRegisterClass);
48 addRegisterClass(MVT::f64, Alpha::F8RCRegisterClass);
49 addRegisterClass(MVT::f32, Alpha::F4RCRegisterClass);
51 setLoadXAction(ISD::EXTLOAD, MVT::i1, Promote);
52 setLoadXAction(ISD::EXTLOAD, MVT::f32, Expand);
54 setLoadXAction(ISD::ZEXTLOAD, MVT::i1, Promote);
55 setLoadXAction(ISD::ZEXTLOAD, MVT::i32, Expand);
57 setLoadXAction(ISD::SEXTLOAD, MVT::i1, Promote);
58 setLoadXAction(ISD::SEXTLOAD, MVT::i8, Expand);
59 setLoadXAction(ISD::SEXTLOAD, MVT::i16, Expand);
61 // setOperationAction(ISD::BRIND, MVT::Other, Expand);
62 setOperationAction(ISD::BR_JT, MVT::Other, Expand);
63 setOperationAction(ISD::BR_CC, MVT::Other, Expand);
64 setOperationAction(ISD::SELECT_CC, MVT::Other, Expand);
66 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1, Expand);
68 setOperationAction(ISD::FREM, MVT::f32, Expand);
69 setOperationAction(ISD::FREM, MVT::f64, Expand);
71 setOperationAction(ISD::UINT_TO_FP, MVT::i64, Expand);
72 setOperationAction(ISD::SINT_TO_FP, MVT::i64, Custom);
73 setOperationAction(ISD::FP_TO_UINT, MVT::i64, Expand);
74 setOperationAction(ISD::FP_TO_SINT, MVT::i64, Custom);
76 if (!TM.getSubtarget<AlphaSubtarget>().hasCT()) {
77 setOperationAction(ISD::CTPOP , MVT::i64 , Expand);
78 setOperationAction(ISD::CTTZ , MVT::i64 , Expand);
79 setOperationAction(ISD::CTLZ , MVT::i64 , Expand);
81 setOperationAction(ISD::BSWAP , MVT::i64, Expand);
82 setOperationAction(ISD::ROTL , MVT::i64, Expand);
83 setOperationAction(ISD::ROTR , MVT::i64, Expand);
85 setOperationAction(ISD::SREM , MVT::i64, Custom);
86 setOperationAction(ISD::UREM , MVT::i64, Custom);
87 setOperationAction(ISD::SDIV , MVT::i64, Custom);
88 setOperationAction(ISD::UDIV , MVT::i64, Custom);
90 // We don't support sin/cos/sqrt/pow
91 setOperationAction(ISD::FSIN , MVT::f64, Expand);
92 setOperationAction(ISD::FCOS , MVT::f64, Expand);
93 setOperationAction(ISD::FSIN , MVT::f32, Expand);
94 setOperationAction(ISD::FCOS , MVT::f32, Expand);
96 setOperationAction(ISD::FSQRT, MVT::f64, Expand);
97 setOperationAction(ISD::FSQRT, MVT::f32, Expand);
99 setOperationAction(ISD::FPOW , MVT::f32, Expand);
100 setOperationAction(ISD::FPOW , MVT::f64, Expand);
102 setOperationAction(ISD::SETCC, MVT::f32, Promote);
104 setOperationAction(ISD::BIT_CONVERT, MVT::f32, Promote);
106 // We don't have line number support yet.
107 setOperationAction(ISD::LOCATION, MVT::Other, Expand);
108 setOperationAction(ISD::DEBUG_LOC, MVT::Other, Expand);
109 setOperationAction(ISD::LABEL, MVT::Other, Expand);
111 // Not implemented yet.
112 setOperationAction(ISD::STACKSAVE, MVT::Other, Expand);
113 setOperationAction(ISD::STACKRESTORE, MVT::Other, Expand);
114 setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i64, Expand);
116 // We want to legalize GlobalAddress and ConstantPool and
117 // ExternalSymbols nodes into the appropriate instructions to
118 // materialize the address.
119 setOperationAction(ISD::GlobalAddress, MVT::i64, Custom);
120 setOperationAction(ISD::ConstantPool, MVT::i64, Custom);
121 setOperationAction(ISD::ExternalSymbol, MVT::i64, Custom);
122 setOperationAction(ISD::GlobalTLSAddress, MVT::i64, Custom);
124 setOperationAction(ISD::VASTART, MVT::Other, Custom);
125 setOperationAction(ISD::VAEND, MVT::Other, Expand);
126 setOperationAction(ISD::VACOPY, MVT::Other, Custom);
127 setOperationAction(ISD::VAARG, MVT::Other, Custom);
128 setOperationAction(ISD::VAARG, MVT::i32, Custom);
130 setOperationAction(ISD::RET, MVT::Other, Custom);
132 setOperationAction(ISD::JumpTable, MVT::i64, Custom);
133 setOperationAction(ISD::JumpTable, MVT::i32, Custom);
135 setStackPointerRegisterToSaveRestore(Alpha::R30);
137 addLegalFPImmediate(APFloat(+0.0)); //F31
138 addLegalFPImmediate(APFloat(+0.0f)); //F31
139 addLegalFPImmediate(APFloat(-0.0)); //-F31
140 addLegalFPImmediate(APFloat(-0.0f)); //-F31
143 setJumpBufAlignment(16);
145 computeRegisterProperties();
148 MVT AlphaTargetLowering::getSetCCResultType(const SDOperand &) const {
152 const char *AlphaTargetLowering::getTargetNodeName(unsigned Opcode) const {
155 case AlphaISD::CVTQT_: return "Alpha::CVTQT_";
156 case AlphaISD::CVTQS_: return "Alpha::CVTQS_";
157 case AlphaISD::CVTTQ_: return "Alpha::CVTTQ_";
158 case AlphaISD::GPRelHi: return "Alpha::GPRelHi";
159 case AlphaISD::GPRelLo: return "Alpha::GPRelLo";
160 case AlphaISD::RelLit: return "Alpha::RelLit";
161 case AlphaISD::GlobalRetAddr: return "Alpha::GlobalRetAddr";
162 case AlphaISD::CALL: return "Alpha::CALL";
163 case AlphaISD::DivCall: return "Alpha::DivCall";
164 case AlphaISD::RET_FLAG: return "Alpha::RET_FLAG";
165 case AlphaISD::COND_BRANCH_I: return "Alpha::COND_BRANCH_I";
166 case AlphaISD::COND_BRANCH_F: return "Alpha::COND_BRANCH_F";
170 static SDOperand LowerJumpTable(SDOperand Op, SelectionDAG &DAG) {
171 MVT PtrVT = Op.getValueType();
172 JumpTableSDNode *JT = cast<JumpTableSDNode>(Op);
173 SDOperand JTI = DAG.getTargetJumpTable(JT->getIndex(), PtrVT);
174 SDOperand Zero = DAG.getConstant(0, PtrVT);
176 SDOperand Hi = DAG.getNode(AlphaISD::GPRelHi, MVT::i64, JTI,
177 DAG.getNode(ISD::GLOBAL_OFFSET_TABLE, MVT::i64));
178 SDOperand Lo = DAG.getNode(AlphaISD::GPRelLo, MVT::i64, JTI, Hi);
182 //http://www.cs.arizona.edu/computer.help/policy/DIGITAL_unix/
183 //AA-PY8AC-TET1_html/callCH3.html#BLOCK21
185 //For now, just use variable size stack frame format
187 //In a standard call, the first six items are passed in registers $16
188 //- $21 and/or registers $f16 - $f21. (See Section 4.1.2 for details
189 //of argument-to-register correspondence.) The remaining items are
190 //collected in a memory argument list that is a naturally aligned
191 //array of quadwords. In a standard call, this list, if present, must
192 //be passed at 0(SP).
193 //7 ... n 0(SP) ... (n-7)*8(SP)
201 static SDOperand LowerFORMAL_ARGUMENTS(SDOperand Op, SelectionDAG &DAG,
203 int &VarArgsOffset) {
204 MachineFunction &MF = DAG.getMachineFunction();
205 MachineFrameInfo *MFI = MF.getFrameInfo();
206 std::vector<SDOperand> ArgValues;
207 SDOperand Root = Op.getOperand(0);
209 AddLiveIn(MF, Alpha::R29, &Alpha::GPRCRegClass); //GP
210 AddLiveIn(MF, Alpha::R26, &Alpha::GPRCRegClass); //RA
212 unsigned args_int[] = {
213 Alpha::R16, Alpha::R17, Alpha::R18, Alpha::R19, Alpha::R20, Alpha::R21};
214 unsigned args_float[] = {
215 Alpha::F16, Alpha::F17, Alpha::F18, Alpha::F19, Alpha::F20, Alpha::F21};
217 for (unsigned ArgNo = 0, e = Op.Val->getNumValues()-1; ArgNo != e; ++ArgNo) {
219 MVT ObjectVT = Op.getValue(ArgNo).getValueType();
223 switch (ObjectVT.getSimpleVT()) {
225 assert(false && "Invalid value type!");
227 args_float[ArgNo] = AddLiveIn(MF, args_float[ArgNo],
228 &Alpha::F8RCRegClass);
229 ArgVal = DAG.getCopyFromReg(Root, args_float[ArgNo], ObjectVT);
232 args_float[ArgNo] = AddLiveIn(MF, args_float[ArgNo],
233 &Alpha::F4RCRegClass);
234 ArgVal = DAG.getCopyFromReg(Root, args_float[ArgNo], ObjectVT);
237 args_int[ArgNo] = AddLiveIn(MF, args_int[ArgNo],
238 &Alpha::GPRCRegClass);
239 ArgVal = DAG.getCopyFromReg(Root, args_int[ArgNo], MVT::i64);
243 // Create the frame index object for this incoming parameter...
244 int FI = MFI->CreateFixedObject(8, 8 * (ArgNo - 6));
246 // Create the SelectionDAG nodes corresponding to a load
247 //from this parameter
248 SDOperand FIN = DAG.getFrameIndex(FI, MVT::i64);
249 ArgVal = DAG.getLoad(ObjectVT, Root, FIN, NULL, 0);
251 ArgValues.push_back(ArgVal);
254 // If the functions takes variable number of arguments, copy all regs to stack
255 bool isVarArg = cast<ConstantSDNode>(Op.getOperand(2))->getValue() != 0;
257 VarArgsOffset = (Op.Val->getNumValues()-1) * 8;
258 std::vector<SDOperand> LS;
259 for (int i = 0; i < 6; ++i) {
260 if (TargetRegisterInfo::isPhysicalRegister(args_int[i]))
261 args_int[i] = AddLiveIn(MF, args_int[i], &Alpha::GPRCRegClass);
262 SDOperand argt = DAG.getCopyFromReg(Root, args_int[i], MVT::i64);
263 int FI = MFI->CreateFixedObject(8, -8 * (6 - i));
264 if (i == 0) VarArgsBase = FI;
265 SDOperand SDFI = DAG.getFrameIndex(FI, MVT::i64);
266 LS.push_back(DAG.getStore(Root, argt, SDFI, NULL, 0));
268 if (TargetRegisterInfo::isPhysicalRegister(args_float[i]))
269 args_float[i] = AddLiveIn(MF, args_float[i], &Alpha::F8RCRegClass);
270 argt = DAG.getCopyFromReg(Root, args_float[i], MVT::f64);
271 FI = MFI->CreateFixedObject(8, - 8 * (12 - i));
272 SDFI = DAG.getFrameIndex(FI, MVT::i64);
273 LS.push_back(DAG.getStore(Root, argt, SDFI, NULL, 0));
276 //Set up a token factor with all the stack traffic
277 Root = DAG.getNode(ISD::TokenFactor, MVT::Other, &LS[0], LS.size());
280 ArgValues.push_back(Root);
282 // Return the new list of results.
283 return DAG.getMergeValues(Op.Val->getVTList(), &ArgValues[0],
287 static SDOperand LowerRET(SDOperand Op, SelectionDAG &DAG) {
288 SDOperand Copy = DAG.getCopyToReg(Op.getOperand(0), Alpha::R26,
289 DAG.getNode(AlphaISD::GlobalRetAddr,
292 switch (Op.getNumOperands()) {
294 assert(0 && "Do not know how to return this many arguments!");
298 //return SDOperand(); // ret void is legal
300 MVT ArgVT = Op.getOperand(1).getValueType();
302 if (ArgVT.isInteger())
305 assert(ArgVT.isFloatingPoint());
308 Copy = DAG.getCopyToReg(Copy, ArgReg, Op.getOperand(1), Copy.getValue(1));
309 if (DAG.getMachineFunction().getRegInfo().liveout_empty())
310 DAG.getMachineFunction().getRegInfo().addLiveOut(ArgReg);
314 return DAG.getNode(AlphaISD::RET_FLAG, MVT::Other, Copy, Copy.getValue(1));
317 std::pair<SDOperand, SDOperand>
318 AlphaTargetLowering::LowerCallTo(SDOperand Chain, const Type *RetTy,
319 bool RetSExt, bool RetZExt, bool isVarArg,
320 unsigned CallingConv, bool isTailCall,
321 SDOperand Callee, ArgListTy &Args,
325 NumBytes = (Args.size() - 6) * 8;
327 Chain = DAG.getCALLSEQ_START(Chain,
328 DAG.getConstant(NumBytes, getPointerTy()));
329 std::vector<SDOperand> args_to_use;
330 for (unsigned i = 0, e = Args.size(); i != e; ++i)
332 switch (getValueType(Args[i].Ty).getSimpleVT()) {
333 default: assert(0 && "Unexpected ValueType for argument!");
338 // Promote the integer to 64 bits. If the input type is signed use a
339 // sign extend, otherwise use a zero extend.
341 Args[i].Node = DAG.getNode(ISD::SIGN_EXTEND, MVT::i64, Args[i].Node);
342 else if (Args[i].isZExt)
343 Args[i].Node = DAG.getNode(ISD::ZERO_EXTEND, MVT::i64, Args[i].Node);
345 Args[i].Node = DAG.getNode(ISD::ANY_EXTEND, MVT::i64, Args[i].Node);
352 args_to_use.push_back(Args[i].Node);
355 std::vector<MVT> RetVals;
356 MVT RetTyVT = getValueType(RetTy);
357 MVT ActualRetTyVT = RetTyVT;
358 if (RetTyVT.getSimpleVT() >= MVT::i1 && RetTyVT.getSimpleVT() <= MVT::i32)
359 ActualRetTyVT = MVT::i64;
361 if (RetTyVT != MVT::isVoid)
362 RetVals.push_back(ActualRetTyVT);
363 RetVals.push_back(MVT::Other);
365 std::vector<SDOperand> Ops;
366 Ops.push_back(Chain);
367 Ops.push_back(Callee);
368 Ops.insert(Ops.end(), args_to_use.begin(), args_to_use.end());
369 SDOperand TheCall = DAG.getNode(AlphaISD::CALL, RetVals, &Ops[0], Ops.size());
370 Chain = TheCall.getValue(RetTyVT != MVT::isVoid);
371 Chain = DAG.getCALLSEQ_END(Chain,
372 DAG.getConstant(NumBytes, getPointerTy()),
373 DAG.getConstant(0, getPointerTy()),
375 SDOperand RetVal = TheCall;
377 if (RetTyVT != ActualRetTyVT) {
378 ISD::NodeType AssertKind = ISD::DELETED_NODE;
380 AssertKind = ISD::AssertSext;
382 AssertKind = ISD::AssertZext;
384 if (AssertKind != ISD::DELETED_NODE)
385 RetVal = DAG.getNode(AssertKind, MVT::i64, RetVal,
386 DAG.getValueType(RetTyVT));
388 RetVal = DAG.getNode(ISD::TRUNCATE, RetTyVT, RetVal);
391 return std::make_pair(RetVal, Chain);
394 /// LowerOperation - Provide custom lowering hooks for some operations.
396 SDOperand AlphaTargetLowering::LowerOperation(SDOperand Op, SelectionDAG &DAG) {
397 switch (Op.getOpcode()) {
398 default: assert(0 && "Wasn't expecting to be able to lower this!");
399 case ISD::FORMAL_ARGUMENTS: return LowerFORMAL_ARGUMENTS(Op, DAG,
403 case ISD::RET: return LowerRET(Op,DAG);
404 case ISD::JumpTable: return LowerJumpTable(Op, DAG);
406 case ISD::SINT_TO_FP: {
407 assert(Op.getOperand(0).getValueType() == MVT::i64 &&
408 "Unhandled SINT_TO_FP type in custom expander!");
410 bool isDouble = Op.getValueType() == MVT::f64;
411 LD = DAG.getNode(ISD::BIT_CONVERT, MVT::f64, Op.getOperand(0));
412 SDOperand FP = DAG.getNode(isDouble?AlphaISD::CVTQT_:AlphaISD::CVTQS_,
413 isDouble?MVT::f64:MVT::f32, LD);
416 case ISD::FP_TO_SINT: {
417 bool isDouble = Op.getOperand(0).getValueType() == MVT::f64;
418 SDOperand src = Op.getOperand(0);
420 if (!isDouble) //Promote
421 src = DAG.getNode(ISD::FP_EXTEND, MVT::f64, src);
423 src = DAG.getNode(AlphaISD::CVTTQ_, MVT::f64, src);
425 return DAG.getNode(ISD::BIT_CONVERT, MVT::i64, src);
427 case ISD::ConstantPool: {
428 ConstantPoolSDNode *CP = cast<ConstantPoolSDNode>(Op);
429 Constant *C = CP->getConstVal();
430 SDOperand CPI = DAG.getTargetConstantPool(C, MVT::i64, CP->getAlignment());
432 SDOperand Hi = DAG.getNode(AlphaISD::GPRelHi, MVT::i64, CPI,
433 DAG.getNode(ISD::GLOBAL_OFFSET_TABLE, MVT::i64));
434 SDOperand Lo = DAG.getNode(AlphaISD::GPRelLo, MVT::i64, CPI, Hi);
437 case ISD::GlobalTLSAddress:
438 assert(0 && "TLS not implemented for Alpha.");
439 case ISD::GlobalAddress: {
440 GlobalAddressSDNode *GSDN = cast<GlobalAddressSDNode>(Op);
441 GlobalValue *GV = GSDN->getGlobal();
442 SDOperand GA = DAG.getTargetGlobalAddress(GV, MVT::i64, GSDN->getOffset());
444 // if (!GV->hasWeakLinkage() && !GV->isDeclaration() && !GV->hasLinkOnceLinkage()) {
445 if (GV->hasInternalLinkage()) {
446 SDOperand Hi = DAG.getNode(AlphaISD::GPRelHi, MVT::i64, GA,
447 DAG.getNode(ISD::GLOBAL_OFFSET_TABLE, MVT::i64));
448 SDOperand Lo = DAG.getNode(AlphaISD::GPRelLo, MVT::i64, GA, Hi);
451 return DAG.getNode(AlphaISD::RelLit, MVT::i64, GA,
452 DAG.getNode(ISD::GLOBAL_OFFSET_TABLE, MVT::i64));
454 case ISD::ExternalSymbol: {
455 return DAG.getNode(AlphaISD::RelLit, MVT::i64,
456 DAG.getTargetExternalSymbol(cast<ExternalSymbolSDNode>(Op)
457 ->getSymbol(), MVT::i64),
458 DAG.getNode(ISD::GLOBAL_OFFSET_TABLE, MVT::i64));
463 //Expand only on constant case
464 if (Op.getOperand(1).getOpcode() == ISD::Constant) {
465 MVT VT = Op.Val->getValueType(0);
466 SDOperand Tmp1 = Op.Val->getOpcode() == ISD::UREM ?
467 BuildUDIV(Op.Val, DAG, NULL) :
468 BuildSDIV(Op.Val, DAG, NULL);
469 Tmp1 = DAG.getNode(ISD::MUL, VT, Tmp1, Op.getOperand(1));
470 Tmp1 = DAG.getNode(ISD::SUB, VT, Op.getOperand(0), Tmp1);
476 if (Op.getValueType().isInteger()) {
477 if (Op.getOperand(1).getOpcode() == ISD::Constant)
478 return Op.getOpcode() == ISD::SDIV ? BuildSDIV(Op.Val, DAG, NULL)
479 : BuildUDIV(Op.Val, DAG, NULL);
480 const char* opstr = 0;
481 switch (Op.getOpcode()) {
482 case ISD::UREM: opstr = "__remqu"; break;
483 case ISD::SREM: opstr = "__remq"; break;
484 case ISD::UDIV: opstr = "__divqu"; break;
485 case ISD::SDIV: opstr = "__divq"; break;
487 SDOperand Tmp1 = Op.getOperand(0),
488 Tmp2 = Op.getOperand(1),
489 Addr = DAG.getExternalSymbol(opstr, MVT::i64);
490 return DAG.getNode(AlphaISD::DivCall, MVT::i64, Addr, Tmp1, Tmp2);
495 SDOperand Chain = Op.getOperand(0);
496 SDOperand VAListP = Op.getOperand(1);
497 const Value *VAListS = cast<SrcValueSDNode>(Op.getOperand(2))->getValue();
499 SDOperand Base = DAG.getLoad(MVT::i64, Chain, VAListP, VAListS, 0);
500 SDOperand Tmp = DAG.getNode(ISD::ADD, MVT::i64, VAListP,
501 DAG.getConstant(8, MVT::i64));
502 SDOperand Offset = DAG.getExtLoad(ISD::SEXTLOAD, MVT::i64, Base.getValue(1),
503 Tmp, NULL, 0, MVT::i32);
504 SDOperand DataPtr = DAG.getNode(ISD::ADD, MVT::i64, Base, Offset);
505 if (Op.getValueType().isFloatingPoint())
507 //if fp && Offset < 6*8, then subtract 6*8 from DataPtr
508 SDOperand FPDataPtr = DAG.getNode(ISD::SUB, MVT::i64, DataPtr,
509 DAG.getConstant(8*6, MVT::i64));
510 SDOperand CC = DAG.getSetCC(MVT::i64, Offset,
511 DAG.getConstant(8*6, MVT::i64), ISD::SETLT);
512 DataPtr = DAG.getNode(ISD::SELECT, MVT::i64, CC, FPDataPtr, DataPtr);
515 SDOperand NewOffset = DAG.getNode(ISD::ADD, MVT::i64, Offset,
516 DAG.getConstant(8, MVT::i64));
517 SDOperand Update = DAG.getTruncStore(Offset.getValue(1), NewOffset,
518 Tmp, NULL, 0, MVT::i32);
521 if (Op.getValueType() == MVT::i32)
522 Result = DAG.getExtLoad(ISD::SEXTLOAD, MVT::i64, Update, DataPtr,
525 Result = DAG.getLoad(Op.getValueType(), Update, DataPtr, NULL, 0);
529 SDOperand Chain = Op.getOperand(0);
530 SDOperand DestP = Op.getOperand(1);
531 SDOperand SrcP = Op.getOperand(2);
532 const Value *DestS = cast<SrcValueSDNode>(Op.getOperand(3))->getValue();
533 const Value *SrcS = cast<SrcValueSDNode>(Op.getOperand(4))->getValue();
535 SDOperand Val = DAG.getLoad(getPointerTy(), Chain, SrcP, SrcS, 0);
536 SDOperand Result = DAG.getStore(Val.getValue(1), Val, DestP, DestS, 0);
537 SDOperand NP = DAG.getNode(ISD::ADD, MVT::i64, SrcP,
538 DAG.getConstant(8, MVT::i64));
539 Val = DAG.getExtLoad(ISD::SEXTLOAD, MVT::i64, Result, NP, NULL,0, MVT::i32);
540 SDOperand NPD = DAG.getNode(ISD::ADD, MVT::i64, DestP,
541 DAG.getConstant(8, MVT::i64));
542 return DAG.getTruncStore(Val.getValue(1), Val, NPD, NULL, 0, MVT::i32);
545 SDOperand Chain = Op.getOperand(0);
546 SDOperand VAListP = Op.getOperand(1);
547 const Value *VAListS = cast<SrcValueSDNode>(Op.getOperand(2))->getValue();
549 // vastart stores the address of the VarArgsBase and VarArgsOffset
550 SDOperand FR = DAG.getFrameIndex(VarArgsBase, MVT::i64);
551 SDOperand S1 = DAG.getStore(Chain, FR, VAListP, VAListS, 0);
552 SDOperand SA2 = DAG.getNode(ISD::ADD, MVT::i64, VAListP,
553 DAG.getConstant(8, MVT::i64));
554 return DAG.getTruncStore(S1, DAG.getConstant(VarArgsOffset, MVT::i64),
555 SA2, NULL, 0, MVT::i32);
557 case ISD::RETURNADDR:
558 return DAG.getNode(AlphaISD::GlobalRetAddr, MVT::i64);
560 case ISD::FRAMEADDR: break;
566 SDOperand AlphaTargetLowering::CustomPromoteOperation(SDOperand Op,
568 assert(Op.getValueType() == MVT::i32 &&
569 Op.getOpcode() == ISD::VAARG &&
570 "Unknown node to custom promote!");
572 // The code in LowerOperation already handles i32 vaarg
573 return LowerOperation(Op, DAG);
579 /// getConstraintType - Given a constraint letter, return the type of
580 /// constraint it is for this target.
581 AlphaTargetLowering::ConstraintType
582 AlphaTargetLowering::getConstraintType(const std::string &Constraint) const {
583 if (Constraint.size() == 1) {
584 switch (Constraint[0]) {
588 return C_RegisterClass;
591 return TargetLowering::getConstraintType(Constraint);
594 std::vector<unsigned> AlphaTargetLowering::
595 getRegClassForInlineAsmConstraint(const std::string &Constraint,
597 if (Constraint.size() == 1) {
598 switch (Constraint[0]) {
599 default: break; // Unknown constriant letter
601 return make_vector<unsigned>(Alpha::F0 , Alpha::F1 , Alpha::F2 ,
602 Alpha::F3 , Alpha::F4 , Alpha::F5 ,
603 Alpha::F6 , Alpha::F7 , Alpha::F8 ,
604 Alpha::F9 , Alpha::F10, Alpha::F11,
605 Alpha::F12, Alpha::F13, Alpha::F14,
606 Alpha::F15, Alpha::F16, Alpha::F17,
607 Alpha::F18, Alpha::F19, Alpha::F20,
608 Alpha::F21, Alpha::F22, Alpha::F23,
609 Alpha::F24, Alpha::F25, Alpha::F26,
610 Alpha::F27, Alpha::F28, Alpha::F29,
611 Alpha::F30, Alpha::F31, 0);
613 return make_vector<unsigned>(Alpha::R0 , Alpha::R1 , Alpha::R2 ,
614 Alpha::R3 , Alpha::R4 , Alpha::R5 ,
615 Alpha::R6 , Alpha::R7 , Alpha::R8 ,
616 Alpha::R9 , Alpha::R10, Alpha::R11,
617 Alpha::R12, Alpha::R13, Alpha::R14,
618 Alpha::R15, Alpha::R16, Alpha::R17,
619 Alpha::R18, Alpha::R19, Alpha::R20,
620 Alpha::R21, Alpha::R22, Alpha::R23,
621 Alpha::R24, Alpha::R25, Alpha::R26,
622 Alpha::R27, Alpha::R28, Alpha::R29,
623 Alpha::R30, Alpha::R31, 0);
627 return std::vector<unsigned>();
629 //===----------------------------------------------------------------------===//
630 // Other Lowering Code
631 //===----------------------------------------------------------------------===//
634 AlphaTargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI,
635 MachineBasicBlock *BB) {
636 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
637 assert((MI->getOpcode() == Alpha::CAS32 ||
638 MI->getOpcode() == Alpha::CAS64 ||
639 MI->getOpcode() == Alpha::LAS32 ||
640 MI->getOpcode() == Alpha::LAS64 ||
641 MI->getOpcode() == Alpha::SWAP32 ||
642 MI->getOpcode() == Alpha::SWAP64) &&
643 "Unexpected instr type to insert");
645 bool is32 = MI->getOpcode() == Alpha::CAS32 ||
646 MI->getOpcode() == Alpha::LAS32 ||
647 MI->getOpcode() == Alpha::SWAP32;
649 //Load locked store conditional for atomic ops take on the same form
652 //do stuff (maybe branch to exit)
654 //test sc and maybe branck to start
656 const BasicBlock *LLVM_BB = BB->getBasicBlock();
657 ilist<MachineBasicBlock>::iterator It = BB;
660 MachineBasicBlock *thisMBB = BB;
661 MachineBasicBlock *llscMBB = new MachineBasicBlock(LLVM_BB);
662 MachineBasicBlock *sinkMBB = new MachineBasicBlock(LLVM_BB);
664 sinkMBB->transferSuccessors(thisMBB);
666 MachineFunction *F = BB->getParent();
667 F->getBasicBlockList().insert(It, llscMBB);
668 F->getBasicBlockList().insert(It, sinkMBB);
670 BuildMI(thisMBB, TII->get(Alpha::BR)).addMBB(llscMBB);
672 unsigned reg_res = MI->getOperand(0).getReg(),
673 reg_ptr = MI->getOperand(1).getReg(),
674 reg_v2 = MI->getOperand(2).getReg(),
675 reg_store = F->getRegInfo().createVirtualRegister(&Alpha::GPRCRegClass);
677 BuildMI(llscMBB, TII->get(is32 ? Alpha::LDL_L : Alpha::LDQ_L),
678 reg_res).addImm(0).addReg(reg_ptr);
679 switch (MI->getOpcode()) {
683 = F->getRegInfo().createVirtualRegister(&Alpha::GPRCRegClass);
684 BuildMI(llscMBB, TII->get(Alpha::CMPEQ), reg_cmp)
685 .addReg(reg_v2).addReg(reg_res);
686 BuildMI(llscMBB, TII->get(Alpha::BEQ))
687 .addImm(0).addReg(reg_cmp).addMBB(sinkMBB);
688 BuildMI(llscMBB, TII->get(Alpha::BISr), reg_store)
689 .addReg(Alpha::R31).addReg(MI->getOperand(3).getReg());
694 BuildMI(llscMBB, TII->get(is32 ? Alpha::ADDLr : Alpha::ADDQr), reg_store)
695 .addReg(reg_res).addReg(reg_v2);
699 case Alpha::SWAP64: {
700 BuildMI(llscMBB, TII->get(Alpha::BISr), reg_store)
701 .addReg(reg_v2).addReg(reg_v2);
705 BuildMI(llscMBB, TII->get(is32 ? Alpha::STL_C : Alpha::STQ_C), reg_store)
706 .addReg(reg_store).addImm(0).addReg(reg_ptr);
707 BuildMI(llscMBB, TII->get(Alpha::BEQ))
708 .addImm(0).addReg(reg_store).addMBB(llscMBB);
709 BuildMI(llscMBB, TII->get(Alpha::BR)).addMBB(sinkMBB);
711 thisMBB->addSuccessor(llscMBB);
712 llscMBB->addSuccessor(llscMBB);
713 llscMBB->addSuccessor(sinkMBB);
714 delete MI; // The pseudo instruction is gone now.