1 //===-- AlphaISelLowering.h - Alpha DAG Lowering Interface ------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines the interfaces that Alpha uses to lower LLVM code into a
13 //===----------------------------------------------------------------------===//
15 #ifndef LLVM_TARGET_ALPHA_ALPHAISELLOWERING_H
16 #define LLVM_TARGET_ALPHA_ALPHAISELLOWERING_H
18 #include "llvm/ADT/VectorExtras.h"
19 #include "llvm/Target/TargetLowering.h"
20 #include "llvm/CodeGen/SelectionDAG.h"
27 // Start the numbering where the builting ops and target ops leave off.
28 FIRST_NUMBER = ISD::BUILTIN_OP_END,
29 //These corrospond to the identical Instruction
30 CVTQT_, CVTQS_, CVTTQ_,
32 /// GPRelHi/GPRelLo - These represent the high and low 16-bit
33 /// parts of a global address respectively.
36 /// RetLit - Literal Relocation of a Global
39 /// GlobalRetAddr - used to restore the return address
42 /// CALL - Normal call.
45 /// DIVCALL - used for special library calls for div and rem
48 /// return flag operand
51 /// CHAIN = COND_BRANCH CHAIN, OPC, (G|F)PRC, DESTBB [, INFLAG] - This
52 /// corresponds to the COND_BRANCH pseudo instruction.
53 /// *PRC is the input register to compare to zero,
54 /// OPC is the branch opcode to use (e.g. Alpha::BEQ),
55 /// DESTBB is the destination block to branch to, and INFLAG is
56 /// an optional input flag argument.
57 COND_BRANCH_I, COND_BRANCH_F
62 class AlphaTargetLowering : public TargetLowering {
64 explicit AlphaTargetLowering(TargetMachine &TM);
66 /// getSetCCResultType - Get the SETCC result ValueType
67 virtual MVT::SimpleValueType getSetCCResultType(EVT VT) const;
69 /// LowerOperation - Provide custom lowering hooks for some operations.
71 virtual SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const;
73 /// ReplaceNodeResults - Replace the results of node with an illegal result
74 /// type with new values built out of custom code.
76 virtual void ReplaceNodeResults(SDNode *N, SmallVectorImpl<SDValue>&Results,
77 SelectionDAG &DAG) const;
79 // Friendly names for dumps
80 const char *getTargetNodeName(unsigned Opcode) const;
82 SDValue LowerCallResult(SDValue Chain, SDValue InFlag,
83 CallingConv::ID CallConv, bool isVarArg,
84 const SmallVectorImpl<ISD::InputArg> &Ins,
85 DebugLoc dl, SelectionDAG &DAG,
86 SmallVectorImpl<SDValue> &InVals) const;
88 ConstraintType getConstraintType(const std::string &Constraint) const;
91 getRegClassForInlineAsmConstraint(const std::string &Constraint,
95 EmitInstrWithCustomInserter(MachineInstr *MI,
96 MachineBasicBlock *BB) const;
98 virtual bool isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const;
100 /// getFunctionAlignment - Return the Log2 alignment of this function.
101 virtual unsigned getFunctionAlignment(const Function *F) const;
103 /// isFPImmLegal - Returns true if the target can instruction select the
104 /// specified FP immediate natively. If false, the legalizer will
105 /// materialize the FP immediate as a load from a constant pool.
106 virtual bool isFPImmLegal(const APFloat &Imm, EVT VT) const;
109 // Helpers for custom lowering.
110 void LowerVAARG(SDNode *N, SDValue &Chain, SDValue &DataPtr,
111 SelectionDAG &DAG) const;
114 LowerFormalArguments(SDValue Chain,
115 CallingConv::ID CallConv, bool isVarArg,
116 const SmallVectorImpl<ISD::InputArg> &Ins,
117 DebugLoc dl, SelectionDAG &DAG,
118 SmallVectorImpl<SDValue> &InVals) const;
121 LowerCall(SDValue Chain, SDValue Callee,
122 CallingConv::ID CallConv, bool isVarArg, bool &isTailCall,
123 const SmallVectorImpl<ISD::OutputArg> &Outs,
124 const SmallVectorImpl<SDValue> &OutVals,
125 const SmallVectorImpl<ISD::InputArg> &Ins,
126 DebugLoc dl, SelectionDAG &DAG,
127 SmallVectorImpl<SDValue> &InVals) const;
130 LowerReturn(SDValue Chain,
131 CallingConv::ID CallConv, bool isVarArg,
132 const SmallVectorImpl<ISD::OutputArg> &Outs,
133 const SmallVectorImpl<SDValue> &OutVals,
134 DebugLoc dl, SelectionDAG &DAG) const;
138 #endif // LLVM_TARGET_ALPHA_ALPHAISELLOWERING_H