1 //===-- AlphaISelLowering.h - Alpha DAG Lowering Interface ------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines the interfaces that Alpha uses to lower LLVM code into a
13 //===----------------------------------------------------------------------===//
15 #ifndef LLVM_TARGET_ALPHA_ALPHAISELLOWERING_H
16 #define LLVM_TARGET_ALPHA_ALPHAISELLOWERING_H
18 #include "llvm/ADT/VectorExtras.h"
19 #include "llvm/Target/TargetLowering.h"
20 #include "llvm/CodeGen/SelectionDAG.h"
27 // Start the numbering where the builting ops and target ops leave off.
28 FIRST_NUMBER = ISD::BUILTIN_OP_END,
29 //These corrospond to the identical Instruction
30 CVTQT_, CVTQS_, CVTTQ_,
32 /// GPRelHi/GPRelLo - These represent the high and low 16-bit
33 /// parts of a global address respectively.
36 /// RetLit - Literal Relocation of a Global
39 /// GlobalRetAddr - used to restore the return address
42 /// CALL - Normal call.
45 /// DIVCALL - used for special library calls for div and rem
48 /// return flag operand
51 /// CHAIN = COND_BRANCH CHAIN, OPC, (G|F)PRC, DESTBB [, INFLAG] - This
52 /// corresponds to the COND_BRANCH pseudo instruction.
53 /// *PRC is the input register to compare to zero,
54 /// OPC is the branch opcode to use (e.g. Alpha::BEQ),
55 /// DESTBB is the destination block to branch to, and INFLAG is
56 /// an optional input flag argument.
57 COND_BRANCH_I, COND_BRANCH_F
62 class AlphaTargetLowering : public TargetLowering {
63 int VarArgsOffset; // What is the offset to the first vaarg
64 int VarArgsBase; // What is the base FrameIndex
66 explicit AlphaTargetLowering(TargetMachine &TM);
68 /// getSetCCResultType - Get the SETCC result ValueType
69 virtual MVT::SimpleValueType getSetCCResultType(EVT VT) const;
71 /// LowerOperation - Provide custom lowering hooks for some operations.
73 virtual SDValue LowerOperation(SDValue Op, SelectionDAG &DAG);
75 /// ReplaceNodeResults - Replace the results of node with an illegal result
76 /// type with new values built out of custom code.
78 virtual void ReplaceNodeResults(SDNode *N, SmallVectorImpl<SDValue>&Results,
81 // Friendly names for dumps
82 const char *getTargetNodeName(unsigned Opcode) const;
84 SDValue LowerCallResult(SDValue Chain, SDValue InFlag,
85 CallingConv::ID CallConv, bool isVarArg,
86 const SmallVectorImpl<ISD::InputArg> &Ins,
87 DebugLoc dl, SelectionDAG &DAG,
88 SmallVectorImpl<SDValue> &InVals);
90 ConstraintType getConstraintType(const std::string &Constraint) const;
93 getRegClassForInlineAsmConstraint(const std::string &Constraint,
96 MachineBasicBlock *EmitInstrWithCustomInserter(MachineInstr *MI,
97 MachineBasicBlock *BB,
98 DenseMap<MachineBasicBlock*, MachineBasicBlock*> *EM) const;
100 virtual bool isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const;
102 /// getFunctionAlignment - Return the Log2 alignment of this function.
103 virtual unsigned getFunctionAlignment(const Function *F) const;
105 /// isFPImmLegal - Returns true if the target can instruction select the
106 /// specified FP immediate natively. If false, the legalizer will
107 /// materialize the FP immediate as a load from a constant pool.
108 virtual bool isFPImmLegal(const APFloat &Imm, EVT VT) const;
111 // Helpers for custom lowering.
112 void LowerVAARG(SDNode *N, SDValue &Chain, SDValue &DataPtr,
116 LowerFormalArguments(SDValue Chain,
117 CallingConv::ID CallConv, bool isVarArg,
118 const SmallVectorImpl<ISD::InputArg> &Ins,
119 DebugLoc dl, SelectionDAG &DAG,
120 SmallVectorImpl<SDValue> &InVals);
123 LowerCall(SDValue Chain, SDValue Callee,
124 CallingConv::ID CallConv, bool isVarArg, bool isTailCall,
125 const SmallVectorImpl<ISD::OutputArg> &Outs,
126 const SmallVectorImpl<ISD::InputArg> &Ins,
127 DebugLoc dl, SelectionDAG &DAG,
128 SmallVectorImpl<SDValue> &InVals);
131 LowerReturn(SDValue Chain,
132 CallingConv::ID CallConv, bool isVarArg,
133 const SmallVectorImpl<ISD::OutputArg> &Outs,
134 DebugLoc dl, SelectionDAG &DAG);
138 #endif // LLVM_TARGET_ALPHA_ALPHAISELLOWERING_H