1 //===- AlphaISelPattern.cpp - A pattern matching inst selector for Alpha --===//
3 // The LLVM Compiler Infrastructure
5 // This file was developed by the LLVM research group and is distributed under
6 // the University of Illinois Open Source License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines a pattern matching instruction selector for Alpha.
12 //===----------------------------------------------------------------------===//
15 #include "AlphaRegisterInfo.h"
16 #include "AlphaTargetMachine.h"
17 #include "AlphaISelLowering.h"
18 #include "llvm/Constants.h" // FIXME: REMOVE
19 #include "llvm/Function.h"
20 #include "llvm/Module.h"
21 #include "llvm/CodeGen/MachineInstrBuilder.h"
22 #include "llvm/CodeGen/MachineConstantPool.h" // FIXME: REMOVE
23 #include "llvm/CodeGen/MachineFunction.h"
24 #include "llvm/CodeGen/MachineFrameInfo.h"
25 #include "llvm/CodeGen/SelectionDAG.h"
26 #include "llvm/CodeGen/SelectionDAGISel.h"
27 #include "llvm/CodeGen/SSARegMap.h"
28 #include "llvm/Target/TargetData.h"
29 #include "llvm/Target/TargetLowering.h"
30 #include "llvm/Support/MathExtras.h"
31 #include "llvm/ADT/Statistic.h"
32 #include "llvm/Support/Debug.h"
33 #include "llvm/Support/CommandLine.h"
39 cl::opt<bool> EnableAlphaIDIV("enable-alpha-intfpdiv",
40 cl::desc("Use the FP div instruction for integer div when possible"),
42 cl::opt<bool> EnableAlphaCount("enable-alpha-count",
43 cl::desc("Print estimates on live ins and outs"),
45 cl::opt<bool> EnableAlphaLSMark("enable-alpha-lsmark",
46 cl::desc("Emit symbols to correlate Mem ops to LLVM Values"),
52 //===--------------------------------------------------------------------===//
53 /// ISel - Alpha specific code to select Alpha machine instructions for
54 /// SelectionDAG operations.
55 //===--------------------------------------------------------------------===//
56 class AlphaISel : public SelectionDAGISel {
58 /// AlphaLowering - This object fully describes how to lower LLVM code to an
59 /// Alpha-specific SelectionDAG.
60 AlphaTargetLowering AlphaLowering;
62 SelectionDAG *ISelDAG; // Hack to support us having a dag->dag transform
63 // for sdiv and udiv until it is put into the future
66 /// ExprMap - As shared expressions are codegen'd, we keep track of which
67 /// vreg the value is produced in, so we only emit one copy of each compiled
69 static const unsigned notIn = (unsigned)(-1);
70 std::map<SDOperand, unsigned> ExprMap;
72 //CCInvMap sometimes (SetNE) we have the inverse CC code for free
73 std::map<SDOperand, unsigned> CCInvMap;
81 AlphaISel(TargetMachine &TM) : SelectionDAGISel(AlphaLowering),
85 virtual const char *getPassName() const {
86 return "Alpha Pattern Instruction Selection";
89 /// InstructionSelectBasicBlock - This callback is invoked by
90 /// SelectionDAGISel when it has created a SelectionDAG for us to codegen.
91 virtual void InstructionSelectBasicBlock(SelectionDAG &DAG) {
98 // Codegen the basic block.
100 max_depth = DAG.getRoot().getNodeDepth();
101 Select(DAG.getRoot());
106 std::cerr << "COUNT: "
107 << BB->getParent()->getFunction ()->getName() << " "
108 << BB->getNumber() << " "
111 << count_outs << "\n";
113 // Clear state used for selection.
118 unsigned SelectExpr(SDOperand N);
119 void Select(SDOperand N);
121 void SelectAddr(SDOperand N, unsigned& Reg, long& offset);
122 void SelectBranchCC(SDOperand N);
123 void MoveFP2Int(unsigned src, unsigned dst, bool isDouble);
124 void MoveInt2FP(unsigned src, unsigned dst, bool isDouble);
125 //returns whether the sense of the comparison was inverted
126 bool SelectFPSetCC(SDOperand N, unsigned dst);
128 // dag -> dag expanders for integer divide by constant
129 SDOperand BuildSDIVSequence(SDOperand N);
130 SDOperand BuildUDIVSequence(SDOperand N);
135 static bool isSIntImmediate(SDOperand N, int64_t& Imm) {
137 if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(N)) {
139 Imm = CN->getSignExtended();
147 // isSIntImmediateBounded - This method tests to see if a constant operand
148 // bounded s.t. low <= Imm <= high
149 // If so Imm will receive the 64 bit value.
150 static bool isSIntImmediateBounded(SDOperand N, int64_t& Imm,
151 int64_t low, int64_t high) {
152 if (isSIntImmediate(N, Imm) && Imm <= high && Imm >= low)
156 static bool isUIntImmediate(SDOperand N, uint64_t& Imm) {
158 if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(N)) {
160 Imm = (uint64_t)CN->getValue();
168 static bool isUIntImmediateBounded(SDOperand N, uint64_t& Imm,
169 uint64_t low, uint64_t high) {
170 if (isUIntImmediate(N, Imm) && Imm <= high && Imm >= low)
175 static void getValueInfo(const Value* v, int& type, int& fun, int& offset)
177 fun = type = offset = 0;
180 } else if (const GlobalValue* GV = dyn_cast<GlobalValue>(v)) {
182 const Module* M = GV->getParent();
183 for(Module::const_global_iterator ii = M->global_begin(); &*ii != GV; ++ii)
185 } else if (const Argument* Arg = dyn_cast<Argument>(v)) {
187 const Function* F = Arg->getParent();
188 const Module* M = F->getParent();
189 for(Module::const_iterator ii = M->begin(); &*ii != F; ++ii)
191 for(Function::const_arg_iterator ii = F->arg_begin(); &*ii != Arg; ++ii)
193 } else if (const Instruction* I = dyn_cast<Instruction>(v)) {
194 assert(dyn_cast<PointerType>(I->getType()));
196 const BasicBlock* bb = I->getParent();
197 const Function* F = bb->getParent();
198 const Module* M = F->getParent();
199 for(Module::const_iterator ii = M->begin(); &*ii != F; ++ii)
201 for(Function::const_iterator ii = F->begin(); &*ii != bb; ++ii)
202 offset += ii->size();
203 for(BasicBlock::const_iterator ii = bb->begin(); &*ii != I; ++ii)
205 } else if (const Constant* C = dyn_cast<Constant>(v)) {
206 //Don't know how to look these up yet
209 assert(0 && "Error in value marking");
211 //type = 4: register spilling
212 //type = 5: global address loading or constant loading
221 //Factorize a number using the list of constants
222 static bool factorize(int v[], int res[], int size, uint64_t c)
225 while (c != 1 && cont)
228 for(int i = 0; i < size; ++i)
242 //These describe LDAx
243 static const int IMM_LOW = -32768;
244 static const int IMM_HIGH = 32767;
245 static const int IMM_MULT = 65536;
247 static long getUpper16(long l)
249 long y = l / IMM_MULT;
250 if (l % IMM_MULT > IMM_HIGH)
255 static long getLower16(long l)
257 long h = getUpper16(l);
258 return l - h * IMM_MULT;
261 static unsigned GetRelVersion(unsigned opcode)
264 default: assert(0 && "unknown load or store"); return 0;
265 case Alpha::LDQ: return Alpha::LDQr;
266 case Alpha::LDS: return Alpha::LDSr;
267 case Alpha::LDT: return Alpha::LDTr;
268 case Alpha::LDL: return Alpha::LDLr;
269 case Alpha::LDBU: return Alpha::LDBUr;
270 case Alpha::LDWU: return Alpha::LDWUr;
271 case Alpha::STB: return Alpha::STBr;
272 case Alpha::STW: return Alpha::STWr;
273 case Alpha::STL: return Alpha::STLr;
274 case Alpha::STQ: return Alpha::STQr;
275 case Alpha::STS: return Alpha::STSr;
276 case Alpha::STT: return Alpha::STTr;
281 void AlphaISel::MoveFP2Int(unsigned src, unsigned dst, bool isDouble)
283 unsigned Opc = Alpha::WTF;
284 if (TLI.getTargetMachine().getSubtarget<AlphaSubtarget>().hasF2I()) {
285 Opc = isDouble ? Alpha::FTOIT : Alpha::FTOIS;
286 BuildMI(BB, Opc, 1, dst).addReg(src).addReg(Alpha::F31);
289 // Spill the integer to memory and reload it from there.
290 unsigned Size = MVT::getSizeInBits(MVT::f64)/8;
291 MachineFunction *F = BB->getParent();
292 int FrameIdx = F->getFrameInfo()->CreateStackObject(Size, 8);
294 if (EnableAlphaLSMark)
295 BuildMI(BB, Alpha::MEMLABEL, 4).addImm(4).addImm(0).addImm(0)
297 Opc = isDouble ? Alpha::STT : Alpha::STS;
298 BuildMI(BB, Opc, 3).addReg(src).addFrameIndex(FrameIdx).addReg(Alpha::F31);
300 if (EnableAlphaLSMark)
301 BuildMI(BB, Alpha::MEMLABEL, 4).addImm(4).addImm(0).addImm(0)
303 Opc = isDouble ? Alpha::LDQ : Alpha::LDL;
304 BuildMI(BB, Alpha::LDQ, 2, dst).addFrameIndex(FrameIdx).addReg(Alpha::F31);
308 void AlphaISel::MoveInt2FP(unsigned src, unsigned dst, bool isDouble)
310 unsigned Opc = Alpha::WTF;
311 if (TLI.getTargetMachine().getSubtarget<AlphaSubtarget>().hasF2I()) {
312 Opc = isDouble?Alpha::ITOFT:Alpha::ITOFS;
313 BuildMI(BB, Opc, 1, dst).addReg(src).addReg(Alpha::R31);
316 // Spill the integer to memory and reload it from there.
317 unsigned Size = MVT::getSizeInBits(MVT::f64)/8;
318 MachineFunction *F = BB->getParent();
319 int FrameIdx = F->getFrameInfo()->CreateStackObject(Size, 8);
321 if (EnableAlphaLSMark)
322 BuildMI(BB, Alpha::MEMLABEL, 4).addImm(4).addImm(0).addImm(0)
324 Opc = isDouble ? Alpha::STQ : Alpha::STL;
325 BuildMI(BB, Opc, 3).addReg(src).addFrameIndex(FrameIdx).addReg(Alpha::F31);
327 if (EnableAlphaLSMark)
328 BuildMI(BB, Alpha::MEMLABEL, 4).addImm(4).addImm(0).addImm(0)
330 Opc = isDouble ? Alpha::LDT : Alpha::LDS;
331 BuildMI(BB, Opc, 2, dst).addFrameIndex(FrameIdx).addReg(Alpha::F31);
335 bool AlphaISel::SelectFPSetCC(SDOperand N, unsigned dst)
337 SDNode *SetCC = N.Val;
338 unsigned Tmp1, Tmp2, Tmp3, Opc = Alpha::WTF;
339 ISD::CondCode CC = cast<CondCodeSDNode>(SetCC->getOperand(2))->get();
344 default: SetCC->dump(); assert(0 && "Unknown FP comparison!");
345 case ISD::SETEQ: Opc = Alpha::CMPTEQ; break;
346 case ISD::SETLT: Opc = Alpha::CMPTLT; break;
347 case ISD::SETLE: Opc = Alpha::CMPTLE; break;
348 case ISD::SETGT: Opc = Alpha::CMPTLT; rev = true; break;
349 case ISD::SETGE: Opc = Alpha::CMPTLE; rev = true; break;
350 case ISD::SETNE: Opc = Alpha::CMPTEQ; inv = true; break;
353 ConstantFPSDNode *CN;
354 if ((CN = dyn_cast<ConstantFPSDNode>(SetCC->getOperand(0)))
355 && (CN->isExactlyValue(+0.0) || CN->isExactlyValue(-0.0)))
358 Tmp1 = SelectExpr(N.getOperand(0));
360 if ((CN = dyn_cast<ConstantFPSDNode>(SetCC->getOperand(1)))
361 && (CN->isExactlyValue(+0.0) || CN->isExactlyValue(-0.0)))
364 Tmp2 = SelectExpr(N.getOperand(1));
366 //Can only compare doubles, and dag won't promote for me
367 if (SetCC->getOperand(0).getValueType() == MVT::f32)
368 assert(0 && "Setcc On float?\n");
369 if (SetCC->getOperand(1).getValueType() == MVT::f32)
370 assert (0 && "Setcc On float?\n");
372 if (rev) std::swap(Tmp1, Tmp2);
374 BuildMI(BB, Opc, 2, dst).addReg(Tmp1).addReg(Tmp2);
378 //Check to see if the load is a constant offset from a base register
379 void AlphaISel::SelectAddr(SDOperand N, unsigned& Reg, long& offset)
381 unsigned opcode = N.getOpcode();
382 if (opcode == ISD::ADD && N.getOperand(1).getOpcode() == ISD::Constant &&
383 cast<ConstantSDNode>(N.getOperand(1))->getValue() <= 32767)
385 Reg = SelectExpr(N.getOperand(0));
386 offset = cast<ConstantSDNode>(N.getOperand(1))->getValue();
394 void AlphaISel::SelectBranchCC(SDOperand N)
396 assert(N.getOpcode() == ISD::BRCOND && "Not a BranchCC???");
397 MachineBasicBlock *Dest =
398 cast<BasicBlockSDNode>(N.getOperand(2))->getBasicBlock();
399 unsigned Opc = Alpha::WTF;
401 Select(N.getOperand(0)); //chain
402 SDOperand CC = N.getOperand(1);
404 if (CC.getOpcode() == ISD::SETCC)
406 ISD::CondCode cCode= cast<CondCodeSDNode>(CC.getOperand(2))->get();
407 if (MVT::isInteger(CC.getOperand(0).getValueType())) {
408 //Dropping the CC is only useful if we are comparing to 0
409 bool RightZero = CC.getOperand(1).getOpcode() == ISD::Constant &&
410 cast<ConstantSDNode>(CC.getOperand(1))->getValue() == 0;
414 if(cCode == ISD::SETNE)
419 default: CC.Val->dump(); assert(0 && "Unknown integer comparison!");
420 case ISD::SETEQ: Opc = Alpha::BEQ; break;
421 case ISD::SETLT: Opc = Alpha::BLT; break;
422 case ISD::SETLE: Opc = Alpha::BLE; break;
423 case ISD::SETGT: Opc = Alpha::BGT; break;
424 case ISD::SETGE: Opc = Alpha::BGE; break;
425 case ISD::SETULT: assert(0 && "x (unsigned) < 0 is never true"); break;
426 case ISD::SETUGT: Opc = Alpha::BNE; break;
427 //Technically you could have this CC
428 case ISD::SETULE: Opc = Alpha::BEQ; break;
429 case ISD::SETUGE: assert(0 && "x (unsgined >= 0 is always true"); break;
430 case ISD::SETNE: Opc = Alpha::BNE; break;
432 unsigned Tmp1 = SelectExpr(CC.getOperand(0)); //Cond
433 BuildMI(BB, Opc, 2).addReg(Tmp1).addMBB(Dest);
436 unsigned Tmp1 = SelectExpr(CC);
438 BuildMI(BB, Alpha::BEQ, 2).addReg(CCInvMap[CC]).addMBB(Dest);
440 BuildMI(BB, Alpha::BNE, 2).addReg(Tmp1).addMBB(Dest);
444 //Any comparison between 2 values should be codegened as an folded
445 //branch, as moving CC to the integer register is very expensive
446 //for a cmp b: c = a - b;
451 bool invTest = false;
454 ConstantFPSDNode *CN;
455 if ((CN = dyn_cast<ConstantFPSDNode>(CC.getOperand(1)))
456 && (CN->isExactlyValue(+0.0) || CN->isExactlyValue(-0.0)))
457 Tmp3 = SelectExpr(CC.getOperand(0));
458 else if ((CN = dyn_cast<ConstantFPSDNode>(CC.getOperand(0)))
459 && (CN->isExactlyValue(+0.0) || CN->isExactlyValue(-0.0)))
461 Tmp3 = SelectExpr(CC.getOperand(1));
466 unsigned Tmp1 = SelectExpr(CC.getOperand(0));
467 unsigned Tmp2 = SelectExpr(CC.getOperand(1));
468 bool isD = CC.getOperand(0).getValueType() == MVT::f64;
469 Tmp3 = MakeReg(isD ? MVT::f64 : MVT::f32);
470 BuildMI(BB, isD ? Alpha::SUBT : Alpha::SUBS, 2, Tmp3)
471 .addReg(Tmp1).addReg(Tmp2);
475 default: CC.Val->dump(); assert(0 && "Unknown FP comparison!");
476 case ISD::SETEQ: Opc = invTest ? Alpha::FBNE : Alpha::FBEQ; break;
477 case ISD::SETLT: Opc = invTest ? Alpha::FBGT : Alpha::FBLT; break;
478 case ISD::SETLE: Opc = invTest ? Alpha::FBGE : Alpha::FBLE; break;
479 case ISD::SETGT: Opc = invTest ? Alpha::FBLT : Alpha::FBGT; break;
480 case ISD::SETGE: Opc = invTest ? Alpha::FBLE : Alpha::FBGE; break;
481 case ISD::SETNE: Opc = invTest ? Alpha::FBEQ : Alpha::FBNE; break;
483 BuildMI(BB, Opc, 2).addReg(Tmp3).addMBB(Dest);
486 abort(); //Should never be reached
488 //Giveup and do the stupid thing
489 unsigned Tmp1 = SelectExpr(CC);
490 BuildMI(BB, Alpha::BNE, 2).addReg(Tmp1).addMBB(Dest);
493 abort(); //Should never be reached
496 unsigned AlphaISel::SelectExpr(SDOperand N) {
498 unsigned Tmp1, Tmp2 = 0, Tmp3;
500 unsigned opcode = N.getOpcode();
504 SDNode *Node = N.Val;
505 MVT::ValueType DestType = N.getValueType();
506 bool isFP = DestType == MVT::f64 || DestType == MVT::f32;
508 unsigned &Reg = ExprMap[N];
511 switch(N.getOpcode()) {
513 Reg = Result = (N.getValueType() != MVT::Other) ?
514 MakeReg(N.getValueType()) : notIn;
516 case ISD::AssertSext:
517 case ISD::AssertZext:
518 return Reg = SelectExpr(N.getOperand(0));
521 // If this is a call instruction, make sure to prepare ALL of the result
522 // values as well as the chain.
523 if (Node->getNumValues() == 1)
524 Reg = Result = notIn; // Void call, just a chain.
526 Result = MakeReg(Node->getValueType(0));
527 ExprMap[N.getValue(0)] = Result;
528 for (unsigned i = 1, e = N.Val->getNumValues()-1; i != e; ++i)
529 ExprMap[N.getValue(i)] = MakeReg(Node->getValueType(i));
530 ExprMap[SDOperand(Node, Node->getNumValues()-1)] = notIn;
538 assert(0 && "Node not handled!\n");
540 case ISD::READCYCLECOUNTER:
541 Select(N.getOperand(0)); //Select chain
543 ExprMap[N.getValue(1)] = notIn; // Generate the token
545 Result = ExprMap[N.getValue(0)] = MakeReg(N.getValue(0).getValueType());
547 BuildMI(BB, Alpha::RPCC, 1, Result).addReg(Alpha::R31);
553 Opc = opcode == ISD::CTPOP ? Alpha::CTPOP :
554 (opcode == ISD::CTTZ ? Alpha::CTTZ : Alpha::CTLZ);
555 Tmp1 = SelectExpr(N.getOperand(0));
556 BuildMI(BB, Opc, 1, Result).addReg(Tmp1);
560 Tmp1 = SelectExpr(N.getOperand(0));
561 Tmp2 = SelectExpr(N.getOperand(1));
562 BuildMI(BB, Alpha::UMULH, 2, Result).addReg(Tmp1).addReg(Tmp2);
566 //MULHU - Ra<63>*Rb - Rb<63>*Ra
567 Tmp1 = SelectExpr(N.getOperand(0));
568 Tmp2 = SelectExpr(N.getOperand(1));
569 Tmp3 = MakeReg(MVT::i64);
570 BuildMI(BB, Alpha::UMULH, 2, Tmp3).addReg(Tmp1).addReg(Tmp2);
571 unsigned V1 = MakeReg(MVT::i64);
572 unsigned V2 = MakeReg(MVT::i64);
573 BuildMI(BB, Alpha::CMOVGE, 3, V1).addReg(Tmp2).addReg(Alpha::R31)
575 BuildMI(BB, Alpha::CMOVGE, 3, V2).addReg(Tmp1).addReg(Alpha::R31)
577 unsigned IRes = MakeReg(MVT::i64);
578 BuildMI(BB, Alpha::SUBQ, 2, IRes).addReg(Tmp3).addReg(V1);
579 BuildMI(BB, Alpha::SUBQ, 2, Result).addReg(IRes).addReg(V2);
583 Opc = isFP ? (DestType == MVT::f32 ? Alpha::IDEF_F32 : Alpha::IDEF_F64)
585 BuildMI(BB, Opc, 0, Result);
589 case ISD::DYNAMIC_STACKALLOC:
590 // Generate both result values.
592 ExprMap[N.getValue(1)] = notIn; // Generate the token
594 Result = ExprMap[N.getValue(0)] = MakeReg(N.getValue(0).getValueType());
596 // FIXME: We are currently ignoring the requested alignment for handling
597 // greater than the stack alignment. This will need to be revisited at some
598 // point. Align = N.getOperand(2);
600 if (!isa<ConstantSDNode>(N.getOperand(2)) ||
601 cast<ConstantSDNode>(N.getOperand(2))->getValue() != 0) {
602 std::cerr << "Cannot allocate stack object with greater alignment than"
603 << " the stack alignment yet!";
607 Select(N.getOperand(0));
608 if (isSIntImmediateBounded(N.getOperand(1), SImm, 0, 32767))
609 BuildMI(BB, Alpha::LDA, 2, Alpha::R30).addImm(-SImm).addReg(Alpha::R30);
611 Tmp1 = SelectExpr(N.getOperand(1));
612 // Subtract size from stack pointer, thereby allocating some space.
613 BuildMI(BB, Alpha::SUBQ, 2, Alpha::R30).addReg(Alpha::R30).addReg(Tmp1);
616 // Put a pointer to the space into the result register, by copying the stack
618 BuildMI(BB, Alpha::BIS, 2, Result).addReg(Alpha::R30).addReg(Alpha::R30);
621 case ISD::ConstantPool:
622 Tmp1 = BB->getParent()->getConstantPool()->
623 getConstantPoolIndex(cast<ConstantPoolSDNode>(N)->get());
624 AlphaLowering.restoreGP(BB);
625 Tmp2 = MakeReg(MVT::i64);
626 BuildMI(BB, Alpha::LDAHr, 2, Tmp2).addConstantPoolIndex(Tmp1)
628 BuildMI(BB, Alpha::LDAr, 2, Result).addConstantPoolIndex(Tmp1)
632 case ISD::FrameIndex:
633 BuildMI(BB, Alpha::LDA, 2, Result)
634 .addFrameIndex(cast<FrameIndexSDNode>(N)->getIndex())
643 // Make sure we generate both values.
645 ExprMap[N.getValue(1)] = notIn; // Generate the token
647 Result = ExprMap[N.getValue(0)] = MakeReg(N.getValue(0).getValueType());
649 SDOperand Chain = N.getOperand(0);
650 SDOperand Address = N.getOperand(1);
655 if (opcode == ISD::LOAD)
656 switch (Node->getValueType(0)) {
657 default: Node->dump(); assert(0 && "Bad load!");
658 case MVT::i64: Opc = Alpha::LDQ; break;
659 case MVT::f64: Opc = Alpha::LDT; break;
660 case MVT::f32: Opc = Alpha::LDS; break;
663 switch (cast<VTSDNode>(Node->getOperand(3))->getVT()) {
664 default: Node->dump(); assert(0 && "Bad sign extend!");
665 case MVT::i32: Opc = Alpha::LDL;
666 assert(opcode != ISD::ZEXTLOAD && "Not sext"); break;
667 case MVT::i16: Opc = Alpha::LDWU;
668 assert(opcode != ISD::SEXTLOAD && "Not zext"); break;
669 case MVT::i1: //FIXME: Treat i1 as i8 since there are problems otherwise
670 case MVT::i8: Opc = Alpha::LDBU;
671 assert(opcode != ISD::SEXTLOAD && "Not zext"); break;
675 if (EnableAlphaLSMark)
676 getValueInfo(dyn_cast<SrcValueSDNode>(N.getOperand(2))->getValue(),
679 GlobalAddressSDNode *GASD = dyn_cast<GlobalAddressSDNode>(Address);
680 if (GASD && !GASD->getGlobal()->isExternal()) {
681 Tmp1 = MakeReg(MVT::i64);
682 AlphaLowering.restoreGP(BB);
683 BuildMI(BB, Alpha::LDAHr, 2, Tmp1)
684 .addGlobalAddress(GASD->getGlobal()).addReg(Alpha::R29);
685 if (EnableAlphaLSMark)
686 BuildMI(BB, Alpha::MEMLABEL, 4).addImm(i).addImm(j).addImm(k)
688 BuildMI(BB, GetRelVersion(Opc), 2, Result)
689 .addGlobalAddress(GASD->getGlobal()).addReg(Tmp1);
690 } else if (ConstantPoolSDNode *CP =
691 dyn_cast<ConstantPoolSDNode>(Address)) {
692 unsigned CPIdx = BB->getParent()->getConstantPool()->
693 getConstantPoolIndex(CP->get());
694 AlphaLowering.restoreGP(BB);
696 Tmp1 = MakeReg(MVT::i64);
697 BuildMI(BB, Alpha::LDAHr, 2, Tmp1).addConstantPoolIndex(CPIdx)
699 if (EnableAlphaLSMark)
700 BuildMI(BB, Alpha::MEMLABEL, 4).addImm(i).addImm(j).addImm(k)
702 BuildMI(BB, GetRelVersion(Opc), 2, Result)
703 .addConstantPoolIndex(CPIdx).addReg(Tmp1);
704 } else if(Address.getOpcode() == ISD::FrameIndex) {
705 if (EnableAlphaLSMark)
706 BuildMI(BB, Alpha::MEMLABEL, 4).addImm(i).addImm(j).addImm(k)
708 BuildMI(BB, Opc, 2, Result)
709 .addFrameIndex(cast<FrameIndexSDNode>(Address)->getIndex())
713 SelectAddr(Address, Tmp1, offset);
714 if (EnableAlphaLSMark)
715 BuildMI(BB, Alpha::MEMLABEL, 4).addImm(i).addImm(j).addImm(k)
717 BuildMI(BB, Opc, 2, Result).addImm(offset).addReg(Tmp1);
722 case ISD::GlobalAddress:
723 AlphaLowering.restoreGP(BB);
726 Reg = Result = MakeReg(MVT::i64);
728 if (EnableAlphaLSMark)
729 BuildMI(BB, Alpha::MEMLABEL, 4).addImm(5).addImm(0).addImm(0)
732 BuildMI(BB, Alpha::LDQl, 2, Result)
733 .addGlobalAddress(cast<GlobalAddressSDNode>(N)->getGlobal())
737 case ISD::ExternalSymbol:
738 AlphaLowering.restoreGP(BB);
741 Reg = Result = MakeReg(MVT::i64);
743 if (EnableAlphaLSMark)
744 BuildMI(BB, Alpha::MEMLABEL, 4).addImm(5).addImm(0).addImm(0)
747 BuildMI(BB, Alpha::LDQl, 2, Result)
748 .addExternalSymbol(cast<ExternalSymbolSDNode>(N)->getSymbol())
755 Select(N.getOperand(0));
757 // The chain for this call is now lowered.
758 ExprMap[N.getValue(Node->getNumValues()-1)] = notIn;
761 std::vector<unsigned> argvregs;
762 //assert(Node->getNumOperands() < 8 && "Only 6 args supported");
763 for(int i = 2, e = Node->getNumOperands(); i < e; ++i)
764 argvregs.push_back(SelectExpr(N.getOperand(i)));
767 for(int i = 0, e = std::min(6, (int)argvregs.size()); i < e; ++i)
769 unsigned args_int[] = {Alpha::R16, Alpha::R17, Alpha::R18,
770 Alpha::R19, Alpha::R20, Alpha::R21};
771 unsigned args_float[] = {Alpha::F16, Alpha::F17, Alpha::F18,
772 Alpha::F19, Alpha::F20, Alpha::F21};
773 switch(N.getOperand(i+2).getValueType()) {
776 N.getOperand(i).Val->dump();
777 std::cerr << "Type for " << i << " is: " <<
778 N.getOperand(i+2).getValueType() << "\n";
779 assert(0 && "Unknown value type for call");
785 BuildMI(BB, Alpha::BIS, 2, args_int[i]).addReg(argvregs[i])
786 .addReg(argvregs[i]);
789 BuildMI(BB, Alpha::CPYSS, 2, args_float[i]).addReg(argvregs[i])
790 .addReg(argvregs[i]);
793 BuildMI(BB, Alpha::CPYST, 2, args_float[i]).addReg(argvregs[i])
794 .addReg(argvregs[i]);
799 for (int i = 6, e = argvregs.size(); i < e; ++i)
801 switch(N.getOperand(i+2).getValueType()) {
804 N.getOperand(i).Val->dump();
805 std::cerr << "Type for " << i << " is: " <<
806 N.getOperand(i+2).getValueType() << "\n";
807 assert(0 && "Unknown value type for call");
813 BuildMI(BB, Alpha::STQ, 3).addReg(argvregs[i]).addImm((i - 6) * 8)
817 BuildMI(BB, Alpha::STS, 3).addReg(argvregs[i]).addImm((i - 6) * 8)
821 BuildMI(BB, Alpha::STT, 3).addReg(argvregs[i]).addImm((i - 6) * 8)
826 //build the right kind of call
827 GlobalAddressSDNode *GASD = dyn_cast<GlobalAddressSDNode>(N.getOperand(1));
828 if (GASD && !GASD->getGlobal()->isExternal()) {
829 //use PC relative branch call
830 AlphaLowering.restoreGP(BB);
831 BuildMI(BB, Alpha::BSR, 1, Alpha::R26)
832 .addGlobalAddress(GASD->getGlobal(),true);
834 //no need to restore GP as we are doing an indirect call
835 Tmp1 = SelectExpr(N.getOperand(1));
836 BuildMI(BB, Alpha::BIS, 2, Alpha::R27).addReg(Tmp1).addReg(Tmp1);
837 BuildMI(BB, Alpha::JSR, 2, Alpha::R26).addReg(Alpha::R27).addImm(0);
840 //push the result into a virtual register
842 switch (Node->getValueType(0)) {
843 default: Node->dump(); assert(0 && "Unknown value type for call result!");
844 case MVT::Other: return notIn;
846 BuildMI(BB, Alpha::BIS, 2, Result).addReg(Alpha::R0).addReg(Alpha::R0);
849 BuildMI(BB, Alpha::CPYSS, 2, Result).addReg(Alpha::F0).addReg(Alpha::F0);
852 BuildMI(BB, Alpha::CPYST, 2, Result).addReg(Alpha::F0).addReg(Alpha::F0);
855 return Result+N.ResNo;
858 case ISD::SIGN_EXTEND_INREG:
860 //do SDIV opt for all levels of ints if not dividing by a constant
861 if (EnableAlphaIDIV && N.getOperand(0).getOpcode() == ISD::SDIV
862 && N.getOperand(0).getOperand(1).getOpcode() != ISD::Constant)
864 unsigned Tmp4 = MakeReg(MVT::f64);
865 unsigned Tmp5 = MakeReg(MVT::f64);
866 unsigned Tmp6 = MakeReg(MVT::f64);
867 unsigned Tmp7 = MakeReg(MVT::f64);
868 unsigned Tmp8 = MakeReg(MVT::f64);
869 unsigned Tmp9 = MakeReg(MVT::f64);
871 Tmp1 = SelectExpr(N.getOperand(0).getOperand(0));
872 Tmp2 = SelectExpr(N.getOperand(0).getOperand(1));
873 MoveInt2FP(Tmp1, Tmp4, true);
874 MoveInt2FP(Tmp2, Tmp5, true);
875 BuildMI(BB, Alpha::CVTQT, 1, Tmp6).addReg(Alpha::F31).addReg(Tmp4);
876 BuildMI(BB, Alpha::CVTQT, 1, Tmp7).addReg(Alpha::F31).addReg(Tmp5);
877 BuildMI(BB, Alpha::DIVT, 2, Tmp8).addReg(Tmp6).addReg(Tmp7);
878 BuildMI(BB, Alpha::CVTTQ, 1, Tmp9).addReg(Alpha::F31).addReg(Tmp8);
879 MoveFP2Int(Tmp9, Result, true);
883 //Alpha has instructions for a bunch of signed 32 bit stuff
884 if(cast<VTSDNode>(Node->getOperand(1))->getVT() == MVT::i32) {
885 switch (N.getOperand(0).getOpcode()) {
890 bool isAdd = N.getOperand(0).getOpcode() == ISD::ADD;
891 bool isMul = N.getOperand(0).getOpcode() == ISD::MUL;
892 //FIXME: first check for Scaled Adds and Subs!
893 if(!isMul && N.getOperand(0).getOperand(0).getOpcode() == ISD::SHL &&
894 isSIntImmediateBounded(N.getOperand(0).getOperand(0).getOperand(1), SImm, 2, 3))
896 bool use4 = SImm == 2;
897 Tmp1 = SelectExpr(N.getOperand(0).getOperand(0).getOperand(0));
898 Tmp2 = SelectExpr(N.getOperand(0).getOperand(1));
899 BuildMI(BB, isAdd?(use4?Alpha::S4ADDL:Alpha::S8ADDL):(use4?Alpha::S4SUBL:Alpha::S8SUBL),
900 2,Result).addReg(Tmp1).addReg(Tmp2);
902 else if(isAdd && N.getOperand(0).getOperand(1).getOpcode() == ISD::SHL &&
903 isSIntImmediateBounded(N.getOperand(0).getOperand(1).getOperand(1), SImm, 2, 3))
905 bool use4 = SImm == 2;
906 Tmp1 = SelectExpr(N.getOperand(0).getOperand(1).getOperand(0));
907 Tmp2 = SelectExpr(N.getOperand(0).getOperand(0));
908 BuildMI(BB, use4?Alpha::S4ADDL:Alpha::S8ADDL, 2,Result).addReg(Tmp1).addReg(Tmp2);
910 else if(isSIntImmediateBounded(N.getOperand(0).getOperand(1), SImm, 0, 255))
911 { //Normal imm add/sub
912 Opc = isAdd ? Alpha::ADDLi : (isMul ? Alpha::MULLi : Alpha::SUBLi);
913 Tmp1 = SelectExpr(N.getOperand(0).getOperand(0));
914 BuildMI(BB, Opc, 2, Result).addReg(Tmp1).addImm(SImm);
916 else if(!isMul && isSIntImmediate(N.getOperand(0).getOperand(1), SImm) &&
917 (((SImm << 32) >> 32) >= -255) && (((SImm << 32) >> 32) <= 0))
918 { //handle canonicalization
919 Opc = isAdd ? Alpha::SUBLi : Alpha::ADDLi;
920 Tmp1 = SelectExpr(N.getOperand(0).getOperand(0));
921 SImm = 0 - ((SImm << 32) >> 32);
922 assert(SImm >= 0 && SImm <= 255);
923 BuildMI(BB, Opc, 2, Result).addReg(Tmp1).addImm(SImm);
927 Opc = isAdd ? Alpha::ADDL : (isMul ? Alpha::MULL : Alpha::SUBL);
928 Tmp1 = SelectExpr(N.getOperand(0).getOperand(0));
929 Tmp2 = SelectExpr(N.getOperand(0).getOperand(1));
930 BuildMI(BB, Opc, 2, Result).addReg(Tmp1).addReg(Tmp2);
934 default: break; //Fall Though;
936 } //Every thing else fall though too, including unhandled opcodes above
937 Tmp1 = SelectExpr(N.getOperand(0));
938 //std::cerr << "SrcT: " << MVN->getExtraValueType() << "\n";
939 switch(cast<VTSDNode>(Node->getOperand(1))->getVT()) {
942 assert(0 && "Sign Extend InReg not there yet");
946 BuildMI(BB, Alpha::ADDLi, 2, Result).addReg(Tmp1).addImm(0);
950 BuildMI(BB, Alpha::SEXTW, 1, Result).addReg(Tmp1);
953 BuildMI(BB, Alpha::SEXTB, 1, Result).addReg(Tmp1);
956 Tmp2 = MakeReg(MVT::i64);
957 BuildMI(BB, Alpha::ANDi, 2, Tmp2).addReg(Tmp1).addImm(1);
958 BuildMI(BB, Alpha::SUBQ, 2, Result).addReg(Alpha::R31).addReg(Tmp2);
966 ISD::CondCode CC = cast<CondCodeSDNode>(N.getOperand(2))->get();
967 if (MVT::isInteger(N.getOperand(0).getValueType())) {
968 bool isConst = false;
971 //Tmp1 = SelectExpr(N.getOperand(0));
972 if(isSIntImmediate(N.getOperand(1), SImm) && SImm <= 255 && SImm >= 0)
976 default: Node->dump(); assert(0 && "Unknown integer comparison!");
978 Opc = isConst ? Alpha::CMPEQi : Alpha::CMPEQ; dir=1; break;
980 Opc = isConst ? Alpha::CMPLTi : Alpha::CMPLT; dir = 1; break;
982 Opc = isConst ? Alpha::CMPLEi : Alpha::CMPLE; dir = 1; break;
983 case ISD::SETGT: Opc = Alpha::CMPLT; dir = 2; break;
984 case ISD::SETGE: Opc = Alpha::CMPLE; dir = 2; break;
986 Opc = isConst ? Alpha::CMPULTi : Alpha::CMPULT; dir = 1; break;
987 case ISD::SETUGT: Opc = Alpha::CMPULT; dir = 2; break;
989 Opc = isConst ? Alpha::CMPULEi : Alpha::CMPULE; dir = 1; break;
990 case ISD::SETUGE: Opc = Alpha::CMPULE; dir = 2; break;
991 case ISD::SETNE: {//Handle this one special
992 //std::cerr << "Alpha does not have a setne.\n";
994 Tmp1 = SelectExpr(N.getOperand(0));
995 Tmp2 = SelectExpr(N.getOperand(1));
996 Tmp3 = MakeReg(MVT::i64);
997 BuildMI(BB, Alpha::CMPEQ, 2, Tmp3).addReg(Tmp1).addReg(Tmp2);
998 //Remeber we have the Inv for this CC
1001 BuildMI(BB, Alpha::CMPEQ, 2, Result).addReg(Alpha::R31).addReg(Tmp3);
1006 Tmp1 = SelectExpr(N.getOperand(0));
1008 BuildMI(BB, Opc, 2, Result).addReg(Tmp1).addImm(SImm);
1010 Tmp2 = SelectExpr(N.getOperand(1));
1011 BuildMI(BB, Opc, 2, Result).addReg(Tmp1).addReg(Tmp2);
1013 } else { //if (dir == 2) {
1014 Tmp1 = SelectExpr(N.getOperand(1));
1015 Tmp2 = SelectExpr(N.getOperand(0));
1016 BuildMI(BB, Opc, 2, Result).addReg(Tmp1).addReg(Tmp2);
1020 Tmp1 = MakeReg(MVT::f64);
1021 bool inv = SelectFPSetCC(N, Tmp1);
1023 //now arrange for Result (int) to have a 1 or 0
1024 Tmp2 = MakeReg(MVT::i64);
1025 BuildMI(BB, Alpha::ADDQi, 2, Tmp2).addReg(Alpha::R31).addImm(1);
1026 Opc = inv?Alpha::CMOVNEi_FP:Alpha::CMOVEQi_FP;
1027 BuildMI(BB, Opc, 3, Result).addReg(Tmp2).addImm(0).addReg(Tmp1);
1032 case ISD::CopyFromReg:
1036 // Make sure we generate both values.
1037 if (Result != notIn)
1038 ExprMap[N.getValue(1)] = notIn; // Generate the token
1040 Result = ExprMap[N.getValue(0)] = MakeReg(N.getValue(0).getValueType());
1042 SDOperand Chain = N.getOperand(0);
1045 unsigned r = cast<RegisterSDNode>(Node->getOperand(1))->getReg();
1046 //std::cerr << "CopyFromReg " << Result << " = " << r << "\n";
1047 switch(N.getValue(0).getValueType()) {
1049 BuildMI(BB, Alpha::CPYSS, 2, Result).addReg(r).addReg(r);
1052 BuildMI(BB, Alpha::CPYST, 2, Result).addReg(r).addReg(r);
1055 BuildMI(BB, Alpha::BIS, 2, Result).addReg(r).addReg(r);
1061 //Most of the plain arithmetic and logic share the same form, and the same
1062 //constant immediate test
1065 if (isSIntImmediate(N.getOperand(1), SImm) && SImm == -1) {
1066 Tmp1 = SelectExpr(N.getOperand(0));
1067 BuildMI(BB, Alpha::ORNOT, 2, Result).addReg(Alpha::R31).addReg(Tmp1);
1073 if (opcode == ISD::AND && isUIntImmediate(N.getOperand(1), UImm))
1075 unsigned int build = 0;
1076 for(int i = 0; i < 8; ++i)
1078 if ((UImm & 0x00FF) == 0x00FF)
1080 else if ((UImm & 0x00FF) != 0)
1081 { build = 0; break; }
1086 Tmp1 = SelectExpr(N.getOperand(0));
1087 BuildMI(BB, Alpha::ZAPNOTi, 2, Result).addReg(Tmp1).addImm(build);
1092 //Check operand(0) == Not
1093 if (N.getOperand(0).getOpcode() == ISD::XOR &&
1094 isSIntImmediate(N.getOperand(0).getOperand(1), SImm) && SImm == -1) {
1096 case ISD::AND: Opc = Alpha::BIC; break;
1097 case ISD::OR: Opc = Alpha::ORNOT; break;
1098 case ISD::XOR: Opc = Alpha::EQV; break;
1100 Tmp1 = SelectExpr(N.getOperand(1));
1101 Tmp2 = SelectExpr(N.getOperand(0).getOperand(0));
1102 BuildMI(BB, Opc, 2, Result).addReg(Tmp1).addReg(Tmp2);
1105 //Check operand(1) == Not
1106 if (N.getOperand(1).getOpcode() == ISD::XOR &&
1107 isSIntImmediate(N.getOperand(1).getOperand(1), SImm) && SImm == -1) {
1109 case ISD::AND: Opc = Alpha::BIC; break;
1110 case ISD::OR: Opc = Alpha::ORNOT; break;
1111 case ISD::XOR: Opc = Alpha::EQV; break;
1113 Tmp1 = SelectExpr(N.getOperand(0));
1114 Tmp2 = SelectExpr(N.getOperand(1).getOperand(0));
1115 BuildMI(BB, Opc, 2, Result).addReg(Tmp1).addReg(Tmp2);
1123 if(isSIntImmediateBounded(N.getOperand(1), SImm, 0, 255)) {
1125 case ISD::AND: Opc = Alpha::ANDi; break;
1126 case ISD::OR: Opc = Alpha::BISi; break;
1127 case ISD::XOR: Opc = Alpha::XORi; break;
1128 case ISD::SHL: Opc = Alpha::SLi; break;
1129 case ISD::SRL: Opc = Alpha::SRLi; break;
1130 case ISD::SRA: Opc = Alpha::SRAi; break;
1131 case ISD::MUL: Opc = Alpha::MULQi; break;
1133 Tmp1 = SelectExpr(N.getOperand(0));
1134 BuildMI(BB, Opc, 2, Result).addReg(Tmp1).addImm(SImm);
1137 case ISD::AND: Opc = Alpha::AND; break;
1138 case ISD::OR: Opc = Alpha::BIS; break;
1139 case ISD::XOR: Opc = Alpha::XOR; break;
1140 case ISD::SHL: Opc = Alpha::SL; break;
1141 case ISD::SRL: Opc = Alpha::SRL; break;
1142 case ISD::SRA: Opc = Alpha::SRA; break;
1143 case ISD::MUL: Opc = Alpha::MULQ; break;
1145 Tmp1 = SelectExpr(N.getOperand(0));
1146 Tmp2 = SelectExpr(N.getOperand(1));
1147 BuildMI(BB, Opc, 2, Result).addReg(Tmp1).addReg(Tmp2);
1154 bool isAdd = opcode == ISD::ADD;
1156 //first check for Scaled Adds and Subs!
1157 //Valid for add and sub
1158 if(N.getOperand(0).getOpcode() == ISD::SHL &&
1159 isSIntImmediate(N.getOperand(0).getOperand(1), SImm) &&
1160 (SImm == 2 || SImm == 3)) {
1161 bool use4 = SImm == 2;
1162 Tmp2 = SelectExpr(N.getOperand(0).getOperand(0));
1163 if (isSIntImmediateBounded(N.getOperand(1), SImm, 0, 255))
1164 BuildMI(BB, isAdd?(use4?Alpha::S4ADDQi:Alpha::S8ADDQi):(use4?Alpha::S4SUBQi:Alpha::S8SUBQi),
1165 2, Result).addReg(Tmp2).addImm(SImm);
1167 Tmp1 = SelectExpr(N.getOperand(1));
1168 BuildMI(BB, isAdd?(use4?Alpha::S4ADDQi:Alpha::S8ADDQi):(use4?Alpha::S4SUBQi:Alpha::S8SUBQi),
1169 2, Result).addReg(Tmp2).addReg(Tmp1);
1172 //Position prevents subs
1173 else if(N.getOperand(1).getOpcode() == ISD::SHL && isAdd &&
1174 isSIntImmediate(N.getOperand(1).getOperand(1), SImm) &&
1175 (SImm == 2 || SImm == 3)) {
1176 bool use4 = SImm == 2;
1177 Tmp2 = SelectExpr(N.getOperand(1).getOperand(0));
1178 if (isSIntImmediateBounded(N.getOperand(0), SImm, 0, 255))
1179 BuildMI(BB, use4?Alpha::S4ADDQi:Alpha::S8ADDQi, 2, Result).addReg(Tmp2).addImm(SImm);
1181 Tmp1 = SelectExpr(N.getOperand(0));
1182 BuildMI(BB, use4?Alpha::S4ADDQ:Alpha::S8ADDQ, 2, Result).addReg(Tmp2).addReg(Tmp1);
1186 else if(isSIntImmediateBounded(N.getOperand(1), SImm, 0, 255))
1187 { //Normal imm add/sub
1188 Opc = isAdd ? Alpha::ADDQi : Alpha::SUBQi;
1189 Tmp1 = SelectExpr(N.getOperand(0));
1190 BuildMI(BB, Opc, 2, Result).addReg(Tmp1).addImm(SImm);
1192 else if(isSIntImmediateBounded(N.getOperand(1), SImm, -255, 0))
1193 { //inverted imm add/sub
1194 Opc = isAdd ? Alpha::SUBQi : Alpha::ADDQi;
1195 Tmp1 = SelectExpr(N.getOperand(0));
1196 BuildMI(BB, Opc, 2, Result).addReg(Tmp1).addImm(-SImm);
1199 else if(isSIntImmediateBounded(N.getOperand(1), SImm, -32767, 32767))
1201 Tmp1 = SelectExpr(N.getOperand(0));
1204 BuildMI(BB, Alpha::LDA, 2, Result).addImm(SImm).addReg(Tmp1);
1206 //give up and do the operation
1209 Opc = isAdd ? Alpha::ADDQ : Alpha::SUBQ;
1210 Tmp1 = SelectExpr(N.getOperand(0));
1211 Tmp2 = SelectExpr(N.getOperand(1));
1212 BuildMI(BB, Opc, 2, Result).addReg(Tmp1).addReg(Tmp2);
1220 if (opcode == ISD::FADD)
1221 Opc = DestType == MVT::f64 ? Alpha::ADDT : Alpha::ADDS;
1222 else if (opcode == ISD::FSUB)
1223 Opc = DestType == MVT::f64 ? Alpha::SUBT : Alpha::SUBS;
1224 else if (opcode == ISD::FMUL)
1225 Opc = DestType == MVT::f64 ? Alpha::MULT : Alpha::MULS;
1227 Opc = DestType == MVT::f64 ? Alpha::DIVT : Alpha::DIVS;
1228 Tmp1 = SelectExpr(N.getOperand(0));
1229 Tmp2 = SelectExpr(N.getOperand(1));
1230 BuildMI(BB, Opc, 2, Result).addReg(Tmp1).addReg(Tmp2);
1235 //check if we can convert into a shift!
1236 if (isSIntImmediate(N.getOperand(1), SImm) &&
1237 SImm != 0 && isPowerOf2_64(llabs(SImm))) {
1238 unsigned k = Log2_64(llabs(SImm));
1239 Tmp1 = SelectExpr(N.getOperand(0));
1244 Tmp2 = MakeReg(MVT::i64);
1245 BuildMI(BB, Alpha::SRAi, 2, Tmp2).addReg(Tmp1).addImm(k - 1);
1247 Tmp3 = MakeReg(MVT::i64);
1248 BuildMI(BB, Alpha::SRLi, 2, Tmp3).addReg(Tmp2).addImm(64-k);
1249 unsigned Tmp4 = MakeReg(MVT::i64);
1250 BuildMI(BB, Alpha::ADDQ, 2, Tmp4).addReg(Tmp3).addReg(Tmp1);
1252 BuildMI(BB, Alpha::SRAi, 2, Result).addReg(Tmp4).addImm(k);
1255 unsigned Tmp5 = MakeReg(MVT::i64);
1256 BuildMI(BB, Alpha::SRAi, 2, Tmp5).addReg(Tmp4).addImm(k);
1257 BuildMI(BB, Alpha::SUBQ, 2, Result).addReg(Alpha::R31).addReg(Tmp5);
1267 const char* opstr = 0;
1269 case ISD::UREM: opstr = "__remqu"; break;
1270 case ISD::SREM: opstr = "__remq"; break;
1271 case ISD::UDIV: opstr = "__divqu"; break;
1272 case ISD::SDIV: opstr = "__divq"; break;
1274 Tmp1 = SelectExpr(N.getOperand(0));
1275 Tmp2 = SelectExpr(N.getOperand(1));
1277 ISelDAG->getExternalSymbol(opstr, AlphaLowering.getPointerTy());
1278 Tmp3 = SelectExpr(Addr);
1279 //set up regs explicitly (helps Reg alloc)
1280 BuildMI(BB, Alpha::BIS, 2, Alpha::R24).addReg(Tmp1).addReg(Tmp1);
1281 BuildMI(BB, Alpha::BIS, 2, Alpha::R25).addReg(Tmp2).addReg(Tmp2);
1282 BuildMI(BB, Alpha::BIS, 2, Alpha::R27).addReg(Tmp3).addReg(Tmp3);
1283 BuildMI(BB, Alpha::JSRs, 2, Alpha::R23).addReg(Alpha::R27).addImm(0);
1284 BuildMI(BB, Alpha::BIS, 2, Result).addReg(Alpha::R27).addReg(Alpha::R27);
1290 //Tmp1 = SelectExpr(N.getOperand(0)); //Cond
1291 unsigned TV = SelectExpr(N.getOperand(1)); //Use if TRUE
1292 unsigned FV = SelectExpr(N.getOperand(2)); //Use if FALSE
1294 SDOperand CC = N.getOperand(0);
1296 if (CC.getOpcode() == ISD::SETCC &&
1297 !MVT::isInteger(CC.getOperand(0).getValueType())) {
1298 //FP Setcc -> Select yay!
1301 //for a cmp b: c = a - b;
1306 bool invTest = false;
1308 bool isD = CC.getOperand(0).getValueType() == MVT::f64;
1309 ConstantFPSDNode *CN;
1310 if ((CN = dyn_cast<ConstantFPSDNode>(CC.getOperand(1)))
1311 && (CN->isExactlyValue(+0.0) || CN->isExactlyValue(-0.0)))
1312 Tmp3 = SelectExpr(CC.getOperand(0));
1313 else if ((CN = dyn_cast<ConstantFPSDNode>(CC.getOperand(0)))
1314 && (CN->isExactlyValue(+0.0) || CN->isExactlyValue(-0.0)))
1316 Tmp3 = SelectExpr(CC.getOperand(1));
1321 unsigned Tmp1 = SelectExpr(CC.getOperand(0));
1322 unsigned Tmp2 = SelectExpr(CC.getOperand(1));
1323 Tmp3 = MakeReg(isD ? MVT::f64 : MVT::f32);
1324 BuildMI(BB, isD ? Alpha::SUBT : Alpha::SUBS, 2, Tmp3)
1325 .addReg(Tmp1).addReg(Tmp2);
1329 switch (cast<CondCodeSDNode>(CC.getOperand(2))->get()) {
1330 default: CC.Val->dump(); assert(0 && "Unknown FP comparison!");
1331 case ISD::SETEQ: Opc = invTest ? Alpha::FCMOVNET : Alpha::FCMOVEQT; break;
1332 case ISD::SETLT: Opc = invTest ? Alpha::FCMOVGTT : Alpha::FCMOVLTT; break;
1333 case ISD::SETLE: Opc = invTest ? Alpha::FCMOVGET : Alpha::FCMOVLET; break;
1334 case ISD::SETGT: Opc = invTest ? Alpha::FCMOVLTT : Alpha::FCMOVGTT; break;
1335 case ISD::SETGE: Opc = invTest ? Alpha::FCMOVLET : Alpha::FCMOVGET; break;
1336 case ISD::SETNE: Opc = invTest ? Alpha::FCMOVEQT : Alpha::FCMOVNET; break;
1339 switch (cast<CondCodeSDNode>(CC.getOperand(2))->get()) {
1340 default: CC.Val->dump(); assert(0 && "Unknown FP comparison!");
1341 case ISD::SETEQ: Opc = invTest ? Alpha::FCMOVNES : Alpha::FCMOVEQS; break;
1342 case ISD::SETLT: Opc = invTest ? Alpha::FCMOVGTS : Alpha::FCMOVLTS; break;
1343 case ISD::SETLE: Opc = invTest ? Alpha::FCMOVGES : Alpha::FCMOVLES; break;
1344 case ISD::SETGT: Opc = invTest ? Alpha::FCMOVLTS : Alpha::FCMOVGTS; break;
1345 case ISD::SETGE: Opc = invTest ? Alpha::FCMOVLES : Alpha::FCMOVGES; break;
1346 case ISD::SETNE: Opc = invTest ? Alpha::FCMOVEQS : Alpha::FCMOVNES; break;
1348 BuildMI(BB, Opc, 3, Result).addReg(FV).addReg(TV).addReg(Tmp3);
1353 Tmp1 = SelectExpr(N.getOperand(0)); //Cond
1354 BuildMI(BB, Alpha::FCMOVEQ_INT, 3, Result).addReg(TV).addReg(FV)
1356 // // Spill the cond to memory and reload it from there.
1357 // unsigned Tmp4 = MakeReg(MVT::f64);
1358 // MoveIntFP(Tmp1, Tmp4, true);
1359 // //now ideally, we don't have to do anything to the flag...
1360 // // Get the condition into the zero flag.
1361 // BuildMI(BB, Alpha::FCMOVEQ, 3, Result).addReg(TV).addReg(FV).addReg(Tmp4);
1365 //FIXME: look at parent to decide if intCC can be folded, or if setCC(FP)
1366 //and can save stack use
1367 //Tmp1 = SelectExpr(N.getOperand(0)); //Cond
1368 //Tmp2 = SelectExpr(N.getOperand(1)); //Use if TRUE
1369 //Tmp3 = SelectExpr(N.getOperand(2)); //Use if FALSE
1370 // Get the condition into the zero flag.
1371 //BuildMI(BB, Alpha::CMOVEQ, 2, Result).addReg(Tmp2).addReg(Tmp3).addReg(Tmp1);
1373 SDOperand CC = N.getOperand(0);
1375 if (CC.getOpcode() == ISD::SETCC &&
1376 !MVT::isInteger(CC.getOperand(0).getValueType()))
1377 { //FP Setcc -> Int Select
1378 Tmp1 = MakeReg(MVT::f64);
1379 Tmp2 = SelectExpr(N.getOperand(1)); //Use if TRUE
1380 Tmp3 = SelectExpr(N.getOperand(2)); //Use if FALSE
1381 bool inv = SelectFPSetCC(CC, Tmp1);
1382 BuildMI(BB, inv?Alpha::CMOVNE_FP:Alpha::CMOVEQ_FP, 2, Result)
1383 .addReg(Tmp2).addReg(Tmp3).addReg(Tmp1);
1386 if (CC.getOpcode() == ISD::SETCC) {
1387 //Int SetCC -> Select
1388 //Dropping the CC is only useful if we are comparing to 0
1389 if(isSIntImmediateBounded(CC.getOperand(1), SImm, 0, 0)) {
1390 //figure out a few things
1391 bool useImm = isSIntImmediateBounded(N.getOperand(2), SImm, 0, 255);
1394 ISD::CondCode cCode= cast<CondCodeSDNode>(CC.getOperand(2))->get();
1395 if (useImm) //Invert sense to get Imm field right
1396 cCode = ISD::getSetCCInverse(cCode, true);
1400 default: CC.Val->dump(); assert(0 && "Unknown integer comparison!");
1401 case ISD::SETEQ: Opc = useImm?Alpha::CMOVEQi:Alpha::CMOVEQ; break;
1402 case ISD::SETLT: Opc = useImm?Alpha::CMOVLTi:Alpha::CMOVLT; break;
1403 case ISD::SETLE: Opc = useImm?Alpha::CMOVLEi:Alpha::CMOVLE; break;
1404 case ISD::SETGT: Opc = useImm?Alpha::CMOVGTi:Alpha::CMOVGT; break;
1405 case ISD::SETGE: Opc = useImm?Alpha::CMOVGEi:Alpha::CMOVGE; break;
1406 case ISD::SETULT: assert(0 && "unsigned < 0 is never true"); break;
1407 case ISD::SETUGT: Opc = useImm?Alpha::CMOVNEi:Alpha::CMOVNE; break;
1408 //Technically you could have this CC
1409 case ISD::SETULE: Opc = useImm?Alpha::CMOVEQi:Alpha::CMOVEQ; break;
1410 case ISD::SETUGE: assert(0 && "unsgined >= 0 is always true"); break;
1411 case ISD::SETNE: Opc = useImm?Alpha::CMOVNEi:Alpha::CMOVNE; break;
1413 Tmp1 = SelectExpr(CC.getOperand(0)); //Cond
1416 Tmp3 = SelectExpr(N.getOperand(1)); //Use if FALSE
1417 BuildMI(BB, Opc, 2, Result).addReg(Tmp3).addImm(SImm).addReg(Tmp1);
1419 Tmp2 = SelectExpr(N.getOperand(1)); //Use if TRUE
1420 Tmp3 = SelectExpr(N.getOperand(2)); //Use if FALSE
1421 BuildMI(BB, Opc, 2, Result).addReg(Tmp3).addReg(Tmp2).addReg(Tmp1);
1425 //Otherwise, fall though
1427 Tmp1 = SelectExpr(N.getOperand(0)); //Cond
1428 Tmp2 = SelectExpr(N.getOperand(1)); //Use if TRUE
1429 Tmp3 = SelectExpr(N.getOperand(2)); //Use if FALSE
1430 BuildMI(BB, Alpha::CMOVEQ, 2, Result).addReg(Tmp2).addReg(Tmp3)
1438 int64_t val = (int64_t)cast<ConstantSDNode>(N)->getValue();
1439 int zero_extend_top = 0;
1440 if (val > 0 && (val & 0xFFFFFFFF00000000ULL) == 0 &&
1441 ((int32_t)val < 0)) {
1442 //try a small load and zero extend
1444 zero_extend_top = 15;
1447 if (val <= IMM_HIGH && val >= IMM_LOW) {
1448 if(!zero_extend_top)
1449 BuildMI(BB, Alpha::LDA, 2, Result).addImm(val).addReg(Alpha::R31);
1451 Tmp1 = MakeReg(MVT::i64);
1452 BuildMI(BB, Alpha::LDA, 2, Tmp1).addImm(val).addReg(Alpha::R31);
1453 BuildMI(BB, Alpha::ZAPNOT, 2, Result).addReg(Tmp1).addImm(zero_extend_top);
1456 else if (val <= (int64_t)IMM_HIGH +(int64_t)IMM_HIGH* (int64_t)IMM_MULT &&
1457 val >= (int64_t)IMM_LOW + (int64_t)IMM_LOW * (int64_t)IMM_MULT) {
1458 Tmp1 = MakeReg(MVT::i64);
1459 BuildMI(BB, Alpha::LDAH, 2, Tmp1).addImm(getUpper16(val))
1460 .addReg(Alpha::R31);
1461 if (!zero_extend_top)
1462 BuildMI(BB, Alpha::LDA, 2, Result).addImm(getLower16(val)).addReg(Tmp1);
1464 Tmp3 = MakeReg(MVT::i64);
1465 BuildMI(BB, Alpha::LDA, 2, Tmp3).addImm(getLower16(val)).addReg(Tmp1);
1466 BuildMI(BB, Alpha::ZAPNOT, 2, Result).addReg(Tmp3).addImm(zero_extend_top);
1470 //re-get the val since we are going to mem anyway
1471 val = (int64_t)cast<ConstantSDNode>(N)->getValue();
1472 MachineConstantPool *CP = BB->getParent()->getConstantPool();
1474 ConstantUInt::get(Type::getPrimitiveType(Type::ULongTyID) , val);
1475 unsigned CPI = CP->getConstantPoolIndex(C);
1476 AlphaLowering.restoreGP(BB);
1478 Tmp1 = MakeReg(MVT::i64);
1479 BuildMI(BB, Alpha::LDAHr, 2, Tmp1).addConstantPoolIndex(CPI)
1480 .addReg(Alpha::R29);
1481 if (EnableAlphaLSMark)
1482 BuildMI(BB, Alpha::MEMLABEL, 4).addImm(5).addImm(0).addImm(0)
1484 BuildMI(BB, Alpha::LDQr, 2, Result).addConstantPoolIndex(CPI)
1490 if(ISD::FABS == N.getOperand(0).getOpcode())
1492 Tmp1 = SelectExpr(N.getOperand(0).getOperand(0));
1493 BuildMI(BB, DestType == MVT::f64 ? Alpha::CPYSNT : Alpha::CPYSNS,
1494 2, Result).addReg(Alpha::F31).addReg(Tmp1);
1496 Tmp1 = SelectExpr(N.getOperand(0));
1497 BuildMI(BB, DestType == MVT::f64 ? Alpha::CPYSNT : Alpha::CPYSNS
1498 , 2, Result).addReg(Tmp1).addReg(Tmp1);
1503 Tmp1 = SelectExpr(N.getOperand(0));
1504 BuildMI(BB, DestType == MVT::f64 ? Alpha::CPYST : Alpha::CPYSS, 2, Result)
1505 .addReg(Alpha::F31).addReg(Tmp1);
1509 assert (DestType == MVT::f32 &&
1510 N.getOperand(0).getValueType() == MVT::f64 &&
1511 "only f64 to f32 conversion supported here");
1512 Tmp1 = SelectExpr(N.getOperand(0));
1513 BuildMI(BB, Alpha::CVTTS, 1, Result).addReg(Tmp1);
1516 case ISD::FP_EXTEND:
1517 assert (DestType == MVT::f64 &&
1518 N.getOperand(0).getValueType() == MVT::f32 &&
1519 "only f32 to f64 conversion supported here");
1520 Tmp1 = SelectExpr(N.getOperand(0));
1521 BuildMI(BB, Alpha::CVTST, 1, Result).addReg(Tmp1);
1524 case ISD::ConstantFP:
1525 if (ConstantFPSDNode *CN = dyn_cast<ConstantFPSDNode>(N)) {
1526 if (CN->isExactlyValue(+0.0)) {
1527 BuildMI(BB, DestType == MVT::f64 ? Alpha::CPYST : Alpha::CPYSS
1528 , 2, Result).addReg(Alpha::F31)
1529 .addReg(Alpha::F31);
1530 } else if ( CN->isExactlyValue(-0.0)) {
1531 BuildMI(BB, DestType == MVT::f64 ? Alpha::CPYSNT : Alpha::CPYSNS,
1532 2, Result).addReg(Alpha::F31)
1533 .addReg(Alpha::F31);
1540 case AlphaISD::CVTQT_:
1541 Tmp1 = SelectExpr(N.getOperand(0));
1542 BuildMI(BB, Alpha::CVTQT, 1, Result).addReg(Tmp1);
1545 case AlphaISD::CVTQS_:
1546 Tmp1 = SelectExpr(N.getOperand(0));
1547 BuildMI(BB, Alpha::CVTQS, 1, Result).addReg(Tmp1);
1550 case AlphaISD::CVTTQ_:
1551 Tmp1 = SelectExpr(N.getOperand(0));
1552 BuildMI(BB, Alpha::CVTTQ, 1, Result).addReg(Tmp1);
1555 case AlphaISD::ITOFT_:
1556 Tmp1 = SelectExpr(N.getOperand(0));
1557 BuildMI(BB, Alpha::ITOFT, 1, Result).addReg(Tmp1);
1560 case AlphaISD::FTOIT_:
1561 Tmp1 = SelectExpr(N.getOperand(0));
1562 BuildMI(BB, Alpha::FTOIT, 1, Result).addReg(Tmp1);
1565 case ISD::AssertSext:
1566 case ISD::AssertZext:
1567 return SelectExpr(N.getOperand(0));
1574 void AlphaISel::Select(SDOperand N) {
1575 unsigned Tmp1, Tmp2, Opc = Alpha::WTF;
1576 unsigned opcode = N.getOpcode();
1578 if (!ExprMap.insert(std::make_pair(N, notIn)).second)
1579 return; // Already selected.
1581 SDNode *Node = N.Val;
1586 Node->dump(); std::cerr << "\n";
1587 assert(0 && "Node not handled yet!");
1595 MachineBasicBlock *Dest =
1596 cast<BasicBlockSDNode>(N.getOperand(1))->getBasicBlock();
1598 Select(N.getOperand(0));
1599 BuildMI(BB, Alpha::BR, 1, Alpha::R31).addMBB(Dest);
1603 case ISD::ImplicitDef:
1605 Select(N.getOperand(0));
1606 switch(N.getValueType()) {
1607 case MVT::f32: Opc = Alpha::IDEF_F32; break;
1608 case MVT::f64: Opc = Alpha::IDEF_F64; break;
1609 case MVT::i64: Opc = Alpha::IDEF_I; break;
1610 default: assert(0 && "should have been legalized");
1613 cast<RegisterSDNode>(N.getOperand(1))->getReg());
1616 case ISD::EntryToken: return; // Noop
1618 case ISD::TokenFactor:
1619 for (unsigned i = 0, e = Node->getNumOperands(); i != e; ++i)
1620 Select(Node->getOperand(i));
1622 //N.Val->dump(); std::cerr << "\n";
1623 //assert(0 && "Node not handled yet!");
1627 case ISD::CopyToReg:
1629 Select(N.getOperand(0));
1630 Tmp1 = SelectExpr(N.getOperand(2));
1631 Tmp2 = cast<RegisterSDNode>(N.getOperand(1))->getReg();
1634 switch(N.getOperand(2).getValueType()) {
1636 BuildMI(BB, Alpha::CPYST, 2, Tmp2).addReg(Tmp1).addReg(Tmp1);
1639 BuildMI(BB, Alpha::CPYSS, 2, Tmp2).addReg(Tmp1).addReg(Tmp1);
1642 BuildMI(BB, Alpha::BIS, 2, Tmp2).addReg(Tmp1).addReg(Tmp1);
1650 switch (N.getNumOperands()) {
1652 std::cerr << N.getNumOperands() << "\n";
1653 for (unsigned i = 0; i < N.getNumOperands(); ++i)
1654 std::cerr << N.getOperand(i).getValueType() << "\n";
1656 assert(0 && "Unknown return instruction!");
1658 Select(N.getOperand(0));
1659 Tmp1 = SelectExpr(N.getOperand(1));
1660 switch (N.getOperand(1).getValueType()) {
1661 default: Node->dump();
1662 assert(0 && "All other types should have been promoted!!");
1664 BuildMI(BB, Alpha::CPYST, 2, Alpha::F0).addReg(Tmp1).addReg(Tmp1);
1667 BuildMI(BB, Alpha::CPYSS, 2, Alpha::F0).addReg(Tmp1).addReg(Tmp1);
1671 BuildMI(BB, Alpha::BIS, 2, Alpha::R0).addReg(Tmp1).addReg(Tmp1);
1676 Select(N.getOperand(0));
1679 // Just emit a 'ret' instruction
1680 AlphaLowering.restoreRA(BB);
1681 BuildMI(BB, Alpha::RET, 2, Alpha::R31).addReg(Alpha::R26).addImm(1);
1684 case ISD::TRUNCSTORE:
1687 SDOperand Chain = N.getOperand(0);
1688 SDOperand Value = N.getOperand(1);
1689 SDOperand Address = N.getOperand(2);
1692 Tmp1 = SelectExpr(Value); //value
1694 if (opcode == ISD::STORE) {
1695 switch(Value.getValueType()) {
1696 default: assert(0 && "unknown Type in store");
1697 case MVT::i64: Opc = Alpha::STQ; break;
1698 case MVT::f64: Opc = Alpha::STT; break;
1699 case MVT::f32: Opc = Alpha::STS; break;
1701 } else { //ISD::TRUNCSTORE
1702 switch(cast<VTSDNode>(Node->getOperand(4))->getVT()) {
1703 default: assert(0 && "unknown Type in store");
1704 case MVT::i8: Opc = Alpha::STB; break;
1705 case MVT::i16: Opc = Alpha::STW; break;
1706 case MVT::i32: Opc = Alpha::STL; break;
1711 if (EnableAlphaLSMark)
1712 getValueInfo(cast<SrcValueSDNode>(N.getOperand(3))->getValue(),
1715 GlobalAddressSDNode *GASD = dyn_cast<GlobalAddressSDNode>(Address);
1716 if (GASD && !GASD->getGlobal()->isExternal()) {
1717 Tmp2 = MakeReg(MVT::i64);
1718 AlphaLowering.restoreGP(BB);
1719 BuildMI(BB, Alpha::LDAHr, 2, Tmp2)
1720 .addGlobalAddress(GASD->getGlobal()).addReg(Alpha::R29);
1721 if (EnableAlphaLSMark)
1722 BuildMI(BB, Alpha::MEMLABEL, 4).addImm(i).addImm(j).addImm(k)
1724 BuildMI(BB, GetRelVersion(Opc), 3).addReg(Tmp1)
1725 .addGlobalAddress(GASD->getGlobal()).addReg(Tmp2);
1726 } else if(Address.getOpcode() == ISD::FrameIndex) {
1727 if (EnableAlphaLSMark)
1728 BuildMI(BB, Alpha::MEMLABEL, 4).addImm(i).addImm(j).addImm(k)
1730 BuildMI(BB, Opc, 3).addReg(Tmp1)
1731 .addFrameIndex(cast<FrameIndexSDNode>(Address)->getIndex())
1732 .addReg(Alpha::F31);
1735 SelectAddr(Address, Tmp2, offset);
1736 if (EnableAlphaLSMark)
1737 BuildMI(BB, Alpha::MEMLABEL, 4).addImm(i).addImm(j).addImm(k)
1739 BuildMI(BB, Opc, 3).addReg(Tmp1).addImm(offset).addReg(Tmp2);
1748 case ISD::CopyFromReg:
1751 case ISD::READCYCLECOUNTER:
1752 case ISD::DYNAMIC_STACKALLOC:
1757 case ISD::CALLSEQ_START:
1758 case ISD::CALLSEQ_END:
1759 Select(N.getOperand(0));
1760 Tmp1 = cast<ConstantSDNode>(N.getOperand(1))->getValue();
1762 Opc = N.getOpcode() == ISD::CALLSEQ_START ? Alpha::ADJUSTSTACKDOWN :
1763 Alpha::ADJUSTSTACKUP;
1764 BuildMI(BB, Opc, 1).addImm(Tmp1);
1768 Select(N.getOperand(0)); //Chain
1769 BuildMI(BB, Alpha::PCLABEL, 2)
1770 .addImm( cast<ConstantSDNode>(N.getOperand(1))->getValue());
1773 assert(0 && "Should not be reached!");
1777 /// createAlphaPatternInstructionSelector - This pass converts an LLVM function
1778 /// into a machine code representation using pattern matching and a machine
1779 /// description file.
1781 FunctionPass *llvm::createAlphaPatternInstructionSelector(TargetMachine &TM) {
1782 return new AlphaISel(TM);