1 //===- AlphaISelPattern.cpp - A pattern matching inst selector for Alpha --===//
3 // The LLVM Compiler Infrastructure
5 // This file was developed by the LLVM research group and is distributed under
6 // the University of Illinois Open Source License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines a pattern matching instruction selector for Alpha.
12 //===----------------------------------------------------------------------===//
15 #include "AlphaRegisterInfo.h"
16 #include "llvm/Constants.h" // FIXME: REMOVE
17 #include "llvm/Function.h"
18 #include "llvm/CodeGen/MachineInstrBuilder.h"
19 #include "llvm/CodeGen/MachineConstantPool.h" // FIXME: REMOVE
20 #include "llvm/CodeGen/MachineFunction.h"
21 #include "llvm/CodeGen/MachineFrameInfo.h"
22 #include "llvm/CodeGen/SelectionDAG.h"
23 #include "llvm/CodeGen/SelectionDAGISel.h"
24 #include "llvm/CodeGen/SSARegMap.h"
25 #include "llvm/Target/TargetData.h"
26 #include "llvm/Target/TargetLowering.h"
27 #include "llvm/Support/MathExtras.h"
28 #include "llvm/ADT/Statistic.h"
29 #include "llvm/Support/Debug.h"
34 //===----------------------------------------------------------------------===//
35 // AlphaTargetLowering - Alpha Implementation of the TargetLowering interface
37 class AlphaTargetLowering : public TargetLowering {
38 int VarArgsFrameIndex; // FrameIndex for start of varargs area.
39 unsigned GP; //GOT vreg
41 AlphaTargetLowering(TargetMachine &TM) : TargetLowering(TM) {
42 // Set up the TargetLowering object.
43 //I am having problems with shr n ubyte 1
44 setShiftAmountType(MVT::i64);
45 setSetCCResultType(MVT::i64);
47 addRegisterClass(MVT::i64, Alpha::GPRCRegisterClass);
48 addRegisterClass(MVT::f64, Alpha::FPRCRegisterClass);
49 addRegisterClass(MVT::f32, Alpha::FPRCRegisterClass);
51 setOperationAction(ISD::EXTLOAD , MVT::i1 , Promote);
52 setOperationAction(ISD::EXTLOAD , MVT::f32 , Promote);
54 setOperationAction(ISD::ZEXTLOAD , MVT::i1 , Expand);
55 setOperationAction(ISD::ZEXTLOAD , MVT::i32 , Expand);
57 setOperationAction(ISD::SEXTLOAD , MVT::i1 , Expand);
58 setOperationAction(ISD::SEXTLOAD , MVT::i8 , Expand);
59 setOperationAction(ISD::SEXTLOAD , MVT::i16 , Expand);
61 setOperationAction(ISD::SREM , MVT::f32 , Expand);
62 setOperationAction(ISD::SREM , MVT::f64 , Expand);
64 setOperationAction(ISD::MEMMOVE , MVT::Other, Expand);
65 setOperationAction(ISD::MEMSET , MVT::Other, Expand);
66 setOperationAction(ISD::MEMCPY , MVT::Other, Expand);
69 setOperationAction(ISD::SETCC , MVT::f32, Promote);
71 computeRegisterProperties();
73 addLegalFPImmediate(+0.0); //F31
74 addLegalFPImmediate(-0.0); //-F31
77 /// LowerArguments - This hook must be implemented to indicate how we should
78 /// lower the arguments for the specified function, into the specified DAG.
79 virtual std::vector<SDOperand>
80 LowerArguments(Function &F, SelectionDAG &DAG);
82 /// LowerCallTo - This hook lowers an abstract call to a function into an
84 virtual std::pair<SDOperand, SDOperand>
85 LowerCallTo(SDOperand Chain, const Type *RetTy, SDOperand Callee,
86 ArgListTy &Args, SelectionDAG &DAG);
88 virtual std::pair<SDOperand, SDOperand>
89 LowerVAStart(SDOperand Chain, SelectionDAG &DAG);
91 virtual std::pair<SDOperand,SDOperand>
92 LowerVAArgNext(bool isVANext, SDOperand Chain, SDOperand VAList,
93 const Type *ArgTy, SelectionDAG &DAG);
95 virtual std::pair<SDOperand, SDOperand>
96 LowerFrameReturnAddress(bool isFrameAddr, SDOperand Chain, unsigned Depth,
99 void restoreGP(MachineBasicBlock* BB)
101 BuildMI(BB, Alpha::BIS, 2, Alpha::R29).addReg(GP).addReg(GP);
106 //http://www.cs.arizona.edu/computer.help/policy/DIGITAL_unix/AA-PY8AC-TET1_html/callCH3.html#BLOCK21
108 //For now, just use variable size stack frame format
110 //In a standard call, the first six items are passed in registers $16
111 //- $21 and/or registers $f16 - $f21. (See Section 4.1.2 for details
112 //of argument-to-register correspondence.) The remaining items are
113 //collected in a memory argument list that is a naturally aligned
114 //array of quadwords. In a standard call, this list, if present, must
115 //be passed at 0(SP).
116 //7 ... n 0(SP) ... (n-7)*8(SP)
118 std::vector<SDOperand>
119 AlphaTargetLowering::LowerArguments(Function &F, SelectionDAG &DAG)
121 std::vector<SDOperand> ArgValues;
129 // assert(0 && "TODO");
130 MachineFunction &MF = DAG.getMachineFunction();
131 MachineFrameInfo*MFI = MF.getFrameInfo();
133 GP = MF.getSSARegMap()->createVirtualRegister(getRegClassFor(MVT::i64));
134 MachineBasicBlock& BB = MF.front();
136 //Handle the return address
137 //BuildMI(&BB, Alpha::IDEF, 0, Alpha::R26);
139 unsigned args_int[] = {Alpha::R16, Alpha::R17, Alpha::R18,
140 Alpha::R19, Alpha::R20, Alpha::R21};
141 unsigned args_float[] = {Alpha::F16, Alpha::F17, Alpha::F18,
142 Alpha::F19, Alpha::F20, Alpha::F21};
149 for (Function::aiterator I = F.abegin(), E = F.aend(); I != E; ++I)
151 SDOperand newroot, argt;
153 switch (getValueType(I->getType())) {
155 std::cerr << "Unknown Type " << getValueType(I->getType()) << "\n";
159 BuildMI(&BB, Alpha::IDEF, 0, args_float[count]);
161 MF.getSSARegMap()->createVirtualRegister(
162 getRegClassFor(getValueType(I->getType())));
163 argPreg[count] = args_float[count];
164 argOpc[count] = Alpha::CPYS;
165 argt = newroot = DAG.getCopyFromReg(argVreg[count],
166 getValueType(I->getType()),
174 BuildMI(&BB, Alpha::IDEF, 0, args_int[count]);
176 MF.getSSARegMap()->createVirtualRegister(getRegClassFor(MVT::i64));
177 argPreg[count] = args_int[count];
178 argOpc[count] = Alpha::BIS;
180 DAG.getCopyFromReg(argVreg[count], MVT::i64, DAG.getRoot());
181 if (getValueType(I->getType()) != MVT::i64)
183 DAG.getNode(ISD::TRUNCATE, getValueType(I->getType()), newroot);
187 // Create the frame index object for this incoming parameter...
188 int FI = MFI->CreateFixedObject(8, 8 * (count - 6));
190 // Create the SelectionDAG nodes corresponding to a load
191 //from this parameter
192 SDOperand FIN = DAG.getFrameIndex(FI, MVT::i64);
193 argt = newroot = DAG.getLoad(getValueType(I->getType()),
194 DAG.getEntryNode(), FIN);
197 DAG.setRoot(newroot.getValue(1));
198 ArgValues.push_back(argt);
201 BuildMI(&BB, Alpha::IDEF, 0, Alpha::R29);
202 BuildMI(&BB, Alpha::BIS, 2, GP).addReg(Alpha::R29).addReg(Alpha::R29);
203 for (int i = 0; i < count && i < 6; ++i) {
204 BuildMI(&BB, argOpc[i], 2,
205 argVreg[i]).addReg(argPreg[i]).addReg(argPreg[i]);
211 std::pair<SDOperand, SDOperand>
212 AlphaTargetLowering::LowerCallTo(SDOperand Chain,
213 const Type *RetTy, SDOperand Callee,
214 ArgListTy &Args, SelectionDAG &DAG) {
217 NumBytes = (Args.size() - 6) * 8;
219 Chain = DAG.getNode(ISD::ADJCALLSTACKDOWN, MVT::Other, Chain,
220 DAG.getConstant(NumBytes, getPointerTy()));
221 std::vector<SDOperand> args_to_use;
222 for (unsigned i = 0, e = Args.size(); i != e; ++i)
224 switch (getValueType(Args[i].second)) {
225 default: assert(0 && "Unexpected ValueType for argument!");
230 // Promote the integer to 64 bits. If the input type is signed use a
231 // sign extend, otherwise use a zero extend.
232 if (Args[i].second->isSigned())
233 Args[i].first = DAG.getNode(ISD::SIGN_EXTEND, MVT::i64, Args[i].first);
235 Args[i].first = DAG.getNode(ISD::ZERO_EXTEND, MVT::i64, Args[i].first);
242 args_to_use.push_back(Args[i].first);
245 std::vector<MVT::ValueType> RetVals;
246 MVT::ValueType RetTyVT = getValueType(RetTy);
247 if (RetTyVT != MVT::isVoid)
248 RetVals.push_back(RetTyVT);
249 RetVals.push_back(MVT::Other);
251 SDOperand TheCall = SDOperand(DAG.getCall(RetVals,
252 Chain, Callee, args_to_use), 0);
253 Chain = TheCall.getValue(RetTyVT != MVT::isVoid);
254 Chain = DAG.getNode(ISD::ADJCALLSTACKUP, MVT::Other, Chain,
255 DAG.getConstant(NumBytes, getPointerTy()));
256 return std::make_pair(TheCall, Chain);
259 std::pair<SDOperand, SDOperand>
260 AlphaTargetLowering::LowerVAStart(SDOperand Chain, SelectionDAG &DAG) {
261 //vastart just returns the address of the VarArgsFrameIndex slot.
262 return std::make_pair(DAG.getFrameIndex(VarArgsFrameIndex, MVT::i64), Chain);
265 std::pair<SDOperand,SDOperand> AlphaTargetLowering::
266 LowerVAArgNext(bool isVANext, SDOperand Chain, SDOperand VAList,
267 const Type *ArgTy, SelectionDAG &DAG) {
272 std::pair<SDOperand, SDOperand> AlphaTargetLowering::
273 LowerFrameReturnAddress(bool isFrameAddress, SDOperand Chain, unsigned Depth,
284 //===--------------------------------------------------------------------===//
285 /// ISel - Alpha specific code to select Alpha machine instructions for
286 /// SelectionDAG operations.
287 //===--------------------------------------------------------------------===//
288 class ISel : public SelectionDAGISel {
290 /// AlphaLowering - This object fully describes how to lower LLVM code to an
291 /// Alpha-specific SelectionDAG.
292 AlphaTargetLowering AlphaLowering;
295 /// ExprMap - As shared expressions are codegen'd, we keep track of which
296 /// vreg the value is produced in, so we only emit one copy of each compiled
298 static const unsigned notIn = (unsigned)(-1);
299 std::map<SDOperand, unsigned> ExprMap;
301 //CCInvMap sometimes (SetNE) we have the inverse CC code for free
302 std::map<SDOperand, unsigned> CCInvMap;
305 ISel(TargetMachine &TM) : SelectionDAGISel(AlphaLowering), AlphaLowering(TM)
308 /// InstructionSelectBasicBlock - This callback is invoked by
309 /// SelectionDAGISel when it has created a SelectionDAG for us to codegen.
310 virtual void InstructionSelectBasicBlock(SelectionDAG &DAG) {
312 // Codegen the basic block.
313 Select(DAG.getRoot());
315 // Clear state used for selection.
320 unsigned SelectExpr(SDOperand N);
321 unsigned SelectExprFP(SDOperand N, unsigned Result);
322 void Select(SDOperand N);
324 void SelectAddr(SDOperand N, unsigned& Reg, long& offset);
325 void SelectBranchCC(SDOperand N);
329 //These describe LDAx
330 static const int64_t IMM_LOW = 0xffffffffffff8000LL;
331 static const int IMM_HIGH = 0x0000000000007fffLL;
332 static const int IMM_MULT = 65536;
334 static long getUpper16(long l)
336 long y = l / IMM_MULT;
337 if (l % IMM_MULT > IMM_HIGH)
342 static long getLower16(long l)
344 long h = getUpper16(l);
345 return l - h * IMM_MULT;
348 static unsigned GetSymVersion(unsigned opcode)
351 default: assert(0 && "unknown load or store"); return 0;
352 case Alpha::LDQ: return Alpha::LDQ_SYM;
353 case Alpha::LDS: return Alpha::LDS_SYM;
354 case Alpha::LDT: return Alpha::LDT_SYM;
355 case Alpha::LDL: return Alpha::LDL_SYM;
356 case Alpha::LDBU: return Alpha::LDBU_SYM;
357 case Alpha::LDWU: return Alpha::LDWU_SYM;
358 case Alpha::LDW: return Alpha::LDW_SYM;
359 case Alpha::LDB: return Alpha::LDB_SYM;
360 case Alpha::STQ: return Alpha::STQ_SYM;
361 case Alpha::STS: return Alpha::STS_SYM;
362 case Alpha::STT: return Alpha::STT_SYM;
363 case Alpha::STL: return Alpha::STL_SYM;
364 case Alpha::STW: return Alpha::STW_SYM;
365 case Alpha::STB: return Alpha::STB_SYM;
369 //Check to see if the load is a constant offset from a base register
370 void ISel::SelectAddr(SDOperand N, unsigned& Reg, long& offset)
372 unsigned opcode = N.getOpcode();
373 if (opcode == ISD::ADD) {
374 if(N.getOperand(1).getOpcode() == ISD::Constant &&
375 cast<ConstantSDNode>(N.getOperand(1))->getValue() <= 32767)
377 Reg = SelectExpr(N.getOperand(0));
378 offset = cast<ConstantSDNode>(N.getOperand(1))->getValue();
381 else if(N.getOperand(0).getOpcode() == ISD::Constant &&
382 cast<ConstantSDNode>(N.getOperand(0))->getValue() <= 32767)
384 Reg = SelectExpr(N.getOperand(1));
385 offset = cast<ConstantSDNode>(N.getOperand(0))->getValue();
394 void ISel::SelectBranchCC(SDOperand N)
396 assert(N.getOpcode() == ISD::BRCOND && "Not a BranchCC???");
397 MachineBasicBlock *Dest =
398 cast<BasicBlockSDNode>(N.getOperand(2))->getBasicBlock();
399 unsigned Opc = Alpha::WTF;
401 Select(N.getOperand(0)); //chain
402 SDOperand CC = N.getOperand(1);
404 if (CC.getOpcode() == ISD::SETCC)
406 SetCCSDNode* SetCC = dyn_cast<SetCCSDNode>(CC.Val);
407 if (MVT::isInteger(SetCC->getOperand(0).getValueType())) {
408 //Dropping the CC is only useful if we are comparing to 0
409 bool isZero0 = false;
410 bool isZero1 = false;
413 if(SetCC->getOperand(0).getOpcode() == ISD::Constant &&
414 cast<ConstantSDNode>(SetCC->getOperand(0))->getValue() == 0)
416 if(SetCC->getOperand(1).getOpcode() == ISD::Constant &&
417 cast<ConstantSDNode>(SetCC->getOperand(1))->getValue() == 0)
419 if(SetCC->getCondition() == ISD::SETNE)
423 switch (SetCC->getCondition()) {
424 default: CC.Val->dump(); assert(0 && "Unknown integer comparison!");
425 case ISD::SETEQ: Opc = Alpha::BEQ; break;
426 case ISD::SETLT: Opc = Alpha::BGT; break;
427 case ISD::SETLE: Opc = Alpha::BGE; break;
428 case ISD::SETGT: Opc = Alpha::BLT; break;
429 case ISD::SETGE: Opc = Alpha::BLE; break;
430 case ISD::SETULT: Opc = Alpha::BNE; break;
431 case ISD::SETUGT: assert(0 && "0 > (unsigned) x is never true"); break;
432 case ISD::SETULE: assert(0 && "0 <= (unsigned) x is always true"); break;
433 case ISD::SETUGE: Opc = Alpha::BEQ; break; //Technically you could have this CC
434 case ISD::SETNE: Opc = Alpha::BNE; break;
436 unsigned Tmp1 = SelectExpr(SetCC->getOperand(1));
437 BuildMI(BB, Opc, 2).addReg(Tmp1).addMBB(Dest);
439 } else if (isZero1) {
440 switch (SetCC->getCondition()) {
441 default: CC.Val->dump(); assert(0 && "Unknown integer comparison!");
442 case ISD::SETEQ: Opc = Alpha::BEQ; break;
443 case ISD::SETLT: Opc = Alpha::BLT; break;
444 case ISD::SETLE: Opc = Alpha::BLE; break;
445 case ISD::SETGT: Opc = Alpha::BGT; break;
446 case ISD::SETGE: Opc = Alpha::BGE; break;
447 case ISD::SETULT: assert(0 && "x (unsigned) < 0 is never true"); break;
448 case ISD::SETUGT: Opc = Alpha::BNE; break;
449 case ISD::SETULE: Opc = Alpha::BEQ; break; //Technically you could have this CC
450 case ISD::SETUGE: assert(0 && "x (unsgined >= 0 is always true"); break;
451 case ISD::SETNE: Opc = Alpha::BNE; break;
453 unsigned Tmp1 = SelectExpr(SetCC->getOperand(0));
454 BuildMI(BB, Opc, 2).addReg(Tmp1).addMBB(Dest);
457 unsigned Tmp1 = SelectExpr(CC);
459 BuildMI(BB, Alpha::BEQ, 2).addReg(CCInvMap[CC]).addMBB(Dest);
461 BuildMI(BB, Alpha::BNE, 2).addReg(Tmp1).addMBB(Dest);
465 //Any comparison between 2 values should be codegened as an folded branch, as moving
466 //CC to the integer register is very expensive
467 //for a cmp b: c = a - b;
472 bool invTest = false;
475 ConstantFPSDNode *CN;
476 if ((CN = dyn_cast<ConstantFPSDNode>(SetCC->getOperand(1)))
477 && (CN->isExactlyValue(+0.0) || CN->isExactlyValue(-0.0)))
478 Tmp3 = SelectExpr(SetCC->getOperand(0));
479 else if ((CN = dyn_cast<ConstantFPSDNode>(SetCC->getOperand(0)))
480 && (CN->isExactlyValue(+0.0) || CN->isExactlyValue(-0.0)))
482 Tmp3 = SelectExpr(SetCC->getOperand(1));
487 unsigned Tmp1 = SelectExpr(SetCC->getOperand(0));
488 unsigned Tmp2 = SelectExpr(SetCC->getOperand(1));
489 bool isD = SetCC->getOperand(0).getValueType() == MVT::f64;
490 Tmp3 = MakeReg(isD ? MVT::f64 : MVT::f32);
491 BuildMI(BB, isD ? Alpha::SUBT : Alpha::SUBS, 2, Tmp3)
492 .addReg(Tmp1).addReg(Tmp2);
495 switch (SetCC->getCondition()) {
496 default: CC.Val->dump(); assert(0 && "Unknown FP comparison!");
497 case ISD::SETEQ: Opc = invTest ? Alpha::FBNE : Alpha::FBEQ; break;
498 case ISD::SETLT: Opc = invTest ? Alpha::FBGT : Alpha::FBLT; break;
499 case ISD::SETLE: Opc = invTest ? Alpha::FBGE : Alpha::FBLE; break;
500 case ISD::SETGT: Opc = invTest ? Alpha::FBLT : Alpha::FBGT; break;
501 case ISD::SETGE: Opc = invTest ? Alpha::FBLE : Alpha::FBGE; break;
502 case ISD::SETNE: Opc = invTest ? Alpha::FBEQ : Alpha::FBNE; break;
504 BuildMI(BB, Opc, 2).addReg(Tmp3).addMBB(Dest);
507 abort(); //Should never be reached
509 //Giveup and do the stupid thing
510 unsigned Tmp1 = SelectExpr(CC);
511 BuildMI(BB, Alpha::BNE, 2).addReg(Tmp1).addMBB(Dest);
514 abort(); //Should never be reached
517 unsigned ISel::SelectExprFP(SDOperand N, unsigned Result)
519 unsigned Tmp1, Tmp2, Tmp3;
521 SDNode *Node = N.Val;
522 MVT::ValueType DestType = N.getValueType();
523 unsigned opcode = N.getOpcode();
528 assert(0 && "Node not handled!\n");
532 //Tmp1 = SelectExpr(N.getOperand(0)); //Cond
533 unsigned TV = SelectExpr(N.getOperand(1)); //Use if TRUE
534 unsigned FV = SelectExpr(N.getOperand(2)); //Use if FALSE
536 SDOperand CC = N.getOperand(0);
537 SetCCSDNode* SetCC = dyn_cast<SetCCSDNode>(CC.Val);
539 if (CC.getOpcode() == ISD::SETCC &&
540 !MVT::isInteger(SetCC->getOperand(0).getValueType()))
541 { //FP Setcc -> Select yay!
544 //for a cmp b: c = a - b;
549 bool invTest = false;
552 ConstantFPSDNode *CN;
553 if ((CN = dyn_cast<ConstantFPSDNode>(SetCC->getOperand(1)))
554 && (CN->isExactlyValue(+0.0) || CN->isExactlyValue(-0.0)))
555 Tmp3 = SelectExpr(SetCC->getOperand(0));
556 else if ((CN = dyn_cast<ConstantFPSDNode>(SetCC->getOperand(0)))
557 && (CN->isExactlyValue(+0.0) || CN->isExactlyValue(-0.0)))
559 Tmp3 = SelectExpr(SetCC->getOperand(1));
564 unsigned Tmp1 = SelectExpr(SetCC->getOperand(0));
565 unsigned Tmp2 = SelectExpr(SetCC->getOperand(1));
566 bool isD = SetCC->getOperand(0).getValueType() == MVT::f64;
567 Tmp3 = MakeReg(isD ? MVT::f64 : MVT::f32);
568 BuildMI(BB, isD ? Alpha::SUBT : Alpha::SUBS, 2, Tmp3)
569 .addReg(Tmp1).addReg(Tmp2);
572 switch (SetCC->getCondition()) {
573 default: CC.Val->dump(); assert(0 && "Unknown FP comparison!");
574 case ISD::SETEQ: Opc = invTest ? Alpha::FCMOVNE : Alpha::FCMOVEQ; break;
575 case ISD::SETLT: Opc = invTest ? Alpha::FCMOVGT : Alpha::FCMOVLT; break;
576 case ISD::SETLE: Opc = invTest ? Alpha::FCMOVGE : Alpha::FCMOVLE; break;
577 case ISD::SETGT: Opc = invTest ? Alpha::FCMOVLT : Alpha::FCMOVGT; break;
578 case ISD::SETGE: Opc = invTest ? Alpha::FCMOVLE : Alpha::FCMOVGE; break;
579 case ISD::SETNE: Opc = invTest ? Alpha::FCMOVEQ : Alpha::FCMOVNE; break;
581 BuildMI(BB, Opc, 3, Result).addReg(FV).addReg(TV).addReg(Tmp3);
586 Tmp1 = SelectExpr(N.getOperand(0)); //Cond
587 // Spill the cond to memory and reload it from there.
588 unsigned Size = MVT::getSizeInBits(MVT::f64)/8;
589 MachineFunction *F = BB->getParent();
590 int FrameIdx = F->getFrameInfo()->CreateStackObject(Size, 8);
591 unsigned Tmp4 = MakeReg(MVT::f64);
592 BuildMI(BB, Alpha::STQ, 3).addReg(Tmp1).addFrameIndex(FrameIdx).addReg(Alpha::F31);
593 BuildMI(BB, Alpha::LDT, 2, Tmp4).addFrameIndex(FrameIdx).addReg(Alpha::F31);
594 //now ideally, we don't have to do anything to the flag...
595 // Get the condition into the zero flag.
596 BuildMI(BB, Alpha::FCMOVEQ, 3, Result).addReg(TV).addReg(FV).addReg(Tmp4);
602 assert (DestType == MVT::f32 &&
603 N.getOperand(0).getValueType() == MVT::f64 &&
604 "only f64 to f32 conversion supported here");
605 Tmp1 = SelectExpr(N.getOperand(0));
606 BuildMI(BB, Alpha::CVTTS, 1, Result).addReg(Tmp1);
610 assert (DestType == MVT::f64 &&
611 N.getOperand(0).getValueType() == MVT::f32 &&
612 "only f32 to f64 conversion supported here");
613 Tmp1 = SelectExpr(N.getOperand(0));
614 BuildMI(BB, Alpha::CVTST, 1, Result).addReg(Tmp1);
617 case ISD::CopyFromReg:
619 // Make sure we generate both values.
621 ExprMap[N.getValue(1)] = notIn; // Generate the token
623 Result = ExprMap[N.getValue(0)] = MakeReg(N.getValue(0).getValueType());
625 SDOperand Chain = N.getOperand(0);
628 unsigned r = dyn_cast<RegSDNode>(Node)->getReg();
629 //std::cerr << "CopyFromReg " << Result << " = " << r << "\n";
630 BuildMI(BB, Alpha::CPYS, 2, Result).addReg(r).addReg(r);
636 // Make sure we generate both values.
638 ExprMap[N.getValue(1)] = notIn; // Generate the token
640 Result = ExprMap[N.getValue(0)] = MakeReg(N.getValue(0).getValueType());
642 DestType = N.getValue(0).getValueType();
644 SDOperand Chain = N.getOperand(0);
645 SDOperand Address = N.getOperand(1);
647 Opc = DestType == MVT::f64 ? Alpha::LDT : Alpha::LDS;
649 if (Address.getOpcode() == ISD::GlobalAddress) {
650 AlphaLowering.restoreGP(BB);
651 Opc = GetSymVersion(Opc);
652 BuildMI(BB, Opc, 1, Result).addGlobalAddress(cast<GlobalAddressSDNode>(Address)->getGlobal());
654 else if (ConstantPoolSDNode *CP = dyn_cast<ConstantPoolSDNode>(Address)) {
655 AlphaLowering.restoreGP(BB);
656 Opc = GetSymVersion(Opc);
657 BuildMI(BB, Opc, 1, Result).addConstantPoolIndex(CP->getIndex());
659 else if(Address.getOpcode() == ISD::FrameIndex) {
660 BuildMI(BB, Opc, 2, Result)
661 .addFrameIndex(cast<FrameIndexSDNode>(Address)->getIndex())
665 SelectAddr(Address, Tmp1, offset);
666 BuildMI(BB, Opc, 2, Result).addImm(offset).addReg(Tmp1);
670 case ISD::ConstantFP:
671 if (ConstantFPSDNode *CN = dyn_cast<ConstantFPSDNode>(N)) {
672 if (CN->isExactlyValue(+0.0)) {
673 BuildMI(BB, Alpha::CPYS, 2, Result).addReg(Alpha::F31).addReg(Alpha::F31);
674 } else if ( CN->isExactlyValue(-0.0)) {
675 BuildMI(BB, Alpha::CPYSN, 2, Result).addReg(Alpha::F31).addReg(Alpha::F31);
687 case ISD::MUL: Opc = DestType == MVT::f64 ? Alpha::MULT : Alpha::MULS; break;
688 case ISD::ADD: Opc = DestType == MVT::f64 ? Alpha::ADDT : Alpha::ADDS; break;
689 case ISD::SUB: Opc = DestType == MVT::f64 ? Alpha::SUBT : Alpha::SUBS; break;
690 case ISD::SDIV: Opc = DestType == MVT::f64 ? Alpha::DIVT : Alpha::DIVS; break;
693 ConstantFPSDNode *CN;
694 if (opcode == ISD::SUB
695 && (CN = dyn_cast<ConstantFPSDNode>(N.getOperand(0)))
696 && (CN->isExactlyValue(+0.0) || CN->isExactlyValue(-0.0)))
698 Tmp2 = SelectExpr(N.getOperand(1));
699 BuildMI(BB, Alpha::CPYSN, 2, Result).addReg(Tmp2).addReg(Tmp2);
701 Tmp1 = SelectExpr(N.getOperand(0));
702 Tmp2 = SelectExpr(N.getOperand(1));
703 BuildMI(BB, Opc, 2, Result).addReg(Tmp1).addReg(Tmp2);
709 //include a conversion sequence for float loads to double
711 ExprMap[N.getValue(1)] = notIn; // Generate the token
713 Result = ExprMap[N.getValue(0)] = MakeReg(N.getValue(0).getValueType());
715 Tmp1 = MakeReg(MVT::f32);
717 assert(cast<MVTSDNode>(Node)->getExtraValueType() == MVT::f32 &&
718 "EXTLOAD not from f32");
719 assert(Node->getValueType(0) == MVT::f64 && "EXTLOAD not to f64");
721 SDOperand Chain = N.getOperand(0);
722 SDOperand Address = N.getOperand(1);
725 if (Address.getOpcode() == ISD::GlobalAddress) {
726 AlphaLowering.restoreGP(BB);
727 BuildMI(BB, Alpha::LDS_SYM, 1, Tmp1).addGlobalAddress(cast<GlobalAddressSDNode>(Address)->getGlobal());
729 else if (ConstantPoolSDNode *CP =
730 dyn_cast<ConstantPoolSDNode>(N.getOperand(1)))
732 AlphaLowering.restoreGP(BB);
733 BuildMI(BB, Alpha::LDS_SYM, 1, Tmp1).addConstantPoolIndex(CP->getIndex());
735 else if(Address.getOpcode() == ISD::FrameIndex) {
736 Tmp2 = cast<FrameIndexSDNode>(Address)->getIndex();
737 BuildMI(BB, Alpha::LDS, 2, Tmp1)
738 .addFrameIndex(cast<FrameIndexSDNode>(Address)->getIndex())
742 SelectAddr(Address, Tmp2, offset);
743 BuildMI(BB, Alpha::LDS, 1, Tmp1).addImm(offset).addReg(Tmp2);
745 BuildMI(BB, Alpha::CVTST, 1, Result).addReg(Tmp1);
749 case ISD::UINT_TO_FP:
750 case ISD::SINT_TO_FP:
752 assert (N.getOperand(0).getValueType() == MVT::i64
753 && "only quads can be loaded from");
754 Tmp1 = SelectExpr(N.getOperand(0)); // Get the operand register
755 Tmp2 = MakeReg(MVT::f64);
758 // Spill the integer to memory and reload it from there.
759 unsigned Size = MVT::getSizeInBits(MVT::i64)/8;
760 MachineFunction *F = BB->getParent();
761 int FrameIdx = F->getFrameInfo()->CreateStackObject(Size, Size);
763 BuildMI(BB, Alpha::STQ, 3).addReg(Tmp1).addFrameIndex(FrameIdx).addReg(Alpha::F31);
764 BuildMI(BB, Alpha::LDT, 2, Tmp2).addFrameIndex(FrameIdx).addReg(Alpha::F31);
765 Opc = DestType == MVT::f64 ? Alpha::CVTQT : Alpha::CVTQS;
766 BuildMI(BB, Opc, 1, Result).addReg(Tmp2);
768 //The easy way: doesn't work
769 // //so these instructions are not supported on ev56
770 // Opc = DestType == MVT::f64 ? Alpha::ITOFT : Alpha::ITOFS;
771 // BuildMI(BB, Opc, 1, Tmp2).addReg(Tmp1);
772 // Opc = DestType == MVT::f64 ? Alpha::CVTQT : Alpha::CVTQS;
773 // BuildMI(BB, Opc, 1, Result).addReg(Tmp1);
778 assert(0 && "should not get here");
782 unsigned ISel::SelectExpr(SDOperand N) {
784 unsigned Tmp1, Tmp2, Tmp3;
786 unsigned opcode = N.getOpcode();
788 SDNode *Node = N.Val;
789 MVT::ValueType DestType = N.getValueType();
791 unsigned &Reg = ExprMap[N];
794 if (N.getOpcode() != ISD::CALL)
795 Reg = Result = (N.getValueType() != MVT::Other) ?
796 MakeReg(N.getValueType()) : notIn;
798 // If this is a call instruction, make sure to prepare ALL of the result
799 // values as well as the chain.
800 if (Node->getNumValues() == 1)
801 Reg = Result = notIn; // Void call, just a chain.
803 Result = MakeReg(Node->getValueType(0));
804 ExprMap[N.getValue(0)] = Result;
805 for (unsigned i = 1, e = N.Val->getNumValues()-1; i != e; ++i)
806 ExprMap[N.getValue(i)] = MakeReg(Node->getValueType(i));
807 ExprMap[SDOperand(Node, Node->getNumValues()-1)] = notIn;
811 if (DestType == MVT::f64 || DestType == MVT::f32 ||
813 (opcode == ISD::LOAD || opcode == ISD::CopyFromReg ||
814 opcode == ISD::EXTLOAD) &&
815 (N.getValue(0).getValueType() == MVT::f32 ||
816 N.getValue(0).getValueType() == MVT::f64)
819 return SelectExprFP(N, Result);
824 assert(0 && "Node not handled!\n");
826 case ISD::DYNAMIC_STACKALLOC:
827 // Generate both result values.
829 ExprMap[N.getValue(1)] = notIn; // Generate the token
831 Result = ExprMap[N.getValue(0)] = MakeReg(N.getValue(0).getValueType());
833 // FIXME: We are currently ignoring the requested alignment for handling
834 // greater than the stack alignment. This will need to be revisited at some
835 // point. Align = N.getOperand(2);
837 if (!isa<ConstantSDNode>(N.getOperand(2)) ||
838 cast<ConstantSDNode>(N.getOperand(2))->getValue() != 0) {
839 std::cerr << "Cannot allocate stack object with greater alignment than"
840 << " the stack alignment yet!";
844 Select(N.getOperand(0));
845 if (ConstantSDNode* CN = dyn_cast<ConstantSDNode>(N.getOperand(1)))
847 if (CN->getValue() < 32000)
849 BuildMI(BB, Alpha::LDA, 2, Alpha::R30)
850 .addImm(-CN->getValue()).addReg(Alpha::R30);
852 Tmp1 = SelectExpr(N.getOperand(1));
853 // Subtract size from stack pointer, thereby allocating some space.
854 BuildMI(BB, Alpha::SUBQ, 2, Alpha::R30).addReg(Alpha::R30).addReg(Tmp1);
857 Tmp1 = SelectExpr(N.getOperand(1));
858 // Subtract size from stack pointer, thereby allocating some space.
859 BuildMI(BB, Alpha::SUBQ, 2, Alpha::R30).addReg(Alpha::R30).addReg(Tmp1);
862 // Put a pointer to the space into the result register, by copying the stack
864 BuildMI(BB, Alpha::BIS, 2, Result).addReg(Alpha::R30).addReg(Alpha::R30);
867 // case ISD::ConstantPool:
868 // Tmp1 = cast<ConstantPoolSDNode>(N)->getIndex();
869 // AlphaLowering.restoreGP(BB);
870 // BuildMI(BB, Alpha::LDQ_SYM, 1, Result).addConstantPoolIndex(Tmp1);
873 case ISD::FrameIndex:
874 BuildMI(BB, Alpha::LDA, 2, Result)
875 .addFrameIndex(cast<FrameIndexSDNode>(N)->getIndex())
884 // Make sure we generate both values.
886 ExprMap[N.getValue(1)] = notIn; // Generate the token
888 Result = ExprMap[N.getValue(0)] = MakeReg(N.getValue(0).getValueType());
890 SDOperand Chain = N.getOperand(0);
891 SDOperand Address = N.getOperand(1);
894 assert(Node->getValueType(0) == MVT::i64 &&
895 "Unknown type to sign extend to.");
896 if (opcode == ISD::LOAD)
899 switch (cast<MVTSDNode>(Node)->getExtraValueType()) {
900 default: Node->dump(); assert(0 && "Bad sign extend!");
901 case MVT::i32: Opc = Alpha::LDL;
902 assert(opcode != ISD::ZEXTLOAD && "Not sext"); break;
903 case MVT::i16: Opc = Alpha::LDWU;
904 assert(opcode != ISD::SEXTLOAD && "Not zext"); break;
905 case MVT::i1: //FIXME: Treat i1 as i8 since there are problems otherwise
906 case MVT::i8: Opc = Alpha::LDBU;
907 assert(opcode != ISD::SEXTLOAD && "Not zext"); break;
910 if (Address.getOpcode() == ISD::GlobalAddress) {
911 AlphaLowering.restoreGP(BB);
912 Opc = GetSymVersion(Opc);
913 BuildMI(BB, Opc, 1, Result).addGlobalAddress(cast<GlobalAddressSDNode>(Address)->getGlobal());
915 else if (ConstantPoolSDNode *CP = dyn_cast<ConstantPoolSDNode>(Address)) {
916 AlphaLowering.restoreGP(BB);
917 Opc = GetSymVersion(Opc);
918 BuildMI(BB, Opc, 1, Result).addConstantPoolIndex(CP->getIndex());
920 else if(Address.getOpcode() == ISD::FrameIndex) {
921 BuildMI(BB, Opc, 2, Result)
922 .addFrameIndex(cast<FrameIndexSDNode>(Address)->getIndex())
926 SelectAddr(Address, Tmp1, offset);
927 BuildMI(BB, Opc, 2, Result).addImm(offset).addReg(Tmp1);
932 case ISD::GlobalAddress:
933 AlphaLowering.restoreGP(BB);
934 BuildMI(BB, Alpha::LOAD_ADDR, 1, Result)
935 .addGlobalAddress(cast<GlobalAddressSDNode>(N)->getGlobal());
940 Select(N.getOperand(0));
942 // The chain for this call is now lowered.
943 ExprMap.insert(std::make_pair(N.getValue(Node->getNumValues()-1), notIn));
946 std::vector<unsigned> argvregs;
947 //assert(Node->getNumOperands() < 8 && "Only 6 args supported");
948 for(int i = 2, e = Node->getNumOperands(); i < e; ++i)
949 argvregs.push_back(SelectExpr(N.getOperand(i)));
952 for(int i = 0, e = std::min(6, (int)argvregs.size()); i < e; ++i)
954 unsigned args_int[] = {Alpha::R16, Alpha::R17, Alpha::R18,
955 Alpha::R19, Alpha::R20, Alpha::R21};
956 unsigned args_float[] = {Alpha::F16, Alpha::F17, Alpha::F18,
957 Alpha::F19, Alpha::F20, Alpha::F21};
958 switch(N.getOperand(i+2).getValueType()) {
961 N.getOperand(i).Val->dump();
962 std::cerr << "Type for " << i << " is: " <<
963 N.getOperand(i+2).getValueType() << "\n";
964 assert(0 && "Unknown value type for call");
970 BuildMI(BB, Alpha::BIS, 2, args_int[i]).addReg(argvregs[i]).addReg(argvregs[i]);
974 BuildMI(BB, Alpha::CPYS, 2, args_float[i]).addReg(argvregs[i]).addReg(argvregs[i]);
979 for (int i = 6, e = argvregs.size(); i < e; ++i)
981 switch(N.getOperand(i+2).getValueType()) {
984 N.getOperand(i).Val->dump();
985 std::cerr << "Type for " << i << " is: " <<
986 N.getOperand(i+2).getValueType() << "\n";
987 assert(0 && "Unknown value type for call");
993 BuildMI(BB, Alpha::STQ, 3).addReg(argvregs[i]).addImm((i - 6) * 8).addReg(Alpha::R30);
996 BuildMI(BB, Alpha::STS, 3).addReg(argvregs[i]).addImm((i - 6) * 8).addReg(Alpha::R30);
999 BuildMI(BB, Alpha::STT, 3).addReg(argvregs[i]).addImm((i - 6) * 8).addReg(Alpha::R30);
1003 //build the right kind of call
1004 if (GlobalAddressSDNode *GASD =
1005 dyn_cast<GlobalAddressSDNode>(N.getOperand(1)))
1007 //if (GASD->getGlobal()->isExternal()) {
1008 //use safe calling convention
1009 AlphaLowering.restoreGP(BB);
1010 BuildMI(BB, Alpha::CALL, 1).addGlobalAddress(GASD->getGlobal(),true);
1012 //use PC relative branch call
1013 //BuildMI(BB, Alpha::BSR, 1, Alpha::R26).addGlobalAddress(GASD->getGlobal(),true);
1016 else if (ExternalSymbolSDNode *ESSDN =
1017 dyn_cast<ExternalSymbolSDNode>(N.getOperand(1)))
1019 AlphaLowering.restoreGP(BB);
1020 BuildMI(BB, Alpha::CALL, 0).addExternalSymbol(ESSDN->getSymbol(), true);
1022 //no need to restore GP as we are doing an indirect call
1023 Tmp1 = SelectExpr(N.getOperand(1));
1024 BuildMI(BB, Alpha::BIS, 2, Alpha::R27).addReg(Tmp1).addReg(Tmp1);
1025 BuildMI(BB, Alpha::JSR, 2, Alpha::R26).addReg(Alpha::R27).addImm(0);
1028 //push the result into a virtual register
1030 switch (Node->getValueType(0)) {
1031 default: Node->dump(); assert(0 && "Unknown value type for call result!");
1032 case MVT::Other: return notIn;
1038 BuildMI(BB, Alpha::BIS, 2, Result).addReg(Alpha::R0).addReg(Alpha::R0);
1042 BuildMI(BB, Alpha::CPYS, 2, Result).addReg(Alpha::F0).addReg(Alpha::F0);
1045 return Result+N.ResNo;
1048 case ISD::SIGN_EXTEND:
1051 case ISD::SIGN_EXTEND_INREG:
1053 //Alpha has instructions for a bunch of signed 32 bit stuff
1054 if( dyn_cast<MVTSDNode>(Node)->getExtraValueType() == MVT::i32)
1056 switch (N.getOperand(0).getOpcode()) {
1061 bool isAdd = N.getOperand(0).getOpcode() == ISD::ADD;
1062 bool isMul = N.getOperand(0).getOpcode() == ISD::MUL;
1063 //FIXME: first check for Scaled Adds and Subs!
1064 if(N.getOperand(0).getOperand(1).getOpcode() == ISD::Constant &&
1065 cast<ConstantSDNode>(N.getOperand(0).getOperand(1))->getValue() <= 255)
1066 { //Normal imm add/sub
1067 Opc = isAdd ? Alpha::ADDLi : (isMul ? Alpha::MULLi : Alpha::SUBLi);
1068 //if the value was really originally a i32, skip the up conversion
1069 if (N.getOperand(0).getOperand(0).getOpcode() == ISD::SIGN_EXTEND_INREG &&
1070 dyn_cast<MVTSDNode>(N.getOperand(0).getOperand(0).Val)
1071 ->getExtraValueType() == MVT::i32)
1072 Tmp1 = SelectExpr(N.getOperand(0).getOperand(0).getOperand(0));
1074 Tmp1 = SelectExpr(N.getOperand(0).getOperand(0));
1075 Tmp2 = cast<ConstantSDNode>(N.getOperand(0).getOperand(1))->getValue();
1076 BuildMI(BB, Opc, 2, Result).addReg(Tmp1).addImm(Tmp2);
1080 Opc = isAdd ? Alpha::ADDL : (isMul ? Alpha::MULLi : Alpha::SUBL);
1081 //if the value was really originally a i32, skip the up conversion
1082 if (N.getOperand(0).getOperand(0).getOpcode() == ISD::SIGN_EXTEND_INREG &&
1083 dyn_cast<MVTSDNode>(N.getOperand(0).getOperand(0).Val)
1084 ->getExtraValueType() == MVT::i32)
1085 Tmp1 = SelectExpr(N.getOperand(0).getOperand(0).getOperand(0));
1087 Tmp1 = SelectExpr(N.getOperand(0).getOperand(0));
1088 //if the value was really originally a i32, skip the up conversion
1089 if (N.getOperand(0).getOperand(1).getOpcode() == ISD::SIGN_EXTEND_INREG &&
1090 dyn_cast<MVTSDNode>(N.getOperand(0).getOperand(1).Val)
1091 ->getExtraValueType() == MVT::i32)
1092 Tmp2 = SelectExpr(N.getOperand(0).getOperand(1).getOperand(0));
1094 Tmp2 = SelectExpr(N.getOperand(0).getOperand(1));
1096 Tmp1 = SelectExpr(N.getOperand(0).getOperand(0));
1097 Tmp2 = SelectExpr(N.getOperand(0).getOperand(1));
1098 BuildMI(BB, Opc, 2, Result).addReg(Tmp1).addReg(Tmp2);
1103 //SelectionDag isn't deleting the signextend after sextloads
1104 Reg = Result = SelectExpr(N.getOperand(0));
1106 default: break; //Fall Though;
1108 } //Every thing else fall though too, including unhandled opcodes above
1109 Tmp1 = SelectExpr(N.getOperand(0));
1110 MVTSDNode* MVN = dyn_cast<MVTSDNode>(Node);
1111 //std::cerr << "SrcT: " << MVN->getExtraValueType() << "\n";
1112 switch(MVN->getExtraValueType())
1116 assert(0 && "Sign Extend InReg not there yet");
1120 BuildMI(BB, Alpha::ADDLi, 2, Result).addReg(Tmp1).addImm(0);
1124 BuildMI(BB, Alpha::SEXTW, 1, Result).addReg(Tmp1);
1127 BuildMI(BB, Alpha::SEXTB, 1, Result).addReg(Tmp1);
1130 Tmp2 = MakeReg(MVT::i64);
1131 BuildMI(BB, Alpha::ANDi, 2, Tmp2).addReg(Tmp1).addImm(1);
1132 BuildMI(BB, Alpha::SUBQ, 2, Result).addReg(Alpha::F31).addReg(Tmp2);
1137 case ISD::ZERO_EXTEND_INREG:
1139 Tmp1 = SelectExpr(N.getOperand(0));
1140 MVTSDNode* MVN = dyn_cast<MVTSDNode>(Node);
1141 //std::cerr << "SrcT: " << MVN->getExtraValueType() << "\n";
1142 switch(MVN->getExtraValueType())
1146 assert(0 && "Zero Extend InReg not there yet");
1148 case MVT::i32: Tmp2 = 0xf0; break;
1149 case MVT::i16: Tmp2 = 0xfc; break;
1150 case MVT::i8: Tmp2 = 0xfe; break;
1151 case MVT::i1: //handle this one special
1152 BuildMI(BB, Alpha::ANDi, 2, Result).addReg(Tmp1).addImm(1);
1155 BuildMI(BB, Alpha::ZAPi, 2, Result).addReg(Tmp1).addImm(Tmp2);
1161 if (SetCCSDNode *SetCC = dyn_cast<SetCCSDNode>(Node)) {
1162 if (MVT::isInteger(SetCC->getOperand(0).getValueType())) {
1163 bool isConst1 = false;
1164 bool isConst2 = false;
1167 //Tmp1 = SelectExpr(N.getOperand(0));
1168 if(N.getOperand(0).getOpcode() == ISD::Constant &&
1169 cast<ConstantSDNode>(N.getOperand(0))->getValue() <= 255)
1171 if(N.getOperand(1).getOpcode() == ISD::Constant &&
1172 cast<ConstantSDNode>(N.getOperand(1))->getValue() <= 255)
1175 switch (SetCC->getCondition()) {
1176 default: Node->dump(); assert(0 && "Unknown integer comparison!");
1177 case ISD::SETEQ: Opc = Alpha::CMPEQ; dir=0; break;
1179 Opc = isConst2 ? Alpha::CMPLTi : Alpha::CMPLT; dir = 1; break;
1181 Opc = isConst2 ? Alpha::CMPLEi : Alpha::CMPLE; dir = 1; break;
1183 Opc = isConst1 ? Alpha::CMPLTi : Alpha::CMPLT; dir = 2; break;
1185 Opc = isConst1 ? Alpha::CMPLEi : Alpha::CMPLE; dir = 2; break;
1187 Opc = isConst2 ? Alpha::CMPULTi : Alpha::CMPULT; dir = 1; break;
1189 Opc = isConst1 ? Alpha::CMPULTi : Alpha::CMPULT; dir = 2; break;
1191 Opc = isConst2 ? Alpha::CMPULEi : Alpha::CMPULE; dir = 1; break;
1193 Opc = isConst1 ? Alpha::CMPULEi : Alpha::CMPULE; dir = 2; break;
1194 case ISD::SETNE: {//Handle this one special
1195 //std::cerr << "Alpha does not have a setne.\n";
1197 Tmp1 = SelectExpr(N.getOperand(0));
1198 Tmp2 = SelectExpr(N.getOperand(1));
1199 Tmp3 = MakeReg(MVT::i64);
1200 BuildMI(BB, Alpha::CMPEQ, 2, Tmp3).addReg(Tmp1).addReg(Tmp2);
1201 //Remeber we have the Inv for this CC
1204 BuildMI(BB, Alpha::CMPEQ, 2, Result).addReg(Alpha::R31).addReg(Tmp3);
1209 Tmp1 = SelectExpr(N.getOperand(0));
1211 Tmp2 = cast<ConstantSDNode>(N.getOperand(1))->getValue();
1212 BuildMI(BB, Opc, 2, Result).addReg(Tmp1).addImm(Tmp2);
1214 Tmp2 = SelectExpr(N.getOperand(1));
1215 BuildMI(BB, Opc, 2, Result).addReg(Tmp1).addReg(Tmp2);
1217 } else if (dir == 2) {
1218 Tmp1 = SelectExpr(N.getOperand(1));
1220 Tmp2 = cast<ConstantSDNode>(N.getOperand(0))->getValue();
1221 BuildMI(BB, Opc, 2, Result).addReg(Tmp1).addImm(Tmp2);
1223 Tmp2 = SelectExpr(N.getOperand(0));
1224 BuildMI(BB, Opc, 2, Result).addReg(Tmp1).addReg(Tmp2);
1228 Tmp1 = cast<ConstantSDNode>(N.getOperand(0))->getValue();
1229 Tmp2 = SelectExpr(N.getOperand(1));
1230 BuildMI(BB, Alpha::CMPEQi, 2, Result).addReg(Tmp2).addImm(Tmp1);
1231 } else if (isConst2) {
1232 Tmp1 = SelectExpr(N.getOperand(0));
1233 Tmp2 = cast<ConstantSDNode>(N.getOperand(1))->getValue();
1234 BuildMI(BB, Alpha::CMPEQi, 2, Result).addReg(Tmp1).addImm(Tmp2);
1236 Tmp1 = SelectExpr(N.getOperand(0));
1237 Tmp2 = SelectExpr(N.getOperand(1));
1238 BuildMI(BB, Alpha::CMPEQ, 2, Result).addReg(Tmp1).addReg(Tmp2);
1242 //assert(SetCC->getOperand(0).getValueType() != MVT::f32 && "SetCC f32 should have been promoted");
1246 switch (SetCC->getCondition()) {
1247 default: Node->dump(); assert(0 && "Unknown FP comparison!");
1248 case ISD::SETEQ: Opc = Alpha::CMPTEQ; break;
1249 case ISD::SETLT: Opc = Alpha::CMPTLT; break;
1250 case ISD::SETLE: Opc = Alpha::CMPTLE; break;
1251 case ISD::SETGT: Opc = Alpha::CMPTLT; rev = true; break;
1252 case ISD::SETGE: Opc = Alpha::CMPTLE; rev = true; break;
1253 case ISD::SETNE: Opc = Alpha::CMPTEQ; inv = true; break;
1256 Tmp1 = SelectExpr(N.getOperand(0));
1257 Tmp2 = SelectExpr(N.getOperand(1));
1258 //Can only compare doubles, and dag won't promote for me
1259 if (SetCC->getOperand(0).getValueType() == MVT::f32)
1261 //assert(0 && "Setcc On float?\n");
1262 std::cerr << "Setcc on float!\n";
1263 Tmp3 = MakeReg(MVT::f64);
1264 BuildMI(BB, Alpha::CVTST, 1, Tmp3).addReg(Tmp1);
1267 if (SetCC->getOperand(1).getValueType() == MVT::f32)
1269 //assert (0 && "Setcc On float?\n");
1270 std::cerr << "Setcc on float!\n";
1271 Tmp3 = MakeReg(MVT::f64);
1272 BuildMI(BB, Alpha::CVTST, 1, Tmp3).addReg(Tmp2);
1276 if (rev) std::swap(Tmp1, Tmp2);
1277 Tmp3 = MakeReg(MVT::f64);
1279 BuildMI(BB, Opc, 2, Tmp3).addReg(Tmp1).addReg(Tmp2);
1281 //now arrange for Result (int) to have a 1 or 0
1283 // Spill the FP to memory and reload it from there.
1284 unsigned Size = MVT::getSizeInBits(MVT::f64)/8;
1285 MachineFunction *F = BB->getParent();
1286 int FrameIdx = F->getFrameInfo()->CreateStackObject(Size, 8);
1287 unsigned Tmp4 = MakeReg(MVT::f64);
1288 BuildMI(BB, Alpha::CVTTQ, 1, Tmp4).addReg(Tmp3);
1289 BuildMI(BB, Alpha::STT, 3).addReg(Tmp4).addFrameIndex(FrameIdx).addReg(Alpha::F31);
1290 unsigned Tmp5 = MakeReg(MVT::i64);
1291 BuildMI(BB, Alpha::LDQ, 2, Tmp5).addFrameIndex(FrameIdx).addReg(Alpha::F31);
1293 //now, set result based on Tmp5
1294 //Set Tmp6 if fp cmp was false
1295 unsigned Tmp6 = MakeReg(MVT::i64);
1296 BuildMI(BB, Alpha::CMPEQ, 2, Tmp6).addReg(Tmp5).addReg(Alpha::R31);
1298 BuildMI(BB, Alpha::CMPEQ, 2, Result).addReg(Tmp6).addReg(Alpha::R31);
1304 // assert(0 && "Not a setcc in setcc");
1310 case ISD::CopyFromReg:
1312 // Make sure we generate both values.
1313 if (Result != notIn)
1314 ExprMap[N.getValue(1)] = notIn; // Generate the token
1316 Result = ExprMap[N.getValue(0)] = MakeReg(N.getValue(0).getValueType());
1318 SDOperand Chain = N.getOperand(0);
1321 unsigned r = dyn_cast<RegSDNode>(Node)->getReg();
1322 //std::cerr << "CopyFromReg " << Result << " = " << r << "\n";
1323 BuildMI(BB, Alpha::BIS, 2, Result).addReg(r).addReg(r);
1327 //Most of the plain arithmetic and logic share the same form, and the same
1328 //constant immediate test
1336 assert (DestType == MVT::i64 && "Only do arithmetic on i64s!");
1337 if(N.getOperand(1).getOpcode() == ISD::Constant &&
1338 cast<ConstantSDNode>(N.getOperand(1))->getValue() <= 255)
1341 case ISD::AND: Opc = Alpha::ANDi; break;
1342 case ISD::OR: Opc = Alpha::BISi; break;
1343 case ISD::XOR: Opc = Alpha::XORi; break;
1344 case ISD::SHL: Opc = Alpha::SLi; break;
1345 case ISD::SRL: Opc = Alpha::SRLi; break;
1346 case ISD::SRA: Opc = Alpha::SRAi; break;
1347 case ISD::MUL: Opc = Alpha::MULQi; break;
1349 Tmp1 = SelectExpr(N.getOperand(0));
1350 Tmp2 = cast<ConstantSDNode>(N.getOperand(1))->getValue();
1351 BuildMI(BB, Opc, 2, Result).addReg(Tmp1).addImm(Tmp2);
1354 case ISD::AND: Opc = Alpha::AND; break;
1355 case ISD::OR: Opc = Alpha::BIS; break;
1356 case ISD::XOR: Opc = Alpha::XOR; break;
1357 case ISD::SHL: Opc = Alpha::SL; break;
1358 case ISD::SRL: Opc = Alpha::SRL; break;
1359 case ISD::SRA: Opc = Alpha::SRA; break;
1360 case ISD::MUL: Opc = Alpha::MULQ; break;
1362 Tmp1 = SelectExpr(N.getOperand(0));
1363 Tmp2 = SelectExpr(N.getOperand(1));
1364 BuildMI(BB, Opc, 2, Result).addReg(Tmp1).addReg(Tmp2);
1371 bool isAdd = opcode == ISD::ADD;
1373 //FIXME: first check for Scaled Adds and Subs!
1374 if(N.getOperand(1).getOpcode() == ISD::Constant &&
1375 cast<ConstantSDNode>(N.getOperand(1))->getValue() <= 255)
1376 { //Normal imm add/sub
1377 Opc = isAdd ? Alpha::ADDQi : Alpha::SUBQi;
1378 Tmp1 = SelectExpr(N.getOperand(0));
1379 Tmp2 = cast<ConstantSDNode>(N.getOperand(1))->getValue();
1380 BuildMI(BB, Opc, 2, Result).addReg(Tmp1).addImm(Tmp2);
1382 else if(N.getOperand(1).getOpcode() == ISD::Constant &&
1383 (cast<ConstantSDNode>(N.getOperand(1))->getValue() <= 32767 ||
1384 (long)cast<ConstantSDNode>(N.getOperand(1))->getValue() >= -32767))
1386 Tmp1 = SelectExpr(N.getOperand(0));
1387 Tmp2 = (long)cast<ConstantSDNode>(N.getOperand(1))->getValue();
1390 BuildMI(BB, Alpha::LDA, 2, Result).addImm(Tmp2).addReg(Tmp1);
1393 Opc = isAdd ? Alpha::ADDQ : Alpha::SUBQ;
1394 Tmp1 = SelectExpr(N.getOperand(0));
1395 Tmp2 = SelectExpr(N.getOperand(1));
1396 BuildMI(BB, Opc, 2, Result).addReg(Tmp1).addReg(Tmp2);
1405 //FIXME: alpha really doesn't support any of these operations,
1406 // the ops are expanded into special library calls with
1407 // special calling conventions
1408 //Restore GP because it is a call after all...
1410 case ISD::UREM: Opc = Alpha::REMQU; break;
1411 case ISD::SREM: Opc = Alpha::REMQ; break;
1412 case ISD::UDIV: Opc = Alpha::DIVQU; break;
1413 case ISD::SDIV: Opc = Alpha::DIVQ; break;
1415 Tmp1 = SelectExpr(N.getOperand(0));
1416 Tmp2 = SelectExpr(N.getOperand(1));
1417 //set up regs explicitly (helps Reg alloc)
1418 BuildMI(BB, Alpha::BIS, 2, Alpha::R24).addReg(Tmp1).addReg(Tmp1);
1419 BuildMI(BB, Alpha::BIS, 2, Alpha::R25).addReg(Tmp2).addReg(Tmp2);
1420 AlphaLowering.restoreGP(BB);
1421 BuildMI(BB, Opc, 2).addReg(Alpha::R24).addReg(Alpha::R25);
1422 BuildMI(BB, Alpha::BIS, 2, Result).addReg(Alpha::R27).addReg(Alpha::R27);
1425 case ISD::FP_TO_UINT:
1426 case ISD::FP_TO_SINT:
1428 assert (DestType == MVT::i64 && "only quads can be loaded to");
1429 MVT::ValueType SrcType = N.getOperand(0).getValueType();
1430 assert (SrcType == MVT::f32 || SrcType == MVT::f64);
1431 Tmp1 = SelectExpr(N.getOperand(0)); // Get the operand register
1434 // Spill the integer to memory and reload it from there.
1435 unsigned Size = MVT::getSizeInBits(MVT::f64)/8;
1436 MachineFunction *F = BB->getParent();
1437 int FrameIdx = F->getFrameInfo()->CreateStackObject(Size, 8);
1440 //CVTST CVTTQ STT LDQ
1441 if (SrcType == MVT::f32)
1443 Tmp2 = MakeReg(MVT::f64);
1444 BuildMI(BB, Alpha::CVTST, 1, Tmp2).addReg(Tmp1);
1447 Tmp2 = MakeReg(MVT::f64);
1448 BuildMI(BB, Alpha::CVTTQ, 1, Tmp2).addReg(Tmp1);
1449 BuildMI(BB, Alpha::STT, 3).addReg(Tmp2).addFrameIndex(FrameIdx).addReg(Alpha::F31);
1450 BuildMI(BB, Alpha::LDQ, 2, Result).addFrameIndex(FrameIdx).addReg(Alpha::F31);
1455 // // case ISD::FP_TO_UINT:
1459 Tmp1 = SelectExpr(N.getOperand(0)); //Cond
1460 Tmp2 = SelectExpr(N.getOperand(1)); //Use if TRUE
1461 Tmp3 = SelectExpr(N.getOperand(2)); //Use if FALSE
1462 // Get the condition into the zero flag.
1463 BuildMI(BB, Alpha::CMOVEQ, 2, Result).addReg(Tmp2).addReg(Tmp3).addReg(Tmp1);
1469 int64_t val = (long)cast<ConstantSDNode>(N)->getValue();
1470 if (val <= IMM_HIGH && val >= IMM_LOW) {
1471 BuildMI(BB, Alpha::LDA, 2, Result).addImm(val).addReg(Alpha::R31);
1473 else if (val <= (int64_t)IMM_HIGH + (int64_t)IMM_HIGH * (int64_t)IMM_MULT &&
1474 val >= (int64_t)IMM_LOW + (int64_t)IMM_LOW * (int64_t)IMM_MULT) {
1475 Tmp1 = MakeReg(MVT::i64);
1476 BuildMI(BB, Alpha::LDAH, 2, Tmp1).addImm(getUpper16(val)).addReg(Alpha::R31);
1477 BuildMI(BB, Alpha::LDA, 2, Result).addImm(getLower16(val)).addReg(Tmp1);
1480 MachineConstantPool *CP = BB->getParent()->getConstantPool();
1481 ConstantUInt *C = ConstantUInt::get(Type::getPrimitiveType(Type::ULongTyID) , val);
1482 unsigned CPI = CP->getConstantPoolIndex(C);
1483 AlphaLowering.restoreGP(BB);
1484 BuildMI(BB, Alpha::LDQ_SYM, 1, Result).addConstantPoolIndex(CPI);
1493 void ISel::Select(SDOperand N) {
1494 unsigned Tmp1, Tmp2, Opc;
1495 unsigned opcode = N.getOpcode();
1497 // FIXME: Disable for our current expansion model!
1498 if (/*!N->hasOneUse() &&*/ !ExprMap.insert(std::make_pair(N, notIn)).second)
1499 return; // Already selected.
1501 SDNode *Node = N.Val;
1506 Node->dump(); std::cerr << "\n";
1507 assert(0 && "Node not handled yet!");
1515 MachineBasicBlock *Dest =
1516 cast<BasicBlockSDNode>(N.getOperand(1))->getBasicBlock();
1518 Select(N.getOperand(0));
1519 BuildMI(BB, Alpha::BR, 1, Alpha::R31).addMBB(Dest);
1523 case ISD::ImplicitDef:
1524 Select(N.getOperand(0));
1525 BuildMI(BB, Alpha::IDEF, 0, cast<RegSDNode>(N)->getReg());
1528 case ISD::EntryToken: return; // Noop
1530 case ISD::TokenFactor:
1531 for (unsigned i = 0, e = Node->getNumOperands(); i != e; ++i)
1532 Select(Node->getOperand(i));
1534 //N.Val->dump(); std::cerr << "\n";
1535 //assert(0 && "Node not handled yet!");
1539 case ISD::CopyToReg:
1540 Select(N.getOperand(0));
1541 Tmp1 = SelectExpr(N.getOperand(1));
1542 Tmp2 = cast<RegSDNode>(N)->getReg();
1545 if (N.getOperand(1).getValueType() == MVT::f64 ||
1546 N.getOperand(1).getValueType() == MVT::f32)
1547 BuildMI(BB, Alpha::CPYS, 2, Tmp2).addReg(Tmp1).addReg(Tmp1);
1549 BuildMI(BB, Alpha::BIS, 2, Tmp2).addReg(Tmp1).addReg(Tmp1);
1554 switch (N.getNumOperands()) {
1556 std::cerr << N.getNumOperands() << "\n";
1557 for (unsigned i = 0; i < N.getNumOperands(); ++i)
1558 std::cerr << N.getOperand(i).getValueType() << "\n";
1560 assert(0 && "Unknown return instruction!");
1562 Select(N.getOperand(0));
1563 Tmp1 = SelectExpr(N.getOperand(1));
1564 switch (N.getOperand(1).getValueType()) {
1565 default: Node->dump();
1566 assert(0 && "All other types should have been promoted!!");
1569 BuildMI(BB, Alpha::CPYS, 2, Alpha::F0).addReg(Tmp1).addReg(Tmp1);
1573 BuildMI(BB, Alpha::BIS, 2, Alpha::R0).addReg(Tmp1).addReg(Tmp1);
1578 Select(N.getOperand(0));
1581 //Tmp2 = AlphaLowering.getRetAddr();
1582 //BuildMI(BB, Alpha::BIS, 2, Alpha::R26).addReg(Tmp2).addReg(Tmp2);
1583 BuildMI(BB, Alpha::RETURN, 0); // Just emit a 'ret' instruction
1586 case ISD::TRUNCSTORE:
1589 SDOperand Chain = N.getOperand(0);
1590 SDOperand Value = N.getOperand(1);
1591 SDOperand Address = N.getOperand(2);
1594 Tmp1 = SelectExpr(Value); //value
1596 if (opcode == ISD::STORE) {
1597 switch(Value.getValueType()) {
1598 default: assert(0 && "unknown Type in store");
1599 case MVT::i64: Opc = Alpha::STQ; break;
1600 case MVT::f64: Opc = Alpha::STT; break;
1601 case MVT::f32: Opc = Alpha::STS; break;
1603 } else { //ISD::TRUNCSTORE
1604 switch(cast<MVTSDNode>(Node)->getExtraValueType()) {
1605 default: assert(0 && "unknown Type in store");
1606 case MVT::i1: //FIXME: DAG does not promote this load
1607 case MVT::i8: Opc = Alpha::STB; break;
1608 case MVT::i16: Opc = Alpha::STW; break;
1609 case MVT::i32: Opc = Alpha::STL; break;
1613 if (Address.getOpcode() == ISD::GlobalAddress)
1615 AlphaLowering.restoreGP(BB);
1616 Opc = GetSymVersion(Opc);
1617 BuildMI(BB, Opc, 2).addReg(Tmp1).addGlobalAddress(cast<GlobalAddressSDNode>(Address)->getGlobal());
1619 else if(Address.getOpcode() == ISD::FrameIndex)
1621 BuildMI(BB, Opc, 3).addReg(Tmp1)
1622 .addFrameIndex(cast<FrameIndexSDNode>(Address)->getIndex())
1623 .addReg(Alpha::F31);
1628 SelectAddr(Address, Tmp2, offset);
1629 BuildMI(BB, Opc, 3).addReg(Tmp1).addImm(offset).addReg(Tmp2);
1638 case ISD::CopyFromReg:
1640 case ISD::DYNAMIC_STACKALLOC:
1645 case ISD::ADJCALLSTACKDOWN:
1646 case ISD::ADJCALLSTACKUP:
1647 Select(N.getOperand(0));
1648 Tmp1 = cast<ConstantSDNode>(N.getOperand(1))->getValue();
1650 Opc = N.getOpcode() == ISD::ADJCALLSTACKDOWN ? Alpha::ADJUSTSTACKDOWN :
1651 Alpha::ADJUSTSTACKUP;
1652 BuildMI(BB, Opc, 1).addImm(Tmp1);
1655 assert(0 && "Should not be reached!");
1659 /// createAlphaPatternInstructionSelector - This pass converts an LLVM function
1660 /// into a machine code representation using pattern matching and a machine
1661 /// description file.
1663 FunctionPass *llvm::createAlphaPatternInstructionSelector(TargetMachine &TM) {
1664 return new ISel(TM);