1 //===- AlphaInstrFormats.td - Alpha Instruction Formats ----*- tablegen -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file was developed by the LLVM research group and is distributed under
6 // the University of Illinois Open Source License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
11 //===----------------------------------------------------------------------===//
20 def u8imm : Operand<i64>;
21 def s14imm : Operand<i64>;
22 def s16imm : Operand<i64>;
23 def s21imm : Operand<i64>;
24 def s64imm : Operand<i64>;
25 def u64imm : Operand<i64>;
27 //===----------------------------------------------------------------------===//
28 // Instruction format superclass
29 //===----------------------------------------------------------------------===//
30 // Alpha instruction baseline
31 class InstAlpha<bits<6> op, string asmstr, InstrItinClass itin> : Instruction {
33 let Namespace = "Alpha";
34 let AsmString = asmstr;
41 class MForm<bits<6> opcode, bit store, bit load, string asmstr, list<dag> pattern, InstrItinClass itin>
42 : InstAlpha<opcode, asmstr, itin> {
43 let Pattern = pattern;
46 let Defs = [R28]; //We may use this for frame index calculations, so reserve it here
54 let Inst{15-0} = disp;
56 class MfcForm<bits<6> opcode, bits<16> fc, string asmstr, InstrItinClass itin>
57 : InstAlpha<opcode, asmstr, itin> {
60 let OperandList = (ops GPRC:$RA);
66 class MbrForm<bits<6> opcode, bits<2> TB, dag OL, string asmstr, InstrItinClass itin>
67 : InstAlpha<opcode, asmstr, itin> {
77 let Inst{13-0} = disp;
79 class MbrpForm<bits<6> opcode, bits<2> TB, dag OL, string asmstr, list<dag> pattern, InstrItinClass itin>
80 : InstAlpha<opcode, asmstr, itin> {
91 let Inst{13-0} = disp;
95 def target : Operand<OtherVT> {}
97 let isBranch = 1, isTerminator = 1, hasCtrlDep = 1, noResults = 1 in {
98 class BFormN<bits<6> opcode, dag OL, string asmstr, InstrItinClass itin>
99 : InstAlpha<opcode, asmstr, itin> {
100 let OperandList = OL;
101 bits<64> Opc; //dummy
105 let Inst{25-21} = Ra;
106 let Inst{20-0} = disp;
110 let isBranch = 1, isTerminator = 1 in
111 class BFormD<bits<6> opcode, string asmstr, list<dag> pattern, InstrItinClass itin>
112 : InstAlpha<opcode, asmstr, itin> {
113 let Pattern = pattern;
114 let OperandList = (ops target:$DISP);
118 let Inst{25-21} = Ra;
119 let Inst{20-0} = disp;
123 class OForm<bits<6> opcode, bits<7> fun, string asmstr, list<dag> pattern, InstrItinClass itin>
124 : InstAlpha<opcode, asmstr, itin> {
125 let Pattern = pattern;
126 let OperandList = (ops GPRC:$RC, GPRC:$RA, GPRC:$RB);
131 bits<7> Function = fun;
133 let Inst{25-21} = Ra;
134 let Inst{20-16} = Rb;
137 let Inst{11-5} = Function;
141 class OForm2<bits<6> opcode, bits<7> fun, string asmstr, list<dag> pattern, InstrItinClass itin>
142 : InstAlpha<opcode, asmstr, itin> {
143 let Pattern = pattern;
144 let OperandList = (ops GPRC:$RC, GPRC:$RB);
148 bits<7> Function = fun;
150 let Inst{25-21} = 31;
151 let Inst{20-16} = Rb;
154 let Inst{11-5} = Function;
158 class OForm4<bits<6> opcode, bits<7> fun, string asmstr, list<dag> pattern, InstrItinClass itin>
159 : InstAlpha<opcode, asmstr, itin> {
160 let Pattern = pattern;
161 let OperandList = (ops GPRC:$RDEST, GPRC:$RCOND, GPRC:$RTRUE, GPRC:$RFALSE);
162 let Constraints = "$RFALSE = $RDEST";
163 let DisableEncoding = "$RFALSE";
168 bits<7> Function = fun;
170 // let isTwoAddress = 1;
171 let Inst{25-21} = Ra;
172 let Inst{20-16} = Rb;
175 let Inst{11-5} = Function;
180 class OFormL<bits<6> opcode, bits<7> fun, string asmstr, list<dag> pattern, InstrItinClass itin>
181 : InstAlpha<opcode, asmstr, itin> {
182 let Pattern = pattern;
183 let OperandList = (ops GPRC:$RC, GPRC:$RA, u8imm:$L);
188 bits<7> Function = fun;
190 let Inst{25-21} = Ra;
191 let Inst{20-13} = LIT;
193 let Inst{11-5} = Function;
197 class OForm4L<bits<6> opcode, bits<7> fun, string asmstr, list<dag> pattern, InstrItinClass itin>
198 : InstAlpha<opcode, asmstr, itin> {
199 let Pattern = pattern;
200 let OperandList = (ops GPRC:$RDEST, GPRC:$RCOND, s64imm:$RTRUE, GPRC:$RFALSE);
201 let Constraints = "$RFALSE = $RDEST";
202 let DisableEncoding = "$RFALSE";
207 bits<7> Function = fun;
209 // let isTwoAddress = 1;
210 let Inst{25-21} = Ra;
211 let Inst{20-13} = LIT;
213 let Inst{11-5} = Function;
218 class FPForm<bits<6> opcode, bits<11> fun, string asmstr, list<dag> pattern, InstrItinClass itin>
219 : InstAlpha<opcode, asmstr, itin> {
220 let Pattern = pattern;
225 bits<11> Function = fun;
227 let Inst{25-21} = Fa;
228 let Inst{20-16} = Fb;
229 let Inst{15-5} = Function;
234 class PALForm<bits<6> opcode, dag OL, string asmstr, InstrItinClass itin>
235 : InstAlpha<opcode, asmstr, itin> {
236 let OperandList = OL;
239 let Inst{25-0} = Function;
243 // Pseudo instructions.
244 class PseudoInstAlpha<dag OL, string nm, list<dag> pattern, InstrItinClass itin>
245 : InstAlpha<0, nm, itin> {
246 let OperandList = OL;
247 let Pattern = pattern;