1 //===- AlphaInstrFormats.td - Alpha Instruction Formats ----*- tablegen -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file was developed by the LLVM research group and is distributed under
6 // the University of Illinois Open Source License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
11 //===----------------------------------------------------------------------===//
20 def u8imm : Operand<i64>;
21 def s14imm : Operand<i64>;
22 def s16imm : Operand<i64>;
23 def s21imm : Operand<i64>;
24 def s64imm : Operand<i64>;
26 //===----------------------------------------------------------------------===//
27 // Instruction format superclass
28 //===----------------------------------------------------------------------===//
29 // Alpha instruction baseline
30 class InstAlphaAlt<bits<6> op, string asmstr> : Instruction {
32 let Namespace = "Alpha";
33 let AsmString = asmstr;
37 class InstAlpha<bits<6> op, dag OL, string asmstr>
38 : InstAlphaAlt<op, asmstr> { // Alpha instruction baseline
43 class MForm<bits<6> opcode, string asmstr>
44 : InstAlpha<opcode, (ops GPRC:$RA, s16imm:$DISP, GPRC:$RB), asmstr> {
51 let Inst{15-0} = disp;
53 class MfcForm<bits<6> opcode, bits<16> fc, string asmstr>
54 : InstAlpha<opcode, (ops GPRC:$RA, GPRC:$RB), asmstr> {
63 class MgForm<bits<6> opcode, string asmstr>
64 : InstAlpha<opcode, (ops GPRC:$RA, s16imm:$DISP, GPRC:$RB, s16imm:$NUM), asmstr> {
71 let Inst{15-0} = disp;
74 class MbrForm<bits<6> opcode, bits<2> TB, dag OL, string asmstr> : InstAlpha<opcode, OL, asmstr> {
82 let Inst{13-0} = disp;
86 let isBranch = 1, isTerminator = 1 in
87 class BForm<bits<6> opcode, string asmstr>
88 : InstAlpha<opcode, (ops GPRC:$RA, s21imm:$DISP), asmstr> {
93 let Inst{20-0} = disp;
95 class BFormD<bits<6> opcode, string asmstr>
96 : InstAlpha<opcode, (ops s21imm:$DISP), asmstr> {
100 let Inst{25-21} = Ra;
101 let Inst{20-0} = disp;
104 let isBranch = 1, isTerminator = 1 in
105 class FBForm<bits<6> opcode, string asmstr>
106 : InstAlpha<opcode, (ops F8RC:$RA, s21imm:$DISP), asmstr> {
110 let Inst{25-21} = Ra;
111 let Inst{20-0} = disp;
115 class OForm<bits<6> opcode, bits<7> fun, string asmstr, list<dag> pattern>
116 : InstAlpha<opcode, (ops GPRC:$RC, GPRC:$RA, GPRC:$RB), asmstr> {
117 let Pattern = pattern;
122 bits<7> Function = fun;
124 let Inst{25-21} = Ra;
125 let Inst{20-16} = Rb;
128 let Inst{11-5} = Function;
132 class OForm2<bits<6> opcode, bits<7> fun, string asmstr, list<dag> pattern>
133 : InstAlpha<opcode, (ops GPRC:$RC, GPRC:$RB), asmstr> {
134 let Pattern = pattern;
138 bits<7> Function = fun;
140 let Inst{25-21} = 31;
141 let Inst{20-16} = Rb;
144 let Inst{11-5} = Function;
148 class OForm4<bits<6> opcode, bits<7> fun, string asmstr>
149 : InstAlpha<opcode, (ops GPRC:$RDEST, GPRC:$RSRC2, GPRC:$RSRC, GPRC:$RCOND), asmstr> {
153 bits<7> Function = fun;
155 let isTwoAddress = 1;
156 let Inst{25-21} = Ra;
157 let Inst{20-16} = Rb;
160 let Inst{11-5} = Function;
165 class OFormL<bits<6> opcode, bits<7> fun, string asmstr, list<dag> pattern>
166 : InstAlpha<opcode, (ops GPRC:$RC, GPRC:$RA, u8imm:$L), asmstr> {
167 let Pattern = pattern;
172 bits<7> Function = fun;
174 let Inst{25-21} = Ra;
175 let Inst{20-13} = LIT;
177 let Inst{11-5} = Function;
181 class OForm4L<bits<6> opcode, bits<7> fun, string asmstr>
182 : InstAlpha<opcode, (ops GPRC:$RDEST, GPRC:$RSRC2, u8imm:$L, GPRC:$RCOND), asmstr> {
186 bits<7> Function = fun;
188 let isTwoAddress = 1;
189 let Inst{25-21} = Ra;
190 let Inst{20-13} = LIT;
192 let Inst{11-5} = Function;
197 class FPForm<bits<6> opcode, bits<11> fun, string asmstr, list<dag> pattern>
198 : InstAlphaAlt<opcode, asmstr> {
199 let Pattern = pattern;
204 bits<11> Function = fun;
206 let Inst{25-21} = Fa;
207 let Inst{20-16} = Fb;
208 let Inst{15-5} = Function;
213 class PALForm<bits<6> opcode, dag OL, string asmstr> : InstAlpha<opcode, OL, asmstr> {
216 let Inst{25-0} = Function;
220 // Pseudo instructions.
221 class PseudoInstAlpha<dag OL, string nm> : InstAlpha<0, OL, nm> {