1 //===- AlphaInstrFormats.td - Alpha Instruction Formats ----*- tablegen -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file was developed by the LLVM research group and is distributed under
6 // the University of Illinois Open Source License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
11 //===----------------------------------------------------------------------===//
20 def u8imm : Operand<i8>;
21 def s14imm : Operand<i16>;
22 def s16imm : Operand<i16>;
23 def s21imm : Operand<i32>;
24 def s64imm : Operand<i64>;
26 //===----------------------------------------------------------------------===//
27 // Instruction format superclass
28 //===----------------------------------------------------------------------===//
30 class InstAlpha<bits<6> op, dag OL, string asmstr> : Instruction { // Alpha instruction baseline
32 let Namespace = "Alpha";
34 let AsmString = asmstr;
41 class MForm<bits<6> opcode, string asmstr>
42 : InstAlpha<opcode, (ops GPRC:$RA, s16imm:$DISP, GPRC:$RB), asmstr> {
49 let Inst{15-0} = disp;
52 class MgForm<bits<6> opcode, string asmstr>
53 : InstAlpha<opcode, (ops GPRC:$RA, s16imm:$DISP, GPRC:$RB, s16imm:$NUM), asmstr> {
60 let Inst{15-0} = disp;
63 class MbrForm<bits<6> opcode, bits<2> TB, dag OL, string asmstr> : InstAlpha<opcode, OL, asmstr> {
71 let Inst{13-0} = disp;
75 let isBranch = 1, isTerminator = 1 in
76 class BForm<bits<6> opcode, string asmstr>
77 : InstAlpha<opcode, (ops GPRC:$RA, s21imm:$DISP), asmstr> {
82 let Inst{20-0} = disp;
85 let isBranch = 1, isTerminator = 1 in
86 class FBForm<bits<6> opcode, string asmstr>
87 : InstAlpha<opcode, (ops FPRC:$RA, s21imm:$DISP), asmstr> {
92 let Inst{20-0} = disp;
96 class OForm<bits<6> opcode, bits<7> fun, string asmstr>
97 : InstAlpha<opcode, (ops GPRC:$RC, GPRC:$RA, GPRC:$RB), asmstr> {
101 bits<7> Function = fun;
103 let Inst{25-21} = Ra;
104 let Inst{20-16} = Rb;
107 let Inst{11-5} = Function;
111 class OcmForm<bits<6> opcode, bits<7> fun, dag OL, string asmstr>
112 : InstAlpha<opcode, OL, asmstr> {
115 bits<7> Function = fun;
118 let Inst{25-21} = Ra;
119 let Inst{20-16} = Rb;
122 let Inst{11-5} = Function;
127 class OFormL<bits<6> opcode, bits<7> fun, string asmstr>
128 : InstAlpha<opcode, (ops GPRC:$RC, GPRC:$RA, u8imm:$L), asmstr> {
132 bits<7> Function = fun;
134 let Inst{25-21} = Ra;
135 let Inst{20-13} = LIT;
137 let Inst{11-5} = Function;
141 class OcmFormL<bits<6> opcode, bits<7> fun, dag OL, string asmstr>
142 : InstAlpha<opcode, OL, asmstr> {
145 bits<7> Function = fun;
148 let Inst{25-21} = Ra;
149 let Inst{20-13} = LIT;
151 let Inst{11-5} = Function;
156 class FPForm<bits<6> opcode, bits<11> fun, dag OL, string asmstr> : InstAlpha<opcode, OL, asmstr> {
159 bits<11> Function = fun;
162 let Inst{25-21} = Fa;
163 let Inst{20-16} = Fb;
164 let Inst{15-5} = Function;
169 class PALForm<bits<6> opcode, dag OL, string asmstr> : InstAlpha<opcode, OL, asmstr> {
172 let Inst{25-0} = Function;
176 // Pseudo instructions.
177 class PseudoInstAlpha<dag OL, string nm> : InstAlpha<0, OL, nm> {