1 //===- AlphaInstrFormats.td - Alpha Instruction Formats ----*- tablegen -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file was developed by the LLVM research group and is distributed under
6 // the University of Illinois Open Source License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
11 //===----------------------------------------------------------------------===//
20 def u8imm : Operand<i64>;
21 def s14imm : Operand<i64>;
22 def s16imm : Operand<i64>;
23 def s21imm : Operand<i64>;
24 def s64imm : Operand<i64>;
26 //===----------------------------------------------------------------------===//
27 // Instruction format superclass
28 //===----------------------------------------------------------------------===//
29 // Alpha instruction baseline
30 class InstAlphaAlt<bits<6> op, string asmstr> : Instruction {
32 let Namespace = "Alpha";
33 let AsmString = asmstr;
37 class InstAlpha<bits<6> op, dag OL, string asmstr>
38 : InstAlphaAlt<op, asmstr> { // Alpha instruction baseline
43 class MForm<bits<6> opcode, string asmstr>
44 : InstAlpha<opcode, (ops GPRC:$RA, s16imm:$DISP, GPRC:$RB), asmstr> {
51 let Inst{15-0} = disp;
54 class MgForm<bits<6> opcode, string asmstr>
55 : InstAlpha<opcode, (ops GPRC:$RA, s16imm:$DISP, GPRC:$RB, s16imm:$NUM), asmstr> {
62 let Inst{15-0} = disp;
65 class MbrForm<bits<6> opcode, bits<2> TB, dag OL, string asmstr> : InstAlpha<opcode, OL, asmstr> {
73 let Inst{13-0} = disp;
77 let isBranch = 1, isTerminator = 1 in
78 class BForm<bits<6> opcode, string asmstr>
79 : InstAlpha<opcode, (ops GPRC:$RA, s21imm:$DISP), asmstr> {
84 let Inst{20-0} = disp;
86 class BFormD<bits<6> opcode, string asmstr>
87 : InstAlpha<opcode, (ops s21imm:$DISP), asmstr> {
92 let Inst{20-0} = disp;
95 let isBranch = 1, isTerminator = 1 in
96 class FBForm<bits<6> opcode, string asmstr>
97 : InstAlpha<opcode, (ops F8RC:$RA, s21imm:$DISP), asmstr> {
101 let Inst{25-21} = Ra;
102 let Inst{20-0} = disp;
106 class OForm<bits<6> opcode, bits<7> fun, string asmstr, list<dag> pattern>
107 : InstAlpha<opcode, (ops GPRC:$RC, GPRC:$RA, GPRC:$RB), asmstr> {
108 let Pattern = pattern;
113 bits<7> Function = fun;
115 let Inst{25-21} = Ra;
116 let Inst{20-16} = Rb;
119 let Inst{11-5} = Function;
123 class OForm2<bits<6> opcode, bits<7> fun, string asmstr, list<dag> pattern>
124 : InstAlpha<opcode, (ops GPRC:$RC, GPRC:$RB), asmstr> {
125 let Pattern = pattern;
129 bits<7> Function = fun;
131 let Inst{25-21} = 31;
132 let Inst{20-16} = Rb;
135 let Inst{11-5} = Function;
139 class OForm4<bits<6> opcode, bits<7> fun, string asmstr>
140 : InstAlpha<opcode, (ops GPRC:$RDEST, GPRC:$RSRC2, GPRC:$RSRC, GPRC:$RCOND), asmstr> {
144 bits<7> Function = fun;
146 let isTwoAddress = 1;
147 let Inst{25-21} = Ra;
148 let Inst{20-16} = Rb;
151 let Inst{11-5} = Function;
156 class OFormL<bits<6> opcode, bits<7> fun, string asmstr, list<dag> pattern>
157 : InstAlpha<opcode, (ops GPRC:$RC, GPRC:$RA, u8imm:$L), asmstr> {
158 let Pattern = pattern;
163 bits<7> Function = fun;
165 let Inst{25-21} = Ra;
166 let Inst{20-13} = LIT;
168 let Inst{11-5} = Function;
172 class OForm4L<bits<6> opcode, bits<7> fun, string asmstr>
173 : InstAlpha<opcode, (ops GPRC:$RDEST, GPRC:$RSRC2, u8imm:$L, GPRC:$RCOND), asmstr> {
177 bits<7> Function = fun;
179 let isTwoAddress = 1;
180 let Inst{25-21} = Ra;
181 let Inst{20-13} = LIT;
183 let Inst{11-5} = Function;
188 class FPForm<bits<6> opcode, bits<11> fun, string asmstr, list<dag> pattern>
189 : InstAlphaAlt<opcode, asmstr> {
190 let Pattern = pattern;
195 bits<11> Function = fun;
197 let Inst{25-21} = Fa;
198 let Inst{20-16} = Fb;
199 let Inst{15-5} = Function;
204 class PALForm<bits<6> opcode, dag OL, string asmstr> : InstAlpha<opcode, OL, asmstr> {
207 let Inst{25-0} = Function;
211 // Pseudo instructions.
212 class PseudoInstAlpha<dag OL, string nm> : InstAlpha<0, OL, nm> {