1 //===- AlphaInstrInfo.cpp - Alpha Instruction Information -------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains the Alpha implementation of the TargetInstrInfo class.
12 //===----------------------------------------------------------------------===//
15 #include "AlphaInstrInfo.h"
16 #include "AlphaMachineFunctionInfo.h"
17 #include "llvm/CodeGen/MachineRegisterInfo.h"
18 #include "llvm/ADT/STLExtras.h"
19 #include "llvm/ADT/SmallVector.h"
20 #include "llvm/CodeGen/MachineInstrBuilder.h"
21 #include "llvm/Support/ErrorHandling.h"
23 #define GET_INSTRINFO_MC_DESC
24 #include "AlphaGenInstrInfo.inc"
27 AlphaInstrInfo::AlphaInstrInfo()
28 : TargetInstrInfoImpl(AlphaInsts, array_lengthof(AlphaInsts),
29 Alpha::ADJUSTSTACKDOWN, Alpha::ADJUSTSTACKUP),
34 AlphaInstrInfo::isLoadFromStackSlot(const MachineInstr *MI,
35 int &FrameIndex) const {
36 switch (MI->getOpcode()) {
43 if (MI->getOperand(1).isFI()) {
44 FrameIndex = MI->getOperand(1).getIndex();
45 return MI->getOperand(0).getReg();
53 AlphaInstrInfo::isStoreToStackSlot(const MachineInstr *MI,
54 int &FrameIndex) const {
55 switch (MI->getOpcode()) {
62 if (MI->getOperand(1).isFI()) {
63 FrameIndex = MI->getOperand(1).getIndex();
64 return MI->getOperand(0).getReg();
71 static bool isAlphaIntCondCode(unsigned Opcode) {
87 unsigned AlphaInstrInfo::InsertBranch(MachineBasicBlock &MBB,
88 MachineBasicBlock *TBB,
89 MachineBasicBlock *FBB,
90 const SmallVectorImpl<MachineOperand> &Cond,
92 assert(TBB && "InsertBranch must not be told to insert a fallthrough");
93 assert((Cond.size() == 2 || Cond.size() == 0) &&
94 "Alpha branch conditions have two components!");
98 if (Cond.empty()) // Unconditional branch
99 BuildMI(&MBB, DL, get(Alpha::BR)).addMBB(TBB);
100 else // Conditional branch
101 if (isAlphaIntCondCode(Cond[0].getImm()))
102 BuildMI(&MBB, DL, get(Alpha::COND_BRANCH_I))
103 .addImm(Cond[0].getImm()).addReg(Cond[1].getReg()).addMBB(TBB);
105 BuildMI(&MBB, DL, get(Alpha::COND_BRANCH_F))
106 .addImm(Cond[0].getImm()).addReg(Cond[1].getReg()).addMBB(TBB);
110 // Two-way Conditional Branch.
111 if (isAlphaIntCondCode(Cond[0].getImm()))
112 BuildMI(&MBB, DL, get(Alpha::COND_BRANCH_I))
113 .addImm(Cond[0].getImm()).addReg(Cond[1].getReg()).addMBB(TBB);
115 BuildMI(&MBB, DL, get(Alpha::COND_BRANCH_F))
116 .addImm(Cond[0].getImm()).addReg(Cond[1].getReg()).addMBB(TBB);
117 BuildMI(&MBB, DL, get(Alpha::BR)).addMBB(FBB);
121 void AlphaInstrInfo::copyPhysReg(MachineBasicBlock &MBB,
122 MachineBasicBlock::iterator MI, DebugLoc DL,
123 unsigned DestReg, unsigned SrcReg,
124 bool KillSrc) const {
125 if (Alpha::GPRCRegClass.contains(DestReg, SrcReg)) {
126 BuildMI(MBB, MI, DL, get(Alpha::BISr), DestReg)
128 .addReg(SrcReg, getKillRegState(KillSrc));
129 } else if (Alpha::F4RCRegClass.contains(DestReg, SrcReg)) {
130 BuildMI(MBB, MI, DL, get(Alpha::CPYSS), DestReg)
132 .addReg(SrcReg, getKillRegState(KillSrc));
133 } else if (Alpha::F8RCRegClass.contains(DestReg, SrcReg)) {
134 BuildMI(MBB, MI, DL, get(Alpha::CPYST), DestReg)
136 .addReg(SrcReg, getKillRegState(KillSrc));
138 llvm_unreachable("Attempt to copy register that is not GPR or FPR");
143 AlphaInstrInfo::storeRegToStackSlot(MachineBasicBlock &MBB,
144 MachineBasicBlock::iterator MI,
145 unsigned SrcReg, bool isKill, int FrameIdx,
146 const TargetRegisterClass *RC,
147 const TargetRegisterInfo *TRI) const {
148 //cerr << "Trying to store " << getPrettyName(SrcReg) << " to "
149 // << FrameIdx << "\n";
150 //BuildMI(MBB, MI, Alpha::WTF, 0).addReg(SrcReg);
153 if (MI != MBB.end()) DL = MI->getDebugLoc();
155 if (RC == Alpha::F4RCRegisterClass)
156 BuildMI(MBB, MI, DL, get(Alpha::STS))
157 .addReg(SrcReg, getKillRegState(isKill))
158 .addFrameIndex(FrameIdx).addReg(Alpha::F31);
159 else if (RC == Alpha::F8RCRegisterClass)
160 BuildMI(MBB, MI, DL, get(Alpha::STT))
161 .addReg(SrcReg, getKillRegState(isKill))
162 .addFrameIndex(FrameIdx).addReg(Alpha::F31);
163 else if (RC == Alpha::GPRCRegisterClass)
164 BuildMI(MBB, MI, DL, get(Alpha::STQ))
165 .addReg(SrcReg, getKillRegState(isKill))
166 .addFrameIndex(FrameIdx).addReg(Alpha::F31);
168 llvm_unreachable("Unhandled register class");
172 AlphaInstrInfo::loadRegFromStackSlot(MachineBasicBlock &MBB,
173 MachineBasicBlock::iterator MI,
174 unsigned DestReg, int FrameIdx,
175 const TargetRegisterClass *RC,
176 const TargetRegisterInfo *TRI) const {
177 //cerr << "Trying to load " << getPrettyName(DestReg) << " to "
178 // << FrameIdx << "\n";
180 if (MI != MBB.end()) DL = MI->getDebugLoc();
182 if (RC == Alpha::F4RCRegisterClass)
183 BuildMI(MBB, MI, DL, get(Alpha::LDS), DestReg)
184 .addFrameIndex(FrameIdx).addReg(Alpha::F31);
185 else if (RC == Alpha::F8RCRegisterClass)
186 BuildMI(MBB, MI, DL, get(Alpha::LDT), DestReg)
187 .addFrameIndex(FrameIdx).addReg(Alpha::F31);
188 else if (RC == Alpha::GPRCRegisterClass)
189 BuildMI(MBB, MI, DL, get(Alpha::LDQ), DestReg)
190 .addFrameIndex(FrameIdx).addReg(Alpha::F31);
192 llvm_unreachable("Unhandled register class");
195 static unsigned AlphaRevCondCode(unsigned Opcode) {
197 case Alpha::BEQ: return Alpha::BNE;
198 case Alpha::BNE: return Alpha::BEQ;
199 case Alpha::BGE: return Alpha::BLT;
200 case Alpha::BGT: return Alpha::BLE;
201 case Alpha::BLE: return Alpha::BGT;
202 case Alpha::BLT: return Alpha::BGE;
203 case Alpha::BLBC: return Alpha::BLBS;
204 case Alpha::BLBS: return Alpha::BLBC;
205 case Alpha::FBEQ: return Alpha::FBNE;
206 case Alpha::FBNE: return Alpha::FBEQ;
207 case Alpha::FBGE: return Alpha::FBLT;
208 case Alpha::FBGT: return Alpha::FBLE;
209 case Alpha::FBLE: return Alpha::FBGT;
210 case Alpha::FBLT: return Alpha::FBGE;
212 llvm_unreachable("Unknown opcode");
214 return 0; // Not reached
218 bool AlphaInstrInfo::AnalyzeBranch(MachineBasicBlock &MBB,MachineBasicBlock *&TBB,
219 MachineBasicBlock *&FBB,
220 SmallVectorImpl<MachineOperand> &Cond,
221 bool AllowModify) const {
222 // If the block has no terminators, it just falls into the block after it.
223 MachineBasicBlock::iterator I = MBB.end();
224 if (I == MBB.begin())
227 while (I->isDebugValue()) {
228 if (I == MBB.begin())
232 if (!isUnpredicatedTerminator(I))
235 // Get the last instruction in the block.
236 MachineInstr *LastInst = I;
238 // If there is only one terminator instruction, process it.
239 if (I == MBB.begin() || !isUnpredicatedTerminator(--I)) {
240 if (LastInst->getOpcode() == Alpha::BR) {
241 TBB = LastInst->getOperand(0).getMBB();
243 } else if (LastInst->getOpcode() == Alpha::COND_BRANCH_I ||
244 LastInst->getOpcode() == Alpha::COND_BRANCH_F) {
245 // Block ends with fall-through condbranch.
246 TBB = LastInst->getOperand(2).getMBB();
247 Cond.push_back(LastInst->getOperand(0));
248 Cond.push_back(LastInst->getOperand(1));
251 // Otherwise, don't know what this is.
255 // Get the instruction before it if it's a terminator.
256 MachineInstr *SecondLastInst = I;
258 // If there are three terminators, we don't know what sort of block this is.
259 if (SecondLastInst && I != MBB.begin() &&
260 isUnpredicatedTerminator(--I))
263 // If the block ends with Alpha::BR and Alpha::COND_BRANCH_*, handle it.
264 if ((SecondLastInst->getOpcode() == Alpha::COND_BRANCH_I ||
265 SecondLastInst->getOpcode() == Alpha::COND_BRANCH_F) &&
266 LastInst->getOpcode() == Alpha::BR) {
267 TBB = SecondLastInst->getOperand(2).getMBB();
268 Cond.push_back(SecondLastInst->getOperand(0));
269 Cond.push_back(SecondLastInst->getOperand(1));
270 FBB = LastInst->getOperand(0).getMBB();
274 // If the block ends with two Alpha::BRs, handle it. The second one is not
275 // executed, so remove it.
276 if (SecondLastInst->getOpcode() == Alpha::BR &&
277 LastInst->getOpcode() == Alpha::BR) {
278 TBB = SecondLastInst->getOperand(0).getMBB();
281 I->eraseFromParent();
285 // Otherwise, can't handle this.
289 unsigned AlphaInstrInfo::RemoveBranch(MachineBasicBlock &MBB) const {
290 MachineBasicBlock::iterator I = MBB.end();
291 if (I == MBB.begin()) return 0;
293 while (I->isDebugValue()) {
294 if (I == MBB.begin())
298 if (I->getOpcode() != Alpha::BR &&
299 I->getOpcode() != Alpha::COND_BRANCH_I &&
300 I->getOpcode() != Alpha::COND_BRANCH_F)
303 // Remove the branch.
304 I->eraseFromParent();
308 if (I == MBB.begin()) return 1;
310 if (I->getOpcode() != Alpha::COND_BRANCH_I &&
311 I->getOpcode() != Alpha::COND_BRANCH_F)
314 // Remove the branch.
315 I->eraseFromParent();
319 void AlphaInstrInfo::insertNoop(MachineBasicBlock &MBB,
320 MachineBasicBlock::iterator MI) const {
322 BuildMI(MBB, MI, DL, get(Alpha::BISr), Alpha::R31)
327 bool AlphaInstrInfo::
328 ReverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const {
329 assert(Cond.size() == 2 && "Invalid Alpha branch opcode!");
330 Cond[0].setImm(AlphaRevCondCode(Cond[0].getImm()));
334 /// getGlobalBaseReg - Return a virtual register initialized with the
335 /// the global base register value. Output instructions required to
336 /// initialize the register in the function entry block, if necessary.
338 unsigned AlphaInstrInfo::getGlobalBaseReg(MachineFunction *MF) const {
339 AlphaMachineFunctionInfo *AlphaFI = MF->getInfo<AlphaMachineFunctionInfo>();
340 unsigned GlobalBaseReg = AlphaFI->getGlobalBaseReg();
341 if (GlobalBaseReg != 0)
342 return GlobalBaseReg;
344 // Insert the set of GlobalBaseReg into the first MBB of the function
345 MachineBasicBlock &FirstMBB = MF->front();
346 MachineBasicBlock::iterator MBBI = FirstMBB.begin();
347 MachineRegisterInfo &RegInfo = MF->getRegInfo();
348 const TargetInstrInfo *TII = MF->getTarget().getInstrInfo();
350 GlobalBaseReg = RegInfo.createVirtualRegister(&Alpha::GPRCRegClass);
351 BuildMI(FirstMBB, MBBI, DebugLoc(), TII->get(TargetOpcode::COPY),
352 GlobalBaseReg).addReg(Alpha::R29);
353 RegInfo.addLiveIn(Alpha::R29);
355 AlphaFI->setGlobalBaseReg(GlobalBaseReg);
356 return GlobalBaseReg;
359 /// getGlobalRetAddr - Return a virtual register initialized with the
360 /// the global base register value. Output instructions required to
361 /// initialize the register in the function entry block, if necessary.
363 unsigned AlphaInstrInfo::getGlobalRetAddr(MachineFunction *MF) const {
364 AlphaMachineFunctionInfo *AlphaFI = MF->getInfo<AlphaMachineFunctionInfo>();
365 unsigned GlobalRetAddr = AlphaFI->getGlobalRetAddr();
366 if (GlobalRetAddr != 0)
367 return GlobalRetAddr;
369 // Insert the set of GlobalRetAddr into the first MBB of the function
370 MachineBasicBlock &FirstMBB = MF->front();
371 MachineBasicBlock::iterator MBBI = FirstMBB.begin();
372 MachineRegisterInfo &RegInfo = MF->getRegInfo();
373 const TargetInstrInfo *TII = MF->getTarget().getInstrInfo();
375 GlobalRetAddr = RegInfo.createVirtualRegister(&Alpha::GPRCRegClass);
376 BuildMI(FirstMBB, MBBI, DebugLoc(), TII->get(TargetOpcode::COPY),
377 GlobalRetAddr).addReg(Alpha::R26);
378 RegInfo.addLiveIn(Alpha::R26);
380 AlphaFI->setGlobalRetAddr(GlobalRetAddr);
381 return GlobalRetAddr;