1 //===- AlphaInstrInfo.cpp - Alpha Instruction Information -------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains the Alpha implementation of the TargetInstrInfo class.
12 //===----------------------------------------------------------------------===//
15 #include "AlphaInstrInfo.h"
16 #include "AlphaGenInstrInfo.inc"
17 #include "llvm/ADT/STLExtras.h"
18 #include "llvm/ADT/SmallVector.h"
19 #include "llvm/CodeGen/MachineInstrBuilder.h"
22 AlphaInstrInfo::AlphaInstrInfo()
23 : TargetInstrInfoImpl(AlphaInsts, array_lengthof(AlphaInsts)),
27 bool AlphaInstrInfo::isMoveInstr(const MachineInstr& MI,
28 unsigned& sourceReg, unsigned& destReg,
29 unsigned& SrcSR, unsigned& DstSR) const {
30 unsigned oc = MI.getOpcode();
31 if (oc == Alpha::BISr ||
34 oc == Alpha::CPYSSt ||
35 oc == Alpha::CPYSTs) {
38 assert(MI.getNumOperands() >= 3 &&
39 MI.getOperand(0).isReg() &&
40 MI.getOperand(1).isReg() &&
41 MI.getOperand(2).isReg() &&
42 "invalid Alpha BIS instruction!");
43 if (MI.getOperand(1).getReg() == MI.getOperand(2).getReg()) {
44 sourceReg = MI.getOperand(1).getReg();
45 destReg = MI.getOperand(0).getReg();
54 AlphaInstrInfo::isLoadFromStackSlot(const MachineInstr *MI,
55 int &FrameIndex) const {
56 switch (MI->getOpcode()) {
63 if (MI->getOperand(1).isFI()) {
64 FrameIndex = MI->getOperand(1).getIndex();
65 return MI->getOperand(0).getReg();
73 AlphaInstrInfo::isStoreToStackSlot(const MachineInstr *MI,
74 int &FrameIndex) const {
75 switch (MI->getOpcode()) {
82 if (MI->getOperand(1).isFI()) {
83 FrameIndex = MI->getOperand(1).getIndex();
84 return MI->getOperand(0).getReg();
91 static bool isAlphaIntCondCode(unsigned Opcode) {
107 unsigned AlphaInstrInfo::InsertBranch(MachineBasicBlock &MBB,
108 MachineBasicBlock *TBB,
109 MachineBasicBlock *FBB,
110 const SmallVectorImpl<MachineOperand> &Cond) const {
111 assert(TBB && "InsertBranch must not be told to insert a fallthrough");
112 assert((Cond.size() == 2 || Cond.size() == 0) &&
113 "Alpha branch conditions have two components!");
117 if (Cond.empty()) // Unconditional branch
118 BuildMI(&MBB, get(Alpha::BR)).addMBB(TBB);
119 else // Conditional branch
120 if (isAlphaIntCondCode(Cond[0].getImm()))
121 BuildMI(&MBB, get(Alpha::COND_BRANCH_I))
122 .addImm(Cond[0].getImm()).addReg(Cond[1].getReg()).addMBB(TBB);
124 BuildMI(&MBB, get(Alpha::COND_BRANCH_F))
125 .addImm(Cond[0].getImm()).addReg(Cond[1].getReg()).addMBB(TBB);
129 // Two-way Conditional Branch.
130 if (isAlphaIntCondCode(Cond[0].getImm()))
131 BuildMI(&MBB, get(Alpha::COND_BRANCH_I))
132 .addImm(Cond[0].getImm()).addReg(Cond[1].getReg()).addMBB(TBB);
134 BuildMI(&MBB, get(Alpha::COND_BRANCH_F))
135 .addImm(Cond[0].getImm()).addReg(Cond[1].getReg()).addMBB(TBB);
136 BuildMI(&MBB, get(Alpha::BR)).addMBB(FBB);
140 bool AlphaInstrInfo::copyRegToReg(MachineBasicBlock &MBB,
141 MachineBasicBlock::iterator MI,
142 unsigned DestReg, unsigned SrcReg,
143 const TargetRegisterClass *DestRC,
144 const TargetRegisterClass *SrcRC) const {
145 //cerr << "copyRegToReg " << DestReg << " <- " << SrcReg << "\n";
146 if (DestRC != SrcRC) {
147 // Not yet supported!
151 if (DestRC == Alpha::GPRCRegisterClass) {
152 BuildMI(MBB, MI, get(Alpha::BISr), DestReg).addReg(SrcReg).addReg(SrcReg);
153 } else if (DestRC == Alpha::F4RCRegisterClass) {
154 BuildMI(MBB, MI, get(Alpha::CPYSS), DestReg).addReg(SrcReg).addReg(SrcReg);
155 } else if (DestRC == Alpha::F8RCRegisterClass) {
156 BuildMI(MBB, MI, get(Alpha::CPYST), DestReg).addReg(SrcReg).addReg(SrcReg);
158 // Attempt to copy register that is not GPR or FPR
166 AlphaInstrInfo::storeRegToStackSlot(MachineBasicBlock &MBB,
167 MachineBasicBlock::iterator MI,
168 unsigned SrcReg, bool isKill, int FrameIdx,
169 const TargetRegisterClass *RC) const {
170 //cerr << "Trying to store " << getPrettyName(SrcReg) << " to "
171 // << FrameIdx << "\n";
172 //BuildMI(MBB, MI, Alpha::WTF, 0).addReg(SrcReg);
173 if (RC == Alpha::F4RCRegisterClass)
174 BuildMI(MBB, MI, get(Alpha::STS))
175 .addReg(SrcReg, false, false, isKill)
176 .addFrameIndex(FrameIdx).addReg(Alpha::F31);
177 else if (RC == Alpha::F8RCRegisterClass)
178 BuildMI(MBB, MI, get(Alpha::STT))
179 .addReg(SrcReg, false, false, isKill)
180 .addFrameIndex(FrameIdx).addReg(Alpha::F31);
181 else if (RC == Alpha::GPRCRegisterClass)
182 BuildMI(MBB, MI, get(Alpha::STQ))
183 .addReg(SrcReg, false, false, isKill)
184 .addFrameIndex(FrameIdx).addReg(Alpha::F31);
189 void AlphaInstrInfo::storeRegToAddr(MachineFunction &MF, unsigned SrcReg,
191 SmallVectorImpl<MachineOperand> &Addr,
192 const TargetRegisterClass *RC,
193 SmallVectorImpl<MachineInstr*> &NewMIs) const {
195 if (RC == Alpha::F4RCRegisterClass)
197 else if (RC == Alpha::F8RCRegisterClass)
199 else if (RC == Alpha::GPRCRegisterClass)
203 MachineInstrBuilder MIB =
204 BuildMI(MF, get(Opc)).addReg(SrcReg, false, false, isKill);
205 for (unsigned i = 0, e = Addr.size(); i != e; ++i) {
206 MachineOperand &MO = Addr[i];
208 MIB.addReg(MO.getReg(), MO.isDef(), MO.isImplicit());
210 MIB.addImm(MO.getImm());
212 NewMIs.push_back(MIB);
216 AlphaInstrInfo::loadRegFromStackSlot(MachineBasicBlock &MBB,
217 MachineBasicBlock::iterator MI,
218 unsigned DestReg, int FrameIdx,
219 const TargetRegisterClass *RC) const {
220 //cerr << "Trying to load " << getPrettyName(DestReg) << " to "
221 // << FrameIdx << "\n";
222 if (RC == Alpha::F4RCRegisterClass)
223 BuildMI(MBB, MI, get(Alpha::LDS), DestReg)
224 .addFrameIndex(FrameIdx).addReg(Alpha::F31);
225 else if (RC == Alpha::F8RCRegisterClass)
226 BuildMI(MBB, MI, get(Alpha::LDT), DestReg)
227 .addFrameIndex(FrameIdx).addReg(Alpha::F31);
228 else if (RC == Alpha::GPRCRegisterClass)
229 BuildMI(MBB, MI, get(Alpha::LDQ), DestReg)
230 .addFrameIndex(FrameIdx).addReg(Alpha::F31);
235 void AlphaInstrInfo::loadRegFromAddr(MachineFunction &MF, unsigned DestReg,
236 SmallVectorImpl<MachineOperand> &Addr,
237 const TargetRegisterClass *RC,
238 SmallVectorImpl<MachineInstr*> &NewMIs) const {
240 if (RC == Alpha::F4RCRegisterClass)
242 else if (RC == Alpha::F8RCRegisterClass)
244 else if (RC == Alpha::GPRCRegisterClass)
248 MachineInstrBuilder MIB =
249 BuildMI(MF, get(Opc), DestReg);
250 for (unsigned i = 0, e = Addr.size(); i != e; ++i) {
251 MachineOperand &MO = Addr[i];
253 MIB.addReg(MO.getReg(), MO.isDef(), MO.isImplicit());
255 MIB.addImm(MO.getImm());
257 NewMIs.push_back(MIB);
260 MachineInstr *AlphaInstrInfo::foldMemoryOperandImpl(MachineFunction &MF,
262 const SmallVectorImpl<unsigned> &Ops,
263 int FrameIndex) const {
264 if (Ops.size() != 1) return NULL;
266 // Make sure this is a reg-reg copy.
267 unsigned Opc = MI->getOpcode();
269 MachineInstr *NewMI = NULL;
276 if (MI->getOperand(1).getReg() == MI->getOperand(2).getReg()) {
277 if (Ops[0] == 0) { // move -> store
278 unsigned InReg = MI->getOperand(1).getReg();
279 bool isKill = MI->getOperand(1).isKill();
280 Opc = (Opc == Alpha::BISr) ? Alpha::STQ :
281 ((Opc == Alpha::CPYSS) ? Alpha::STS : Alpha::STT);
282 NewMI = BuildMI(MF, get(Opc)).addReg(InReg, false, false, isKill)
283 .addFrameIndex(FrameIndex)
285 } else { // load -> move
286 unsigned OutReg = MI->getOperand(0).getReg();
287 bool isDead = MI->getOperand(0).isDead();
288 Opc = (Opc == Alpha::BISr) ? Alpha::LDQ :
289 ((Opc == Alpha::CPYSS) ? Alpha::LDS : Alpha::LDT);
290 NewMI = BuildMI(MF, get(Opc)).addReg(OutReg, true, false, false, isDead)
291 .addFrameIndex(FrameIndex)
300 static unsigned AlphaRevCondCode(unsigned Opcode) {
302 case Alpha::BEQ: return Alpha::BNE;
303 case Alpha::BNE: return Alpha::BEQ;
304 case Alpha::BGE: return Alpha::BLT;
305 case Alpha::BGT: return Alpha::BLE;
306 case Alpha::BLE: return Alpha::BGT;
307 case Alpha::BLT: return Alpha::BGE;
308 case Alpha::BLBC: return Alpha::BLBS;
309 case Alpha::BLBS: return Alpha::BLBC;
310 case Alpha::FBEQ: return Alpha::FBNE;
311 case Alpha::FBNE: return Alpha::FBEQ;
312 case Alpha::FBGE: return Alpha::FBLT;
313 case Alpha::FBGT: return Alpha::FBLE;
314 case Alpha::FBLE: return Alpha::FBGT;
315 case Alpha::FBLT: return Alpha::FBGE;
317 assert(0 && "Unknown opcode");
319 return 0; // Not reached
323 bool AlphaInstrInfo::AnalyzeBranch(MachineBasicBlock &MBB,MachineBasicBlock *&TBB,
324 MachineBasicBlock *&FBB,
325 SmallVectorImpl<MachineOperand> &Cond) const {
326 // If the block has no terminators, it just falls into the block after it.
327 MachineBasicBlock::iterator I = MBB.end();
328 if (I == MBB.begin() || !isUnpredicatedTerminator(--I))
331 // Get the last instruction in the block.
332 MachineInstr *LastInst = I;
334 // If there is only one terminator instruction, process it.
335 if (I == MBB.begin() || !isUnpredicatedTerminator(--I)) {
336 if (LastInst->getOpcode() == Alpha::BR) {
337 TBB = LastInst->getOperand(0).getMBB();
339 } else if (LastInst->getOpcode() == Alpha::COND_BRANCH_I ||
340 LastInst->getOpcode() == Alpha::COND_BRANCH_F) {
341 // Block ends with fall-through condbranch.
342 TBB = LastInst->getOperand(2).getMBB();
343 Cond.push_back(LastInst->getOperand(0));
344 Cond.push_back(LastInst->getOperand(1));
347 // Otherwise, don't know what this is.
351 // Get the instruction before it if it's a terminator.
352 MachineInstr *SecondLastInst = I;
354 // If there are three terminators, we don't know what sort of block this is.
355 if (SecondLastInst && I != MBB.begin() &&
356 isUnpredicatedTerminator(--I))
359 // If the block ends with Alpha::BR and Alpha::COND_BRANCH_*, handle it.
360 if ((SecondLastInst->getOpcode() == Alpha::COND_BRANCH_I ||
361 SecondLastInst->getOpcode() == Alpha::COND_BRANCH_F) &&
362 LastInst->getOpcode() == Alpha::BR) {
363 TBB = SecondLastInst->getOperand(2).getMBB();
364 Cond.push_back(SecondLastInst->getOperand(0));
365 Cond.push_back(SecondLastInst->getOperand(1));
366 FBB = LastInst->getOperand(0).getMBB();
370 // If the block ends with two Alpha::BRs, handle it. The second one is not
371 // executed, so remove it.
372 if (SecondLastInst->getOpcode() == Alpha::BR &&
373 LastInst->getOpcode() == Alpha::BR) {
374 TBB = SecondLastInst->getOperand(0).getMBB();
376 I->eraseFromParent();
380 // Otherwise, can't handle this.
384 unsigned AlphaInstrInfo::RemoveBranch(MachineBasicBlock &MBB) const {
385 MachineBasicBlock::iterator I = MBB.end();
386 if (I == MBB.begin()) return 0;
388 if (I->getOpcode() != Alpha::BR &&
389 I->getOpcode() != Alpha::COND_BRANCH_I &&
390 I->getOpcode() != Alpha::COND_BRANCH_F)
393 // Remove the branch.
394 I->eraseFromParent();
398 if (I == MBB.begin()) return 1;
400 if (I->getOpcode() != Alpha::COND_BRANCH_I &&
401 I->getOpcode() != Alpha::COND_BRANCH_F)
404 // Remove the branch.
405 I->eraseFromParent();
409 void AlphaInstrInfo::insertNoop(MachineBasicBlock &MBB,
410 MachineBasicBlock::iterator MI) const {
411 BuildMI(MBB, MI, get(Alpha::BISr), Alpha::R31).addReg(Alpha::R31)
415 bool AlphaInstrInfo::BlockHasNoFallThrough(const MachineBasicBlock &MBB) const {
416 if (MBB.empty()) return false;
418 switch (MBB.back().getOpcode()) {
419 case Alpha::RETDAG: // Return.
421 case Alpha::BR: // Uncond branch.
422 case Alpha::JMP: // Indirect branch.
424 default: return false;
427 bool AlphaInstrInfo::
428 ReverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const {
429 assert(Cond.size() == 2 && "Invalid Alpha branch opcode!");
430 Cond[0].setImm(AlphaRevCondCode(Cond[0].getImm()));