1 //===- AlphaInstrInfo.cpp - Alpha Instruction Information -------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file was developed by the LLVM research group and is distributed under
6 // the University of Illinois Open Source License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains the Alpha implementation of the TargetInstrInfo class.
12 //===----------------------------------------------------------------------===//
15 #include "AlphaInstrInfo.h"
16 #include "AlphaGenInstrInfo.inc"
17 #include "llvm/CodeGen/MachineInstrBuilder.h"
21 AlphaInstrInfo::AlphaInstrInfo()
22 : TargetInstrInfo(AlphaInsts, sizeof(AlphaInsts)/sizeof(AlphaInsts[0])) { }
25 bool AlphaInstrInfo::isMoveInstr(const MachineInstr& MI,
27 unsigned& destReg) const {
28 MachineOpCode oc = MI.getOpcode();
29 if (oc == Alpha::BIS ||
32 oc == Alpha::CPYSSt ||
33 oc == Alpha::CPYSTs) {
36 assert(MI.getNumOperands() == 3 &&
37 MI.getOperand(0).isRegister() &&
38 MI.getOperand(1).isRegister() &&
39 MI.getOperand(2).isRegister() &&
40 "invalid Alpha BIS instruction!");
41 if (MI.getOperand(1).getReg() == MI.getOperand(2).getReg()) {
42 sourceReg = MI.getOperand(1).getReg();
43 destReg = MI.getOperand(0).getReg();
51 AlphaInstrInfo::isLoadFromStackSlot(MachineInstr *MI, int &FrameIndex) const {
52 switch (MI->getOpcode()) {
59 if (MI->getOperand(1).isFrameIndex()) {
60 FrameIndex = MI->getOperand(1).getFrameIndex();
61 return MI->getOperand(0).getReg();
69 AlphaInstrInfo::isStoreToStackSlot(MachineInstr *MI, int &FrameIndex) const {
70 switch (MI->getOpcode()) {
77 if (MI->getOperand(1).isFrameIndex()) {
78 FrameIndex = MI->getOperand(1).getFrameIndex();
79 return MI->getOperand(0).getReg();
86 void AlphaInstrInfo::InsertBranch(MachineBasicBlock &MBB,MachineBasicBlock *TBB,
87 MachineBasicBlock *FBB,
88 const std::vector<MachineOperand> &Cond)const{
89 // Can only insert uncond branches so far.
90 assert(Cond.empty() && !FBB && TBB && "Can only handle uncond branches!");
91 BuildMI(&MBB, Alpha::BR, 1).addMBB(TBB);