1 //===- AlphaInstrInfo.cpp - Alpha Instruction Information -------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains the Alpha implementation of the TargetInstrInfo class.
12 //===----------------------------------------------------------------------===//
15 #include "AlphaInstrInfo.h"
16 #include "AlphaGenInstrInfo.inc"
17 #include "llvm/ADT/STLExtras.h"
18 #include "llvm/CodeGen/MachineInstrBuilder.h"
21 AlphaInstrInfo::AlphaInstrInfo()
22 : TargetInstrInfoImpl(AlphaInsts, array_lengthof(AlphaInsts)),
26 bool AlphaInstrInfo::isMoveInstr(const MachineInstr& MI,
28 unsigned& destReg) const {
29 unsigned oc = MI.getOpcode();
30 if (oc == Alpha::BISr ||
33 oc == Alpha::CPYSSt ||
34 oc == Alpha::CPYSTs) {
37 assert(MI.getNumOperands() >= 3 &&
38 MI.getOperand(0).isRegister() &&
39 MI.getOperand(1).isRegister() &&
40 MI.getOperand(2).isRegister() &&
41 "invalid Alpha BIS instruction!");
42 if (MI.getOperand(1).getReg() == MI.getOperand(2).getReg()) {
43 sourceReg = MI.getOperand(1).getReg();
44 destReg = MI.getOperand(0).getReg();
52 AlphaInstrInfo::isLoadFromStackSlot(MachineInstr *MI, int &FrameIndex) const {
53 switch (MI->getOpcode()) {
60 if (MI->getOperand(1).isFrameIndex()) {
61 FrameIndex = MI->getOperand(1).getIndex();
62 return MI->getOperand(0).getReg();
70 AlphaInstrInfo::isStoreToStackSlot(MachineInstr *MI, int &FrameIndex) const {
71 switch (MI->getOpcode()) {
78 if (MI->getOperand(1).isFrameIndex()) {
79 FrameIndex = MI->getOperand(1).getIndex();
80 return MI->getOperand(0).getReg();
87 static bool isAlphaIntCondCode(unsigned Opcode) {
103 unsigned AlphaInstrInfo::InsertBranch(MachineBasicBlock &MBB,MachineBasicBlock *TBB,
104 MachineBasicBlock *FBB,
105 const std::vector<MachineOperand> &Cond)const{
106 assert(TBB && "InsertBranch must not be told to insert a fallthrough");
107 assert((Cond.size() == 2 || Cond.size() == 0) &&
108 "Alpha branch conditions have two components!");
112 if (Cond.empty()) // Unconditional branch
113 BuildMI(&MBB, get(Alpha::BR)).addMBB(TBB);
114 else // Conditional branch
115 if (isAlphaIntCondCode(Cond[0].getImm()))
116 BuildMI(&MBB, get(Alpha::COND_BRANCH_I))
117 .addImm(Cond[0].getImm()).addReg(Cond[1].getReg()).addMBB(TBB);
119 BuildMI(&MBB, get(Alpha::COND_BRANCH_F))
120 .addImm(Cond[0].getImm()).addReg(Cond[1].getReg()).addMBB(TBB);
124 // Two-way Conditional Branch.
125 if (isAlphaIntCondCode(Cond[0].getImm()))
126 BuildMI(&MBB, get(Alpha::COND_BRANCH_I))
127 .addImm(Cond[0].getImm()).addReg(Cond[1].getReg()).addMBB(TBB);
129 BuildMI(&MBB, get(Alpha::COND_BRANCH_F))
130 .addImm(Cond[0].getImm()).addReg(Cond[1].getReg()).addMBB(TBB);
131 BuildMI(&MBB, get(Alpha::BR)).addMBB(FBB);
135 void AlphaInstrInfo::copyRegToReg(MachineBasicBlock &MBB,
136 MachineBasicBlock::iterator MI,
137 unsigned DestReg, unsigned SrcReg,
138 const TargetRegisterClass *DestRC,
139 const TargetRegisterClass *SrcRC) const {
140 //cerr << "copyRegToReg " << DestReg << " <- " << SrcReg << "\n";
141 if (DestRC != SrcRC) {
142 cerr << "Not yet supported!";
146 if (DestRC == Alpha::GPRCRegisterClass) {
147 BuildMI(MBB, MI, get(Alpha::BISr), DestReg).addReg(SrcReg).addReg(SrcReg);
148 } else if (DestRC == Alpha::F4RCRegisterClass) {
149 BuildMI(MBB, MI, get(Alpha::CPYSS), DestReg).addReg(SrcReg).addReg(SrcReg);
150 } else if (DestRC == Alpha::F8RCRegisterClass) {
151 BuildMI(MBB, MI, get(Alpha::CPYST), DestReg).addReg(SrcReg).addReg(SrcReg);
153 cerr << "Attempt to copy register that is not GPR or FPR";
159 AlphaInstrInfo::storeRegToStackSlot(MachineBasicBlock &MBB,
160 MachineBasicBlock::iterator MI,
161 unsigned SrcReg, bool isKill, int FrameIdx,
162 const TargetRegisterClass *RC) const {
163 //cerr << "Trying to store " << getPrettyName(SrcReg) << " to "
164 // << FrameIdx << "\n";
165 //BuildMI(MBB, MI, Alpha::WTF, 0).addReg(SrcReg);
166 if (RC == Alpha::F4RCRegisterClass)
167 BuildMI(MBB, MI, get(Alpha::STS))
168 .addReg(SrcReg, false, false, isKill)
169 .addFrameIndex(FrameIdx).addReg(Alpha::F31);
170 else if (RC == Alpha::F8RCRegisterClass)
171 BuildMI(MBB, MI, get(Alpha::STT))
172 .addReg(SrcReg, false, false, isKill)
173 .addFrameIndex(FrameIdx).addReg(Alpha::F31);
174 else if (RC == Alpha::GPRCRegisterClass)
175 BuildMI(MBB, MI, get(Alpha::STQ))
176 .addReg(SrcReg, false, false, isKill)
177 .addFrameIndex(FrameIdx).addReg(Alpha::F31);
182 void AlphaInstrInfo::storeRegToAddr(MachineFunction &MF, unsigned SrcReg,
184 SmallVectorImpl<MachineOperand> &Addr,
185 const TargetRegisterClass *RC,
186 SmallVectorImpl<MachineInstr*> &NewMIs) const {
188 if (RC == Alpha::F4RCRegisterClass)
190 else if (RC == Alpha::F8RCRegisterClass)
192 else if (RC == Alpha::GPRCRegisterClass)
196 MachineInstrBuilder MIB =
197 BuildMI(get(Opc)).addReg(SrcReg, false, false, isKill);
198 for (unsigned i = 0, e = Addr.size(); i != e; ++i) {
199 MachineOperand &MO = Addr[i];
201 MIB.addReg(MO.getReg(), MO.isDef(), MO.isImplicit());
203 MIB.addImm(MO.getImm());
205 NewMIs.push_back(MIB);
209 AlphaInstrInfo::loadRegFromStackSlot(MachineBasicBlock &MBB,
210 MachineBasicBlock::iterator MI,
211 unsigned DestReg, int FrameIdx,
212 const TargetRegisterClass *RC) const {
213 //cerr << "Trying to load " << getPrettyName(DestReg) << " to "
214 // << FrameIdx << "\n";
215 if (RC == Alpha::F4RCRegisterClass)
216 BuildMI(MBB, MI, get(Alpha::LDS), DestReg)
217 .addFrameIndex(FrameIdx).addReg(Alpha::F31);
218 else if (RC == Alpha::F8RCRegisterClass)
219 BuildMI(MBB, MI, get(Alpha::LDT), DestReg)
220 .addFrameIndex(FrameIdx).addReg(Alpha::F31);
221 else if (RC == Alpha::GPRCRegisterClass)
222 BuildMI(MBB, MI, get(Alpha::LDQ), DestReg)
223 .addFrameIndex(FrameIdx).addReg(Alpha::F31);
228 void AlphaInstrInfo::loadRegFromAddr(MachineFunction &MF, unsigned DestReg,
229 SmallVectorImpl<MachineOperand> &Addr,
230 const TargetRegisterClass *RC,
231 SmallVectorImpl<MachineInstr*> &NewMIs) const {
233 if (RC == Alpha::F4RCRegisterClass)
235 else if (RC == Alpha::F8RCRegisterClass)
237 else if (RC == Alpha::GPRCRegisterClass)
241 MachineInstrBuilder MIB =
242 BuildMI(get(Opc), DestReg);
243 for (unsigned i = 0, e = Addr.size(); i != e; ++i) {
244 MachineOperand &MO = Addr[i];
246 MIB.addReg(MO.getReg(), MO.isDef(), MO.isImplicit());
248 MIB.addImm(MO.getImm());
250 NewMIs.push_back(MIB);
253 MachineInstr *AlphaInstrInfo::foldMemoryOperand(MachineFunction &MF,
255 SmallVectorImpl<unsigned> &Ops,
256 int FrameIndex) const {
257 if (Ops.size() != 1) return NULL;
259 // Make sure this is a reg-reg copy.
260 unsigned Opc = MI->getOpcode();
262 MachineInstr *NewMI = NULL;
269 if (MI->getOperand(1).getReg() == MI->getOperand(2).getReg()) {
270 if (Ops[0] == 0) { // move -> store
271 unsigned InReg = MI->getOperand(1).getReg();
272 Opc = (Opc == Alpha::BISr) ? Alpha::STQ :
273 ((Opc == Alpha::CPYSS) ? Alpha::STS : Alpha::STT);
274 NewMI = BuildMI(get(Opc)).addReg(InReg).addFrameIndex(FrameIndex)
276 } else { // load -> move
277 unsigned OutReg = MI->getOperand(0).getReg();
278 Opc = (Opc == Alpha::BISr) ? Alpha::LDQ :
279 ((Opc == Alpha::CPYSS) ? Alpha::LDS : Alpha::LDT);
280 NewMI = BuildMI(get(Opc), OutReg).addFrameIndex(FrameIndex)
287 NewMI->copyKillDeadInfo(MI);
291 static unsigned AlphaRevCondCode(unsigned Opcode) {
293 case Alpha::BEQ: return Alpha::BNE;
294 case Alpha::BNE: return Alpha::BEQ;
295 case Alpha::BGE: return Alpha::BLT;
296 case Alpha::BGT: return Alpha::BLE;
297 case Alpha::BLE: return Alpha::BGT;
298 case Alpha::BLT: return Alpha::BGE;
299 case Alpha::BLBC: return Alpha::BLBS;
300 case Alpha::BLBS: return Alpha::BLBC;
301 case Alpha::FBEQ: return Alpha::FBNE;
302 case Alpha::FBNE: return Alpha::FBEQ;
303 case Alpha::FBGE: return Alpha::FBLT;
304 case Alpha::FBGT: return Alpha::FBLE;
305 case Alpha::FBLE: return Alpha::FBGT;
306 case Alpha::FBLT: return Alpha::FBGE;
308 assert(0 && "Unknown opcode");
310 return 0; // Not reached
314 bool AlphaInstrInfo::AnalyzeBranch(MachineBasicBlock &MBB,MachineBasicBlock *&TBB,
315 MachineBasicBlock *&FBB,
316 std::vector<MachineOperand> &Cond) const {
317 // If the block has no terminators, it just falls into the block after it.
318 MachineBasicBlock::iterator I = MBB.end();
319 if (I == MBB.begin() || !isUnpredicatedTerminator(--I))
322 // Get the last instruction in the block.
323 MachineInstr *LastInst = I;
325 // If there is only one terminator instruction, process it.
326 if (I == MBB.begin() || !isUnpredicatedTerminator(--I)) {
327 if (LastInst->getOpcode() == Alpha::BR) {
328 TBB = LastInst->getOperand(0).getMBB();
330 } else if (LastInst->getOpcode() == Alpha::COND_BRANCH_I ||
331 LastInst->getOpcode() == Alpha::COND_BRANCH_F) {
332 // Block ends with fall-through condbranch.
333 TBB = LastInst->getOperand(2).getMBB();
334 Cond.push_back(LastInst->getOperand(0));
335 Cond.push_back(LastInst->getOperand(1));
338 // Otherwise, don't know what this is.
342 // Get the instruction before it if it's a terminator.
343 MachineInstr *SecondLastInst = I;
345 // If there are three terminators, we don't know what sort of block this is.
346 if (SecondLastInst && I != MBB.begin() &&
347 isUnpredicatedTerminator(--I))
350 // If the block ends with Alpha::BR and Alpha::COND_BRANCH_*, handle it.
351 if ((SecondLastInst->getOpcode() == Alpha::COND_BRANCH_I ||
352 SecondLastInst->getOpcode() == Alpha::COND_BRANCH_F) &&
353 LastInst->getOpcode() == Alpha::BR) {
354 TBB = SecondLastInst->getOperand(2).getMBB();
355 Cond.push_back(SecondLastInst->getOperand(0));
356 Cond.push_back(SecondLastInst->getOperand(1));
357 FBB = LastInst->getOperand(0).getMBB();
361 // If the block ends with two Alpha::BRs, handle it. The second one is not
362 // executed, so remove it.
363 if (SecondLastInst->getOpcode() == Alpha::BR &&
364 LastInst->getOpcode() == Alpha::BR) {
365 TBB = SecondLastInst->getOperand(0).getMBB();
367 I->eraseFromParent();
371 // Otherwise, can't handle this.
375 unsigned AlphaInstrInfo::RemoveBranch(MachineBasicBlock &MBB) const {
376 MachineBasicBlock::iterator I = MBB.end();
377 if (I == MBB.begin()) return 0;
379 if (I->getOpcode() != Alpha::BR &&
380 I->getOpcode() != Alpha::COND_BRANCH_I &&
381 I->getOpcode() != Alpha::COND_BRANCH_F)
384 // Remove the branch.
385 I->eraseFromParent();
389 if (I == MBB.begin()) return 1;
391 if (I->getOpcode() != Alpha::COND_BRANCH_I &&
392 I->getOpcode() != Alpha::COND_BRANCH_F)
395 // Remove the branch.
396 I->eraseFromParent();
400 void AlphaInstrInfo::insertNoop(MachineBasicBlock &MBB,
401 MachineBasicBlock::iterator MI) const {
402 BuildMI(MBB, MI, get(Alpha::BISr), Alpha::R31).addReg(Alpha::R31)
406 bool AlphaInstrInfo::BlockHasNoFallThrough(MachineBasicBlock &MBB) const {
407 if (MBB.empty()) return false;
409 switch (MBB.back().getOpcode()) {
410 case Alpha::RETDAG: // Return.
412 case Alpha::BR: // Uncond branch.
413 case Alpha::JMP: // Indirect branch.
415 default: return false;
418 bool AlphaInstrInfo::
419 ReverseBranchCondition(std::vector<MachineOperand> &Cond) const {
420 assert(Cond.size() == 2 && "Invalid Alpha branch opcode!");
421 Cond[0].setImm(AlphaRevCondCode(Cond[0].getImm()));