1 //===- AlphaInstrInfo.cpp - Alpha Instruction Information -------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains the Alpha implementation of the TargetInstrInfo class.
12 //===----------------------------------------------------------------------===//
15 #include "AlphaInstrInfo.h"
16 #include "AlphaMachineFunctionInfo.h"
17 #include "AlphaGenInstrInfo.inc"
18 #include "llvm/CodeGen/MachineRegisterInfo.h"
19 #include "llvm/ADT/STLExtras.h"
20 #include "llvm/ADT/SmallVector.h"
21 #include "llvm/CodeGen/MachineInstrBuilder.h"
22 #include "llvm/Support/ErrorHandling.h"
25 AlphaInstrInfo::AlphaInstrInfo()
26 : TargetInstrInfoImpl(AlphaInsts, array_lengthof(AlphaInsts)),
30 bool AlphaInstrInfo::isMoveInstr(const MachineInstr& MI,
31 unsigned& sourceReg, unsigned& destReg,
32 unsigned& SrcSR, unsigned& DstSR) const {
33 unsigned oc = MI.getOpcode();
34 if (oc == Alpha::BISr ||
37 oc == Alpha::CPYSSt ||
38 oc == Alpha::CPYSTs) {
41 assert(MI.getNumOperands() >= 3 &&
42 MI.getOperand(0).isReg() &&
43 MI.getOperand(1).isReg() &&
44 MI.getOperand(2).isReg() &&
45 "invalid Alpha BIS instruction!");
46 if (MI.getOperand(1).getReg() == MI.getOperand(2).getReg()) {
47 sourceReg = MI.getOperand(1).getReg();
48 destReg = MI.getOperand(0).getReg();
57 AlphaInstrInfo::isLoadFromStackSlot(const MachineInstr *MI,
58 int &FrameIndex) const {
59 switch (MI->getOpcode()) {
66 if (MI->getOperand(1).isFI()) {
67 FrameIndex = MI->getOperand(1).getIndex();
68 return MI->getOperand(0).getReg();
76 AlphaInstrInfo::isStoreToStackSlot(const MachineInstr *MI,
77 int &FrameIndex) const {
78 switch (MI->getOpcode()) {
85 if (MI->getOperand(1).isFI()) {
86 FrameIndex = MI->getOperand(1).getIndex();
87 return MI->getOperand(0).getReg();
94 static bool isAlphaIntCondCode(unsigned Opcode) {
110 unsigned AlphaInstrInfo::InsertBranch(MachineBasicBlock &MBB,
111 MachineBasicBlock *TBB,
112 MachineBasicBlock *FBB,
113 const SmallVectorImpl<MachineOperand> &Cond) const {
114 // FIXME this should probably have a DebugLoc argument
116 assert(TBB && "InsertBranch must not be told to insert a fallthrough");
117 assert((Cond.size() == 2 || Cond.size() == 0) &&
118 "Alpha branch conditions have two components!");
122 if (Cond.empty()) // Unconditional branch
123 BuildMI(&MBB, dl, get(Alpha::BR)).addMBB(TBB);
124 else // Conditional branch
125 if (isAlphaIntCondCode(Cond[0].getImm()))
126 BuildMI(&MBB, dl, get(Alpha::COND_BRANCH_I))
127 .addImm(Cond[0].getImm()).addReg(Cond[1].getReg()).addMBB(TBB);
129 BuildMI(&MBB, dl, get(Alpha::COND_BRANCH_F))
130 .addImm(Cond[0].getImm()).addReg(Cond[1].getReg()).addMBB(TBB);
134 // Two-way Conditional Branch.
135 if (isAlphaIntCondCode(Cond[0].getImm()))
136 BuildMI(&MBB, dl, get(Alpha::COND_BRANCH_I))
137 .addImm(Cond[0].getImm()).addReg(Cond[1].getReg()).addMBB(TBB);
139 BuildMI(&MBB, dl, get(Alpha::COND_BRANCH_F))
140 .addImm(Cond[0].getImm()).addReg(Cond[1].getReg()).addMBB(TBB);
141 BuildMI(&MBB, dl, get(Alpha::BR)).addMBB(FBB);
145 bool AlphaInstrInfo::copyRegToReg(MachineBasicBlock &MBB,
146 MachineBasicBlock::iterator MI,
147 unsigned DestReg, unsigned SrcReg,
148 const TargetRegisterClass *DestRC,
149 const TargetRegisterClass *SrcRC) const {
150 //cerr << "copyRegToReg " << DestReg << " <- " << SrcReg << "\n";
151 if (DestRC != SrcRC) {
152 // Not yet supported!
157 if (MI != MBB.end()) DL = MI->getDebugLoc();
159 if (DestRC == Alpha::GPRCRegisterClass) {
160 BuildMI(MBB, MI, DL, get(Alpha::BISr), DestReg)
163 } else if (DestRC == Alpha::F4RCRegisterClass) {
164 BuildMI(MBB, MI, DL, get(Alpha::CPYSS), DestReg)
167 } else if (DestRC == Alpha::F8RCRegisterClass) {
168 BuildMI(MBB, MI, DL, get(Alpha::CPYST), DestReg)
172 // Attempt to copy register that is not GPR or FPR
180 AlphaInstrInfo::storeRegToStackSlot(MachineBasicBlock &MBB,
181 MachineBasicBlock::iterator MI,
182 unsigned SrcReg, bool isKill, int FrameIdx,
183 const TargetRegisterClass *RC) const {
184 //cerr << "Trying to store " << getPrettyName(SrcReg) << " to "
185 // << FrameIdx << "\n";
186 //BuildMI(MBB, MI, Alpha::WTF, 0).addReg(SrcReg);
189 if (MI != MBB.end()) DL = MI->getDebugLoc();
191 if (RC == Alpha::F4RCRegisterClass)
192 BuildMI(MBB, MI, DL, get(Alpha::STS))
193 .addReg(SrcReg, getKillRegState(isKill))
194 .addFrameIndex(FrameIdx).addReg(Alpha::F31);
195 else if (RC == Alpha::F8RCRegisterClass)
196 BuildMI(MBB, MI, DL, get(Alpha::STT))
197 .addReg(SrcReg, getKillRegState(isKill))
198 .addFrameIndex(FrameIdx).addReg(Alpha::F31);
199 else if (RC == Alpha::GPRCRegisterClass)
200 BuildMI(MBB, MI, DL, get(Alpha::STQ))
201 .addReg(SrcReg, getKillRegState(isKill))
202 .addFrameIndex(FrameIdx).addReg(Alpha::F31);
204 llvm_unreachable("Unhandled register class");
208 AlphaInstrInfo::loadRegFromStackSlot(MachineBasicBlock &MBB,
209 MachineBasicBlock::iterator MI,
210 unsigned DestReg, int FrameIdx,
211 const TargetRegisterClass *RC) const {
212 //cerr << "Trying to load " << getPrettyName(DestReg) << " to "
213 // << FrameIdx << "\n";
215 if (MI != MBB.end()) DL = MI->getDebugLoc();
217 if (RC == Alpha::F4RCRegisterClass)
218 BuildMI(MBB, MI, DL, get(Alpha::LDS), DestReg)
219 .addFrameIndex(FrameIdx).addReg(Alpha::F31);
220 else if (RC == Alpha::F8RCRegisterClass)
221 BuildMI(MBB, MI, DL, get(Alpha::LDT), DestReg)
222 .addFrameIndex(FrameIdx).addReg(Alpha::F31);
223 else if (RC == Alpha::GPRCRegisterClass)
224 BuildMI(MBB, MI, DL, get(Alpha::LDQ), DestReg)
225 .addFrameIndex(FrameIdx).addReg(Alpha::F31);
227 llvm_unreachable("Unhandled register class");
230 MachineInstr *AlphaInstrInfo::foldMemoryOperandImpl(MachineFunction &MF,
232 const SmallVectorImpl<unsigned> &Ops,
233 int FrameIndex) const {
234 if (Ops.size() != 1) return NULL;
236 // Make sure this is a reg-reg copy.
237 unsigned Opc = MI->getOpcode();
239 MachineInstr *NewMI = NULL;
246 if (MI->getOperand(1).getReg() == MI->getOperand(2).getReg()) {
247 if (Ops[0] == 0) { // move -> store
248 unsigned InReg = MI->getOperand(1).getReg();
249 bool isKill = MI->getOperand(1).isKill();
250 bool isUndef = MI->getOperand(1).isUndef();
251 Opc = (Opc == Alpha::BISr) ? Alpha::STQ :
252 ((Opc == Alpha::CPYSS) ? Alpha::STS : Alpha::STT);
253 NewMI = BuildMI(MF, MI->getDebugLoc(), get(Opc))
254 .addReg(InReg, getKillRegState(isKill) | getUndefRegState(isUndef))
255 .addFrameIndex(FrameIndex)
257 } else { // load -> move
258 unsigned OutReg = MI->getOperand(0).getReg();
259 bool isDead = MI->getOperand(0).isDead();
260 bool isUndef = MI->getOperand(0).isUndef();
261 Opc = (Opc == Alpha::BISr) ? Alpha::LDQ :
262 ((Opc == Alpha::CPYSS) ? Alpha::LDS : Alpha::LDT);
263 NewMI = BuildMI(MF, MI->getDebugLoc(), get(Opc))
264 .addReg(OutReg, RegState::Define | getDeadRegState(isDead) |
265 getUndefRegState(isUndef))
266 .addFrameIndex(FrameIndex)
275 static unsigned AlphaRevCondCode(unsigned Opcode) {
277 case Alpha::BEQ: return Alpha::BNE;
278 case Alpha::BNE: return Alpha::BEQ;
279 case Alpha::BGE: return Alpha::BLT;
280 case Alpha::BGT: return Alpha::BLE;
281 case Alpha::BLE: return Alpha::BGT;
282 case Alpha::BLT: return Alpha::BGE;
283 case Alpha::BLBC: return Alpha::BLBS;
284 case Alpha::BLBS: return Alpha::BLBC;
285 case Alpha::FBEQ: return Alpha::FBNE;
286 case Alpha::FBNE: return Alpha::FBEQ;
287 case Alpha::FBGE: return Alpha::FBLT;
288 case Alpha::FBGT: return Alpha::FBLE;
289 case Alpha::FBLE: return Alpha::FBGT;
290 case Alpha::FBLT: return Alpha::FBGE;
292 llvm_unreachable("Unknown opcode");
294 return 0; // Not reached
298 bool AlphaInstrInfo::AnalyzeBranch(MachineBasicBlock &MBB,MachineBasicBlock *&TBB,
299 MachineBasicBlock *&FBB,
300 SmallVectorImpl<MachineOperand> &Cond,
301 bool AllowModify) const {
302 // If the block has no terminators, it just falls into the block after it.
303 MachineBasicBlock::iterator I = MBB.end();
304 if (I == MBB.begin())
307 while (I->isDebugValue()) {
308 if (I == MBB.begin())
312 if (!isUnpredicatedTerminator(I))
315 // Get the last instruction in the block.
316 MachineInstr *LastInst = I;
318 // If there is only one terminator instruction, process it.
319 if (I == MBB.begin() || !isUnpredicatedTerminator(--I)) {
320 if (LastInst->getOpcode() == Alpha::BR) {
321 TBB = LastInst->getOperand(0).getMBB();
323 } else if (LastInst->getOpcode() == Alpha::COND_BRANCH_I ||
324 LastInst->getOpcode() == Alpha::COND_BRANCH_F) {
325 // Block ends with fall-through condbranch.
326 TBB = LastInst->getOperand(2).getMBB();
327 Cond.push_back(LastInst->getOperand(0));
328 Cond.push_back(LastInst->getOperand(1));
331 // Otherwise, don't know what this is.
335 // Get the instruction before it if it's a terminator.
336 MachineInstr *SecondLastInst = I;
338 // If there are three terminators, we don't know what sort of block this is.
339 if (SecondLastInst && I != MBB.begin() &&
340 isUnpredicatedTerminator(--I))
343 // If the block ends with Alpha::BR and Alpha::COND_BRANCH_*, handle it.
344 if ((SecondLastInst->getOpcode() == Alpha::COND_BRANCH_I ||
345 SecondLastInst->getOpcode() == Alpha::COND_BRANCH_F) &&
346 LastInst->getOpcode() == Alpha::BR) {
347 TBB = SecondLastInst->getOperand(2).getMBB();
348 Cond.push_back(SecondLastInst->getOperand(0));
349 Cond.push_back(SecondLastInst->getOperand(1));
350 FBB = LastInst->getOperand(0).getMBB();
354 // If the block ends with two Alpha::BRs, handle it. The second one is not
355 // executed, so remove it.
356 if (SecondLastInst->getOpcode() == Alpha::BR &&
357 LastInst->getOpcode() == Alpha::BR) {
358 TBB = SecondLastInst->getOperand(0).getMBB();
361 I->eraseFromParent();
365 // Otherwise, can't handle this.
369 unsigned AlphaInstrInfo::RemoveBranch(MachineBasicBlock &MBB) const {
370 MachineBasicBlock::iterator I = MBB.end();
371 if (I == MBB.begin()) return 0;
373 while (I->isDebugValue()) {
374 if (I == MBB.begin())
378 if (I->getOpcode() != Alpha::BR &&
379 I->getOpcode() != Alpha::COND_BRANCH_I &&
380 I->getOpcode() != Alpha::COND_BRANCH_F)
383 // Remove the branch.
384 I->eraseFromParent();
388 if (I == MBB.begin()) return 1;
390 if (I->getOpcode() != Alpha::COND_BRANCH_I &&
391 I->getOpcode() != Alpha::COND_BRANCH_F)
394 // Remove the branch.
395 I->eraseFromParent();
399 void AlphaInstrInfo::insertNoop(MachineBasicBlock &MBB,
400 MachineBasicBlock::iterator MI) const {
402 if (MI != MBB.end()) DL = MI->getDebugLoc();
403 BuildMI(MBB, MI, DL, get(Alpha::BISr), Alpha::R31)
408 bool AlphaInstrInfo::
409 ReverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const {
410 assert(Cond.size() == 2 && "Invalid Alpha branch opcode!");
411 Cond[0].setImm(AlphaRevCondCode(Cond[0].getImm()));
415 /// getGlobalBaseReg - Return a virtual register initialized with the
416 /// the global base register value. Output instructions required to
417 /// initialize the register in the function entry block, if necessary.
419 unsigned AlphaInstrInfo::getGlobalBaseReg(MachineFunction *MF) const {
420 AlphaMachineFunctionInfo *AlphaFI = MF->getInfo<AlphaMachineFunctionInfo>();
421 unsigned GlobalBaseReg = AlphaFI->getGlobalBaseReg();
422 if (GlobalBaseReg != 0)
423 return GlobalBaseReg;
425 // Insert the set of GlobalBaseReg into the first MBB of the function
426 MachineBasicBlock &FirstMBB = MF->front();
427 MachineBasicBlock::iterator MBBI = FirstMBB.begin();
428 MachineRegisterInfo &RegInfo = MF->getRegInfo();
429 const TargetInstrInfo *TII = MF->getTarget().getInstrInfo();
431 GlobalBaseReg = RegInfo.createVirtualRegister(&Alpha::GPRCRegClass);
432 bool Ok = TII->copyRegToReg(FirstMBB, MBBI, GlobalBaseReg, Alpha::R29,
433 &Alpha::GPRCRegClass, &Alpha::GPRCRegClass);
434 assert(Ok && "Couldn't assign to global base register!");
435 Ok = Ok; // Silence warning when assertions are turned off.
436 RegInfo.addLiveIn(Alpha::R29);
438 AlphaFI->setGlobalBaseReg(GlobalBaseReg);
439 return GlobalBaseReg;
442 /// getGlobalRetAddr - Return a virtual register initialized with the
443 /// the global base register value. Output instructions required to
444 /// initialize the register in the function entry block, if necessary.
446 unsigned AlphaInstrInfo::getGlobalRetAddr(MachineFunction *MF) const {
447 AlphaMachineFunctionInfo *AlphaFI = MF->getInfo<AlphaMachineFunctionInfo>();
448 unsigned GlobalRetAddr = AlphaFI->getGlobalRetAddr();
449 if (GlobalRetAddr != 0)
450 return GlobalRetAddr;
452 // Insert the set of GlobalRetAddr into the first MBB of the function
453 MachineBasicBlock &FirstMBB = MF->front();
454 MachineBasicBlock::iterator MBBI = FirstMBB.begin();
455 MachineRegisterInfo &RegInfo = MF->getRegInfo();
456 const TargetInstrInfo *TII = MF->getTarget().getInstrInfo();
458 GlobalRetAddr = RegInfo.createVirtualRegister(&Alpha::GPRCRegClass);
459 bool Ok = TII->copyRegToReg(FirstMBB, MBBI, GlobalRetAddr, Alpha::R26,
460 &Alpha::GPRCRegClass, &Alpha::GPRCRegClass);
461 assert(Ok && "Couldn't assign to global return address register!");
462 Ok = Ok; // Silence warning when assertions are turned off.
463 RegInfo.addLiveIn(Alpha::R26);
465 AlphaFI->setGlobalRetAddr(GlobalRetAddr);
466 return GlobalRetAddr;