1 //===- AlphaInstrInfo.cpp - Alpha Instruction Information -------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains the Alpha implementation of the TargetInstrInfo class.
12 //===----------------------------------------------------------------------===//
15 #include "AlphaInstrInfo.h"
16 #include "AlphaGenInstrInfo.inc"
17 #include "llvm/ADT/STLExtras.h"
18 #include "llvm/CodeGen/MachineInstrBuilder.h"
21 AlphaInstrInfo::AlphaInstrInfo()
22 : TargetInstrInfoImpl(AlphaInsts, array_lengthof(AlphaInsts)),
26 bool AlphaInstrInfo::isMoveInstr(const MachineInstr& MI,
28 unsigned& destReg) const {
29 unsigned oc = MI.getOpcode();
30 if (oc == Alpha::BISr ||
33 oc == Alpha::CPYSSt ||
34 oc == Alpha::CPYSTs) {
37 assert(MI.getNumOperands() >= 3 &&
38 MI.getOperand(0).isRegister() &&
39 MI.getOperand(1).isRegister() &&
40 MI.getOperand(2).isRegister() &&
41 "invalid Alpha BIS instruction!");
42 if (MI.getOperand(1).getReg() == MI.getOperand(2).getReg()) {
43 sourceReg = MI.getOperand(1).getReg();
44 destReg = MI.getOperand(0).getReg();
52 AlphaInstrInfo::isLoadFromStackSlot(MachineInstr *MI, int &FrameIndex) const {
53 switch (MI->getOpcode()) {
60 if (MI->getOperand(1).isFrameIndex()) {
61 FrameIndex = MI->getOperand(1).getIndex();
62 return MI->getOperand(0).getReg();
70 AlphaInstrInfo::isStoreToStackSlot(MachineInstr *MI, int &FrameIndex) const {
71 switch (MI->getOpcode()) {
78 if (MI->getOperand(1).isFrameIndex()) {
79 FrameIndex = MI->getOperand(1).getIndex();
80 return MI->getOperand(0).getReg();
87 static bool isAlphaIntCondCode(unsigned Opcode) {
103 unsigned AlphaInstrInfo::InsertBranch(MachineBasicBlock &MBB,
104 MachineBasicBlock *TBB,
105 MachineBasicBlock *FBB,
106 const SmallVectorImpl<MachineOperand> &Cond) const {
107 assert(TBB && "InsertBranch must not be told to insert a fallthrough");
108 assert((Cond.size() == 2 || Cond.size() == 0) &&
109 "Alpha branch conditions have two components!");
113 if (Cond.empty()) // Unconditional branch
114 BuildMI(&MBB, get(Alpha::BR)).addMBB(TBB);
115 else // Conditional branch
116 if (isAlphaIntCondCode(Cond[0].getImm()))
117 BuildMI(&MBB, get(Alpha::COND_BRANCH_I))
118 .addImm(Cond[0].getImm()).addReg(Cond[1].getReg()).addMBB(TBB);
120 BuildMI(&MBB, get(Alpha::COND_BRANCH_F))
121 .addImm(Cond[0].getImm()).addReg(Cond[1].getReg()).addMBB(TBB);
125 // Two-way Conditional Branch.
126 if (isAlphaIntCondCode(Cond[0].getImm()))
127 BuildMI(&MBB, get(Alpha::COND_BRANCH_I))
128 .addImm(Cond[0].getImm()).addReg(Cond[1].getReg()).addMBB(TBB);
130 BuildMI(&MBB, get(Alpha::COND_BRANCH_F))
131 .addImm(Cond[0].getImm()).addReg(Cond[1].getReg()).addMBB(TBB);
132 BuildMI(&MBB, get(Alpha::BR)).addMBB(FBB);
136 void AlphaInstrInfo::copyRegToReg(MachineBasicBlock &MBB,
137 MachineBasicBlock::iterator MI,
138 unsigned DestReg, unsigned SrcReg,
139 const TargetRegisterClass *DestRC,
140 const TargetRegisterClass *SrcRC) const {
141 //cerr << "copyRegToReg " << DestReg << " <- " << SrcReg << "\n";
142 if (DestRC != SrcRC) {
143 cerr << "Not yet supported!";
147 if (DestRC == Alpha::GPRCRegisterClass) {
148 BuildMI(MBB, MI, get(Alpha::BISr), DestReg).addReg(SrcReg).addReg(SrcReg);
149 } else if (DestRC == Alpha::F4RCRegisterClass) {
150 BuildMI(MBB, MI, get(Alpha::CPYSS), DestReg).addReg(SrcReg).addReg(SrcReg);
151 } else if (DestRC == Alpha::F8RCRegisterClass) {
152 BuildMI(MBB, MI, get(Alpha::CPYST), DestReg).addReg(SrcReg).addReg(SrcReg);
154 cerr << "Attempt to copy register that is not GPR or FPR";
160 AlphaInstrInfo::storeRegToStackSlot(MachineBasicBlock &MBB,
161 MachineBasicBlock::iterator MI,
162 unsigned SrcReg, bool isKill, int FrameIdx,
163 const TargetRegisterClass *RC) const {
164 //cerr << "Trying to store " << getPrettyName(SrcReg) << " to "
165 // << FrameIdx << "\n";
166 //BuildMI(MBB, MI, Alpha::WTF, 0).addReg(SrcReg);
167 if (RC == Alpha::F4RCRegisterClass)
168 BuildMI(MBB, MI, get(Alpha::STS))
169 .addReg(SrcReg, false, false, isKill)
170 .addFrameIndex(FrameIdx).addReg(Alpha::F31);
171 else if (RC == Alpha::F8RCRegisterClass)
172 BuildMI(MBB, MI, get(Alpha::STT))
173 .addReg(SrcReg, false, false, isKill)
174 .addFrameIndex(FrameIdx).addReg(Alpha::F31);
175 else if (RC == Alpha::GPRCRegisterClass)
176 BuildMI(MBB, MI, get(Alpha::STQ))
177 .addReg(SrcReg, false, false, isKill)
178 .addFrameIndex(FrameIdx).addReg(Alpha::F31);
183 void AlphaInstrInfo::storeRegToAddr(MachineFunction &MF, unsigned SrcReg,
185 SmallVectorImpl<MachineOperand> &Addr,
186 const TargetRegisterClass *RC,
187 SmallVectorImpl<MachineInstr*> &NewMIs) const {
189 if (RC == Alpha::F4RCRegisterClass)
191 else if (RC == Alpha::F8RCRegisterClass)
193 else if (RC == Alpha::GPRCRegisterClass)
197 MachineInstrBuilder MIB =
198 BuildMI(MF, get(Opc)).addReg(SrcReg, false, false, isKill);
199 for (unsigned i = 0, e = Addr.size(); i != e; ++i) {
200 MachineOperand &MO = Addr[i];
202 MIB.addReg(MO.getReg(), MO.isDef(), MO.isImplicit());
204 MIB.addImm(MO.getImm());
206 NewMIs.push_back(MIB);
210 AlphaInstrInfo::loadRegFromStackSlot(MachineBasicBlock &MBB,
211 MachineBasicBlock::iterator MI,
212 unsigned DestReg, int FrameIdx,
213 const TargetRegisterClass *RC) const {
214 //cerr << "Trying to load " << getPrettyName(DestReg) << " to "
215 // << FrameIdx << "\n";
216 if (RC == Alpha::F4RCRegisterClass)
217 BuildMI(MBB, MI, get(Alpha::LDS), DestReg)
218 .addFrameIndex(FrameIdx).addReg(Alpha::F31);
219 else if (RC == Alpha::F8RCRegisterClass)
220 BuildMI(MBB, MI, get(Alpha::LDT), DestReg)
221 .addFrameIndex(FrameIdx).addReg(Alpha::F31);
222 else if (RC == Alpha::GPRCRegisterClass)
223 BuildMI(MBB, MI, get(Alpha::LDQ), DestReg)
224 .addFrameIndex(FrameIdx).addReg(Alpha::F31);
229 void AlphaInstrInfo::loadRegFromAddr(MachineFunction &MF, unsigned DestReg,
230 SmallVectorImpl<MachineOperand> &Addr,
231 const TargetRegisterClass *RC,
232 SmallVectorImpl<MachineInstr*> &NewMIs) const {
234 if (RC == Alpha::F4RCRegisterClass)
236 else if (RC == Alpha::F8RCRegisterClass)
238 else if (RC == Alpha::GPRCRegisterClass)
242 MachineInstrBuilder MIB =
243 BuildMI(MF, get(Opc), DestReg);
244 for (unsigned i = 0, e = Addr.size(); i != e; ++i) {
245 MachineOperand &MO = Addr[i];
247 MIB.addReg(MO.getReg(), MO.isDef(), MO.isImplicit());
249 MIB.addImm(MO.getImm());
251 NewMIs.push_back(MIB);
254 MachineInstr *AlphaInstrInfo::foldMemoryOperand(MachineFunction &MF,
256 SmallVectorImpl<unsigned> &Ops,
257 int FrameIndex) const {
258 if (Ops.size() != 1) return NULL;
260 // Make sure this is a reg-reg copy.
261 unsigned Opc = MI->getOpcode();
263 MachineInstr *NewMI = NULL;
270 if (MI->getOperand(1).getReg() == MI->getOperand(2).getReg()) {
271 if (Ops[0] == 0) { // move -> store
272 unsigned InReg = MI->getOperand(1).getReg();
273 bool isKill = MI->getOperand(1).isKill();
274 Opc = (Opc == Alpha::BISr) ? Alpha::STQ :
275 ((Opc == Alpha::CPYSS) ? Alpha::STS : Alpha::STT);
276 NewMI = BuildMI(MF, get(Opc)).addReg(InReg, false, false, isKill)
277 .addFrameIndex(FrameIndex)
279 } else { // load -> move
280 unsigned OutReg = MI->getOperand(0).getReg();
281 bool isDead = MI->getOperand(0).isDead();
282 Opc = (Opc == Alpha::BISr) ? Alpha::LDQ :
283 ((Opc == Alpha::CPYSS) ? Alpha::LDS : Alpha::LDT);
284 NewMI = BuildMI(MF, get(Opc)).addReg(OutReg, true, false, false, isDead)
285 .addFrameIndex(FrameIndex)
294 static unsigned AlphaRevCondCode(unsigned Opcode) {
296 case Alpha::BEQ: return Alpha::BNE;
297 case Alpha::BNE: return Alpha::BEQ;
298 case Alpha::BGE: return Alpha::BLT;
299 case Alpha::BGT: return Alpha::BLE;
300 case Alpha::BLE: return Alpha::BGT;
301 case Alpha::BLT: return Alpha::BGE;
302 case Alpha::BLBC: return Alpha::BLBS;
303 case Alpha::BLBS: return Alpha::BLBC;
304 case Alpha::FBEQ: return Alpha::FBNE;
305 case Alpha::FBNE: return Alpha::FBEQ;
306 case Alpha::FBGE: return Alpha::FBLT;
307 case Alpha::FBGT: return Alpha::FBLE;
308 case Alpha::FBLE: return Alpha::FBGT;
309 case Alpha::FBLT: return Alpha::FBGE;
311 assert(0 && "Unknown opcode");
313 return 0; // Not reached
317 bool AlphaInstrInfo::AnalyzeBranch(MachineBasicBlock &MBB,MachineBasicBlock *&TBB,
318 MachineBasicBlock *&FBB,
319 SmallVectorImpl<MachineOperand> &Cond) const {
320 // If the block has no terminators, it just falls into the block after it.
321 MachineBasicBlock::iterator I = MBB.end();
322 if (I == MBB.begin() || !isUnpredicatedTerminator(--I))
325 // Get the last instruction in the block.
326 MachineInstr *LastInst = I;
328 // If there is only one terminator instruction, process it.
329 if (I == MBB.begin() || !isUnpredicatedTerminator(--I)) {
330 if (LastInst->getOpcode() == Alpha::BR) {
331 TBB = LastInst->getOperand(0).getMBB();
333 } else if (LastInst->getOpcode() == Alpha::COND_BRANCH_I ||
334 LastInst->getOpcode() == Alpha::COND_BRANCH_F) {
335 // Block ends with fall-through condbranch.
336 TBB = LastInst->getOperand(2).getMBB();
337 Cond.push_back(LastInst->getOperand(0));
338 Cond.push_back(LastInst->getOperand(1));
341 // Otherwise, don't know what this is.
345 // Get the instruction before it if it's a terminator.
346 MachineInstr *SecondLastInst = I;
348 // If there are three terminators, we don't know what sort of block this is.
349 if (SecondLastInst && I != MBB.begin() &&
350 isUnpredicatedTerminator(--I))
353 // If the block ends with Alpha::BR and Alpha::COND_BRANCH_*, handle it.
354 if ((SecondLastInst->getOpcode() == Alpha::COND_BRANCH_I ||
355 SecondLastInst->getOpcode() == Alpha::COND_BRANCH_F) &&
356 LastInst->getOpcode() == Alpha::BR) {
357 TBB = SecondLastInst->getOperand(2).getMBB();
358 Cond.push_back(SecondLastInst->getOperand(0));
359 Cond.push_back(SecondLastInst->getOperand(1));
360 FBB = LastInst->getOperand(0).getMBB();
364 // If the block ends with two Alpha::BRs, handle it. The second one is not
365 // executed, so remove it.
366 if (SecondLastInst->getOpcode() == Alpha::BR &&
367 LastInst->getOpcode() == Alpha::BR) {
368 TBB = SecondLastInst->getOperand(0).getMBB();
370 I->eraseFromParent();
374 // Otherwise, can't handle this.
378 unsigned AlphaInstrInfo::RemoveBranch(MachineBasicBlock &MBB) const {
379 MachineBasicBlock::iterator I = MBB.end();
380 if (I == MBB.begin()) return 0;
382 if (I->getOpcode() != Alpha::BR &&
383 I->getOpcode() != Alpha::COND_BRANCH_I &&
384 I->getOpcode() != Alpha::COND_BRANCH_F)
387 // Remove the branch.
388 I->eraseFromParent();
392 if (I == MBB.begin()) return 1;
394 if (I->getOpcode() != Alpha::COND_BRANCH_I &&
395 I->getOpcode() != Alpha::COND_BRANCH_F)
398 // Remove the branch.
399 I->eraseFromParent();
403 void AlphaInstrInfo::insertNoop(MachineBasicBlock &MBB,
404 MachineBasicBlock::iterator MI) const {
405 BuildMI(MBB, MI, get(Alpha::BISr), Alpha::R31).addReg(Alpha::R31)
409 bool AlphaInstrInfo::BlockHasNoFallThrough(MachineBasicBlock &MBB) const {
410 if (MBB.empty()) return false;
412 switch (MBB.back().getOpcode()) {
413 case Alpha::RETDAG: // Return.
415 case Alpha::BR: // Uncond branch.
416 case Alpha::JMP: // Indirect branch.
418 default: return false;
421 bool AlphaInstrInfo::
422 ReverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const {
423 assert(Cond.size() == 2 && "Invalid Alpha branch opcode!");
424 Cond[0].setImm(AlphaRevCondCode(Cond[0].getImm()));