1 //===- AlphaInstrInfo.cpp - Alpha Instruction Information -------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file was developed by the LLVM research group and is distributed under
6 // the University of Illinois Open Source License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains the Alpha implementation of the TargetInstrInfo class.
12 //===----------------------------------------------------------------------===//
15 #include "AlphaInstrInfo.h"
16 #include "AlphaGenInstrInfo.inc"
17 #include "llvm/CodeGen/MachineInstrBuilder.h"
20 AlphaInstrInfo::AlphaInstrInfo()
21 : TargetInstrInfo(AlphaInsts, sizeof(AlphaInsts)/sizeof(AlphaInsts[0])),
25 bool AlphaInstrInfo::isMoveInstr(const MachineInstr& MI,
27 unsigned& destReg) const {
28 MachineOpCode oc = MI.getOpcode();
29 if (oc == Alpha::BISr ||
32 oc == Alpha::CPYSSt ||
33 oc == Alpha::CPYSTs) {
36 assert(MI.getNumOperands() >= 3 &&
37 MI.getOperand(0).isRegister() &&
38 MI.getOperand(1).isRegister() &&
39 MI.getOperand(2).isRegister() &&
40 "invalid Alpha BIS instruction!");
41 if (MI.getOperand(1).getReg() == MI.getOperand(2).getReg()) {
42 sourceReg = MI.getOperand(1).getReg();
43 destReg = MI.getOperand(0).getReg();
51 AlphaInstrInfo::isLoadFromStackSlot(MachineInstr *MI, int &FrameIndex) const {
52 switch (MI->getOpcode()) {
59 if (MI->getOperand(1).isFrameIndex()) {
60 FrameIndex = MI->getOperand(1).getFrameIndex();
61 return MI->getOperand(0).getReg();
69 AlphaInstrInfo::isStoreToStackSlot(MachineInstr *MI, int &FrameIndex) const {
70 switch (MI->getOpcode()) {
77 if (MI->getOperand(1).isFrameIndex()) {
78 FrameIndex = MI->getOperand(1).getFrameIndex();
79 return MI->getOperand(0).getReg();
86 static bool isAlphaIntCondCode(unsigned Opcode) {
102 unsigned AlphaInstrInfo::InsertBranch(MachineBasicBlock &MBB,MachineBasicBlock *TBB,
103 MachineBasicBlock *FBB,
104 const std::vector<MachineOperand> &Cond)const{
105 assert(TBB && "InsertBranch must not be told to insert a fallthrough");
106 assert((Cond.size() == 2 || Cond.size() == 0) &&
107 "Alpha branch conditions have two components!");
111 if (Cond.empty()) // Unconditional branch
112 BuildMI(&MBB, get(Alpha::BR)).addMBB(TBB);
113 else // Conditional branch
114 if (isAlphaIntCondCode(Cond[0].getImm()))
115 BuildMI(&MBB, get(Alpha::COND_BRANCH_I))
116 .addImm(Cond[0].getImm()).addReg(Cond[1].getReg()).addMBB(TBB);
118 BuildMI(&MBB, get(Alpha::COND_BRANCH_F))
119 .addImm(Cond[0].getImm()).addReg(Cond[1].getReg()).addMBB(TBB);
123 // Two-way Conditional Branch.
124 if (isAlphaIntCondCode(Cond[0].getImm()))
125 BuildMI(&MBB, get(Alpha::COND_BRANCH_I))
126 .addImm(Cond[0].getImm()).addReg(Cond[1].getReg()).addMBB(TBB);
128 BuildMI(&MBB, get(Alpha::COND_BRANCH_F))
129 .addImm(Cond[0].getImm()).addReg(Cond[1].getReg()).addMBB(TBB);
130 BuildMI(&MBB, get(Alpha::BR)).addMBB(FBB);
134 static unsigned AlphaRevCondCode(unsigned Opcode) {
136 case Alpha::BEQ: return Alpha::BNE;
137 case Alpha::BNE: return Alpha::BEQ;
138 case Alpha::BGE: return Alpha::BLT;
139 case Alpha::BGT: return Alpha::BLE;
140 case Alpha::BLE: return Alpha::BGT;
141 case Alpha::BLT: return Alpha::BGE;
142 case Alpha::BLBC: return Alpha::BLBS;
143 case Alpha::BLBS: return Alpha::BLBC;
144 case Alpha::FBEQ: return Alpha::FBNE;
145 case Alpha::FBNE: return Alpha::FBEQ;
146 case Alpha::FBGE: return Alpha::FBLT;
147 case Alpha::FBGT: return Alpha::FBLE;
148 case Alpha::FBLE: return Alpha::FBGT;
149 case Alpha::FBLT: return Alpha::FBGE;
151 assert(0 && "Unknown opcode");
156 bool AlphaInstrInfo::AnalyzeBranch(MachineBasicBlock &MBB,MachineBasicBlock *&TBB,
157 MachineBasicBlock *&FBB,
158 std::vector<MachineOperand> &Cond) const {
159 // If the block has no terminators, it just falls into the block after it.
160 MachineBasicBlock::iterator I = MBB.end();
161 if (I == MBB.begin() || !isTerminatorInstr((--I)->getOpcode()))
164 // Get the last instruction in the block.
165 MachineInstr *LastInst = I;
167 // If there is only one terminator instruction, process it.
168 if (I == MBB.begin() || !isTerminatorInstr((--I)->getOpcode())) {
169 if (LastInst->getOpcode() == Alpha::BR) {
170 TBB = LastInst->getOperand(0).getMachineBasicBlock();
172 } else if (LastInst->getOpcode() == Alpha::COND_BRANCH_I ||
173 LastInst->getOpcode() == Alpha::COND_BRANCH_F) {
174 // Block ends with fall-through condbranch.
175 TBB = LastInst->getOperand(2).getMachineBasicBlock();
176 Cond.push_back(LastInst->getOperand(0));
177 Cond.push_back(LastInst->getOperand(1));
180 // Otherwise, don't know what this is.
184 // Get the instruction before it if it's a terminator.
185 MachineInstr *SecondLastInst = I;
187 // If there are three terminators, we don't know what sort of block this is.
188 if (SecondLastInst && I != MBB.begin() &&
189 isTerminatorInstr((--I)->getOpcode()))
192 // If the block ends with Alpha::BR and Alpha::COND_BRANCH_*, handle it.
193 if ((SecondLastInst->getOpcode() == Alpha::COND_BRANCH_I ||
194 SecondLastInst->getOpcode() == Alpha::COND_BRANCH_F) &&
195 LastInst->getOpcode() == Alpha::BR) {
196 TBB = SecondLastInst->getOperand(2).getMachineBasicBlock();
197 Cond.push_back(SecondLastInst->getOperand(0));
198 Cond.push_back(SecondLastInst->getOperand(1));
199 FBB = LastInst->getOperand(0).getMachineBasicBlock();
203 // Otherwise, can't handle this.
207 unsigned AlphaInstrInfo::RemoveBranch(MachineBasicBlock &MBB) const {
208 MachineBasicBlock::iterator I = MBB.end();
209 if (I == MBB.begin()) return 0;
211 if (I->getOpcode() != Alpha::BR &&
212 I->getOpcode() != Alpha::COND_BRANCH_I &&
213 I->getOpcode() != Alpha::COND_BRANCH_F)
216 // Remove the branch.
217 I->eraseFromParent();
221 if (I == MBB.begin()) return 1;
223 if (I->getOpcode() != Alpha::COND_BRANCH_I &&
224 I->getOpcode() != Alpha::COND_BRANCH_F)
227 // Remove the branch.
228 I->eraseFromParent();
232 void AlphaInstrInfo::insertNoop(MachineBasicBlock &MBB,
233 MachineBasicBlock::iterator MI) const {
234 BuildMI(MBB, MI, get(Alpha::BISr), Alpha::R31).addReg(Alpha::R31)
238 bool AlphaInstrInfo::BlockHasNoFallThrough(MachineBasicBlock &MBB) const {
239 if (MBB.empty()) return false;
241 switch (MBB.back().getOpcode()) {
242 case Alpha::BR: // Uncond branch.
243 case Alpha::JMP: // Indirect branch.
245 default: return false;
248 bool AlphaInstrInfo::
249 ReverseBranchCondition(std::vector<MachineOperand> &Cond) const {
250 assert(Cond.size() == 2 && "Invalid Alpha branch opcode!");
251 Cond[0].setImm(AlphaRevCondCode(Cond[0].getImm()));