1 //===- AlphaInstrInfo.cpp - Alpha Instruction Information -------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains the Alpha implementation of the TargetInstrInfo class.
12 //===----------------------------------------------------------------------===//
15 #include "AlphaInstrInfo.h"
16 #include "AlphaGenInstrInfo.inc"
17 #include "llvm/ADT/STLExtras.h"
18 #include "llvm/CodeGen/MachineInstrBuilder.h"
21 AlphaInstrInfo::AlphaInstrInfo()
22 : TargetInstrInfoImpl(AlphaInsts, array_lengthof(AlphaInsts)),
26 bool AlphaInstrInfo::isMoveInstr(const MachineInstr& MI,
28 unsigned& destReg) const {
29 unsigned oc = MI.getOpcode();
30 if (oc == Alpha::BISr ||
33 oc == Alpha::CPYSSt ||
34 oc == Alpha::CPYSTs) {
37 assert(MI.getNumOperands() >= 3 &&
38 MI.getOperand(0).isReg() &&
39 MI.getOperand(1).isReg() &&
40 MI.getOperand(2).isReg() &&
41 "invalid Alpha BIS instruction!");
42 if (MI.getOperand(1).getReg() == MI.getOperand(2).getReg()) {
43 sourceReg = MI.getOperand(1).getReg();
44 destReg = MI.getOperand(0).getReg();
52 AlphaInstrInfo::isLoadFromStackSlot(const MachineInstr *MI,
53 int &FrameIndex) const {
54 switch (MI->getOpcode()) {
61 if (MI->getOperand(1).isFI()) {
62 FrameIndex = MI->getOperand(1).getIndex();
63 return MI->getOperand(0).getReg();
71 AlphaInstrInfo::isStoreToStackSlot(const MachineInstr *MI,
72 int &FrameIndex) const {
73 switch (MI->getOpcode()) {
80 if (MI->getOperand(1).isFI()) {
81 FrameIndex = MI->getOperand(1).getIndex();
82 return MI->getOperand(0).getReg();
89 static bool isAlphaIntCondCode(unsigned Opcode) {
105 unsigned AlphaInstrInfo::InsertBranch(MachineBasicBlock &MBB,
106 MachineBasicBlock *TBB,
107 MachineBasicBlock *FBB,
108 const SmallVectorImpl<MachineOperand> &Cond) const {
109 assert(TBB && "InsertBranch must not be told to insert a fallthrough");
110 assert((Cond.size() == 2 || Cond.size() == 0) &&
111 "Alpha branch conditions have two components!");
115 if (Cond.empty()) // Unconditional branch
116 BuildMI(&MBB, get(Alpha::BR)).addMBB(TBB);
117 else // Conditional branch
118 if (isAlphaIntCondCode(Cond[0].getImm()))
119 BuildMI(&MBB, get(Alpha::COND_BRANCH_I))
120 .addImm(Cond[0].getImm()).addReg(Cond[1].getReg()).addMBB(TBB);
122 BuildMI(&MBB, get(Alpha::COND_BRANCH_F))
123 .addImm(Cond[0].getImm()).addReg(Cond[1].getReg()).addMBB(TBB);
127 // Two-way Conditional Branch.
128 if (isAlphaIntCondCode(Cond[0].getImm()))
129 BuildMI(&MBB, get(Alpha::COND_BRANCH_I))
130 .addImm(Cond[0].getImm()).addReg(Cond[1].getReg()).addMBB(TBB);
132 BuildMI(&MBB, get(Alpha::COND_BRANCH_F))
133 .addImm(Cond[0].getImm()).addReg(Cond[1].getReg()).addMBB(TBB);
134 BuildMI(&MBB, get(Alpha::BR)).addMBB(FBB);
138 bool AlphaInstrInfo::copyRegToReg(MachineBasicBlock &MBB,
139 MachineBasicBlock::iterator MI,
140 unsigned DestReg, unsigned SrcReg,
141 const TargetRegisterClass *DestRC,
142 const TargetRegisterClass *SrcRC) const {
143 //cerr << "copyRegToReg " << DestReg << " <- " << SrcReg << "\n";
144 if (DestRC != SrcRC) {
145 // Not yet supported!
149 if (DestRC == Alpha::GPRCRegisterClass) {
150 BuildMI(MBB, MI, get(Alpha::BISr), DestReg).addReg(SrcReg).addReg(SrcReg);
151 } else if (DestRC == Alpha::F4RCRegisterClass) {
152 BuildMI(MBB, MI, get(Alpha::CPYSS), DestReg).addReg(SrcReg).addReg(SrcReg);
153 } else if (DestRC == Alpha::F8RCRegisterClass) {
154 BuildMI(MBB, MI, get(Alpha::CPYST), DestReg).addReg(SrcReg).addReg(SrcReg);
156 // Attempt to copy register that is not GPR or FPR
164 AlphaInstrInfo::storeRegToStackSlot(MachineBasicBlock &MBB,
165 MachineBasicBlock::iterator MI,
166 unsigned SrcReg, bool isKill, int FrameIdx,
167 const TargetRegisterClass *RC) const {
168 //cerr << "Trying to store " << getPrettyName(SrcReg) << " to "
169 // << FrameIdx << "\n";
170 //BuildMI(MBB, MI, Alpha::WTF, 0).addReg(SrcReg);
171 if (RC == Alpha::F4RCRegisterClass)
172 BuildMI(MBB, MI, get(Alpha::STS))
173 .addReg(SrcReg, false, false, isKill)
174 .addFrameIndex(FrameIdx).addReg(Alpha::F31);
175 else if (RC == Alpha::F8RCRegisterClass)
176 BuildMI(MBB, MI, get(Alpha::STT))
177 .addReg(SrcReg, false, false, isKill)
178 .addFrameIndex(FrameIdx).addReg(Alpha::F31);
179 else if (RC == Alpha::GPRCRegisterClass)
180 BuildMI(MBB, MI, get(Alpha::STQ))
181 .addReg(SrcReg, false, false, isKill)
182 .addFrameIndex(FrameIdx).addReg(Alpha::F31);
187 void AlphaInstrInfo::storeRegToAddr(MachineFunction &MF, unsigned SrcReg,
189 SmallVectorImpl<MachineOperand> &Addr,
190 const TargetRegisterClass *RC,
191 SmallVectorImpl<MachineInstr*> &NewMIs) const {
193 if (RC == Alpha::F4RCRegisterClass)
195 else if (RC == Alpha::F8RCRegisterClass)
197 else if (RC == Alpha::GPRCRegisterClass)
201 MachineInstrBuilder MIB =
202 BuildMI(MF, get(Opc)).addReg(SrcReg, false, false, isKill);
203 for (unsigned i = 0, e = Addr.size(); i != e; ++i) {
204 MachineOperand &MO = Addr[i];
206 MIB.addReg(MO.getReg(), MO.isDef(), MO.isImplicit());
208 MIB.addImm(MO.getImm());
210 NewMIs.push_back(MIB);
214 AlphaInstrInfo::loadRegFromStackSlot(MachineBasicBlock &MBB,
215 MachineBasicBlock::iterator MI,
216 unsigned DestReg, int FrameIdx,
217 const TargetRegisterClass *RC) const {
218 //cerr << "Trying to load " << getPrettyName(DestReg) << " to "
219 // << FrameIdx << "\n";
220 if (RC == Alpha::F4RCRegisterClass)
221 BuildMI(MBB, MI, get(Alpha::LDS), DestReg)
222 .addFrameIndex(FrameIdx).addReg(Alpha::F31);
223 else if (RC == Alpha::F8RCRegisterClass)
224 BuildMI(MBB, MI, get(Alpha::LDT), DestReg)
225 .addFrameIndex(FrameIdx).addReg(Alpha::F31);
226 else if (RC == Alpha::GPRCRegisterClass)
227 BuildMI(MBB, MI, get(Alpha::LDQ), DestReg)
228 .addFrameIndex(FrameIdx).addReg(Alpha::F31);
233 void AlphaInstrInfo::loadRegFromAddr(MachineFunction &MF, unsigned DestReg,
234 SmallVectorImpl<MachineOperand> &Addr,
235 const TargetRegisterClass *RC,
236 SmallVectorImpl<MachineInstr*> &NewMIs) const {
238 if (RC == Alpha::F4RCRegisterClass)
240 else if (RC == Alpha::F8RCRegisterClass)
242 else if (RC == Alpha::GPRCRegisterClass)
246 MachineInstrBuilder MIB =
247 BuildMI(MF, get(Opc), DestReg);
248 for (unsigned i = 0, e = Addr.size(); i != e; ++i) {
249 MachineOperand &MO = Addr[i];
251 MIB.addReg(MO.getReg(), MO.isDef(), MO.isImplicit());
253 MIB.addImm(MO.getImm());
255 NewMIs.push_back(MIB);
258 MachineInstr *AlphaInstrInfo::foldMemoryOperandImpl(MachineFunction &MF,
260 const SmallVectorImpl<unsigned> &Ops,
261 int FrameIndex) const {
262 if (Ops.size() != 1) return NULL;
264 // Make sure this is a reg-reg copy.
265 unsigned Opc = MI->getOpcode();
267 MachineInstr *NewMI = NULL;
274 if (MI->getOperand(1).getReg() == MI->getOperand(2).getReg()) {
275 if (Ops[0] == 0) { // move -> store
276 unsigned InReg = MI->getOperand(1).getReg();
277 bool isKill = MI->getOperand(1).isKill();
278 Opc = (Opc == Alpha::BISr) ? Alpha::STQ :
279 ((Opc == Alpha::CPYSS) ? Alpha::STS : Alpha::STT);
280 NewMI = BuildMI(MF, get(Opc)).addReg(InReg, false, false, isKill)
281 .addFrameIndex(FrameIndex)
283 } else { // load -> move
284 unsigned OutReg = MI->getOperand(0).getReg();
285 bool isDead = MI->getOperand(0).isDead();
286 Opc = (Opc == Alpha::BISr) ? Alpha::LDQ :
287 ((Opc == Alpha::CPYSS) ? Alpha::LDS : Alpha::LDT);
288 NewMI = BuildMI(MF, get(Opc)).addReg(OutReg, true, false, false, isDead)
289 .addFrameIndex(FrameIndex)
298 static unsigned AlphaRevCondCode(unsigned Opcode) {
300 case Alpha::BEQ: return Alpha::BNE;
301 case Alpha::BNE: return Alpha::BEQ;
302 case Alpha::BGE: return Alpha::BLT;
303 case Alpha::BGT: return Alpha::BLE;
304 case Alpha::BLE: return Alpha::BGT;
305 case Alpha::BLT: return Alpha::BGE;
306 case Alpha::BLBC: return Alpha::BLBS;
307 case Alpha::BLBS: return Alpha::BLBC;
308 case Alpha::FBEQ: return Alpha::FBNE;
309 case Alpha::FBNE: return Alpha::FBEQ;
310 case Alpha::FBGE: return Alpha::FBLT;
311 case Alpha::FBGT: return Alpha::FBLE;
312 case Alpha::FBLE: return Alpha::FBGT;
313 case Alpha::FBLT: return Alpha::FBGE;
315 assert(0 && "Unknown opcode");
317 return 0; // Not reached
321 bool AlphaInstrInfo::AnalyzeBranch(MachineBasicBlock &MBB,MachineBasicBlock *&TBB,
322 MachineBasicBlock *&FBB,
323 SmallVectorImpl<MachineOperand> &Cond) const {
324 // If the block has no terminators, it just falls into the block after it.
325 MachineBasicBlock::iterator I = MBB.end();
326 if (I == MBB.begin() || !isUnpredicatedTerminator(--I))
329 // Get the last instruction in the block.
330 MachineInstr *LastInst = I;
332 // If there is only one terminator instruction, process it.
333 if (I == MBB.begin() || !isUnpredicatedTerminator(--I)) {
334 if (LastInst->getOpcode() == Alpha::BR) {
335 TBB = LastInst->getOperand(0).getMBB();
337 } else if (LastInst->getOpcode() == Alpha::COND_BRANCH_I ||
338 LastInst->getOpcode() == Alpha::COND_BRANCH_F) {
339 // Block ends with fall-through condbranch.
340 TBB = LastInst->getOperand(2).getMBB();
341 Cond.push_back(LastInst->getOperand(0));
342 Cond.push_back(LastInst->getOperand(1));
345 // Otherwise, don't know what this is.
349 // Get the instruction before it if it's a terminator.
350 MachineInstr *SecondLastInst = I;
352 // If there are three terminators, we don't know what sort of block this is.
353 if (SecondLastInst && I != MBB.begin() &&
354 isUnpredicatedTerminator(--I))
357 // If the block ends with Alpha::BR and Alpha::COND_BRANCH_*, handle it.
358 if ((SecondLastInst->getOpcode() == Alpha::COND_BRANCH_I ||
359 SecondLastInst->getOpcode() == Alpha::COND_BRANCH_F) &&
360 LastInst->getOpcode() == Alpha::BR) {
361 TBB = SecondLastInst->getOperand(2).getMBB();
362 Cond.push_back(SecondLastInst->getOperand(0));
363 Cond.push_back(SecondLastInst->getOperand(1));
364 FBB = LastInst->getOperand(0).getMBB();
368 // If the block ends with two Alpha::BRs, handle it. The second one is not
369 // executed, so remove it.
370 if (SecondLastInst->getOpcode() == Alpha::BR &&
371 LastInst->getOpcode() == Alpha::BR) {
372 TBB = SecondLastInst->getOperand(0).getMBB();
374 I->eraseFromParent();
378 // Otherwise, can't handle this.
382 unsigned AlphaInstrInfo::RemoveBranch(MachineBasicBlock &MBB) const {
383 MachineBasicBlock::iterator I = MBB.end();
384 if (I == MBB.begin()) return 0;
386 if (I->getOpcode() != Alpha::BR &&
387 I->getOpcode() != Alpha::COND_BRANCH_I &&
388 I->getOpcode() != Alpha::COND_BRANCH_F)
391 // Remove the branch.
392 I->eraseFromParent();
396 if (I == MBB.begin()) return 1;
398 if (I->getOpcode() != Alpha::COND_BRANCH_I &&
399 I->getOpcode() != Alpha::COND_BRANCH_F)
402 // Remove the branch.
403 I->eraseFromParent();
407 void AlphaInstrInfo::insertNoop(MachineBasicBlock &MBB,
408 MachineBasicBlock::iterator MI) const {
409 BuildMI(MBB, MI, get(Alpha::BISr), Alpha::R31).addReg(Alpha::R31)
413 bool AlphaInstrInfo::BlockHasNoFallThrough(const MachineBasicBlock &MBB) const {
414 if (MBB.empty()) return false;
416 switch (MBB.back().getOpcode()) {
417 case Alpha::RETDAG: // Return.
419 case Alpha::BR: // Uncond branch.
420 case Alpha::JMP: // Indirect branch.
422 default: return false;
425 bool AlphaInstrInfo::
426 ReverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const {
427 assert(Cond.size() == 2 && "Invalid Alpha branch opcode!");
428 Cond[0].setImm(AlphaRevCondCode(Cond[0].getImm()));