1 //===- AlphaInstrInfo.h - Alpha Instruction Information ---------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains the Alpha implementation of the TargetInstrInfo class.
12 //===----------------------------------------------------------------------===//
14 #ifndef ALPHAINSTRUCTIONINFO_H
15 #define ALPHAINSTRUCTIONINFO_H
17 #include "llvm/Target/TargetInstrInfo.h"
18 #include "AlphaRegisterInfo.h"
22 class AlphaInstrInfo : public TargetInstrInfoImpl {
23 const AlphaRegisterInfo RI;
27 /// getRegisterInfo - TargetInstrInfo is a superset of MRegister info. As
28 /// such, whenever a client has an instance of instruction info, it should
29 /// always be able to get register info as well (through this method).
31 virtual const AlphaRegisterInfo &getRegisterInfo() const { return RI; }
33 /// Return true if the instruction is a register to register move and
34 /// leave the source and dest operands in the passed parameters.
36 virtual bool isMoveInstr(const MachineInstr &MI,
37 unsigned &SrcReg, unsigned &DstReg) const;
39 virtual unsigned isLoadFromStackSlot(MachineInstr *MI, int &FrameIndex) const;
40 virtual unsigned isStoreToStackSlot(MachineInstr *MI, int &FrameIndex) const;
42 virtual unsigned InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB,
43 MachineBasicBlock *FBB,
44 const std::vector<MachineOperand> &Cond) const;
45 virtual void copyRegToReg(MachineBasicBlock &MBB,
46 MachineBasicBlock::iterator MI,
47 unsigned DestReg, unsigned SrcReg,
48 const TargetRegisterClass *DestRC,
49 const TargetRegisterClass *SrcRC) const;
50 virtual void storeRegToStackSlot(MachineBasicBlock &MBB,
51 MachineBasicBlock::iterator MBBI,
52 unsigned SrcReg, bool isKill, int FrameIndex,
53 const TargetRegisterClass *RC) const;
55 virtual void storeRegToAddr(MachineFunction &MF, unsigned SrcReg, bool isKill,
56 SmallVectorImpl<MachineOperand> &Addr,
57 const TargetRegisterClass *RC,
58 SmallVectorImpl<MachineInstr*> &NewMIs) const;
60 virtual void loadRegFromStackSlot(MachineBasicBlock &MBB,
61 MachineBasicBlock::iterator MBBI,
62 unsigned DestReg, int FrameIndex,
63 const TargetRegisterClass *RC) const;
65 virtual void loadRegFromAddr(MachineFunction &MF, unsigned DestReg,
66 SmallVectorImpl<MachineOperand> &Addr,
67 const TargetRegisterClass *RC,
68 SmallVectorImpl<MachineInstr*> &NewMIs) const;
70 virtual MachineInstr* foldMemoryOperand(MachineFunction &MF,
72 SmallVectorImpl<unsigned> &Ops,
73 int FrameIndex) const;
75 virtual MachineInstr* foldMemoryOperand(MachineFunction &MF,
77 SmallVectorImpl<unsigned> &Ops,
78 MachineInstr* LoadMI) const {
82 bool AnalyzeBranch(MachineBasicBlock &MBB,MachineBasicBlock *&TBB,
83 MachineBasicBlock *&FBB,
84 std::vector<MachineOperand> &Cond) const;
85 unsigned RemoveBranch(MachineBasicBlock &MBB) const;
86 void insertNoop(MachineBasicBlock &MBB,
87 MachineBasicBlock::iterator MI) const;
88 bool BlockHasNoFallThrough(MachineBasicBlock &MBB) const;
89 bool ReverseBranchCondition(std::vector<MachineOperand> &Cond) const;