1 //===- AlphaInstrInfo.h - Alpha Instruction Information ---------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains the Alpha implementation of the TargetInstrInfo class.
12 //===----------------------------------------------------------------------===//
14 #ifndef ALPHAINSTRUCTIONINFO_H
15 #define ALPHAINSTRUCTIONINFO_H
17 #include "llvm/Target/TargetInstrInfo.h"
18 #include "AlphaRegisterInfo.h"
22 class AlphaInstrInfo : public TargetInstrInfoImpl {
23 const AlphaRegisterInfo RI;
27 /// getRegisterInfo - TargetInstrInfo is a superset of MRegister info. As
28 /// such, whenever a client has an instance of instruction info, it should
29 /// always be able to get register info as well (through this method).
31 virtual const AlphaRegisterInfo &getRegisterInfo() const { return RI; }
33 /// Return true if the instruction is a register to register move and return
34 /// the source and dest operands and their sub-register indices by reference.
35 virtual bool isMoveInstr(const MachineInstr &MI,
36 unsigned &SrcReg, unsigned &DstReg,
37 unsigned &SrcSubIdx, unsigned &DstSubIdx) const;
39 virtual unsigned isLoadFromStackSlot(const MachineInstr *MI,
40 int &FrameIndex) const;
41 virtual unsigned isStoreToStackSlot(const MachineInstr *MI,
42 int &FrameIndex) const;
44 virtual unsigned InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB,
45 MachineBasicBlock *FBB,
46 const SmallVectorImpl<MachineOperand> &Cond) const;
47 virtual bool copyRegToReg(MachineBasicBlock &MBB,
48 MachineBasicBlock::iterator MI,
49 unsigned DestReg, unsigned SrcReg,
50 const TargetRegisterClass *DestRC,
51 const TargetRegisterClass *SrcRC) const;
52 virtual void storeRegToStackSlot(MachineBasicBlock &MBB,
53 MachineBasicBlock::iterator MBBI,
54 unsigned SrcReg, bool isKill, int FrameIndex,
55 const TargetRegisterClass *RC) const;
57 virtual void loadRegFromStackSlot(MachineBasicBlock &MBB,
58 MachineBasicBlock::iterator MBBI,
59 unsigned DestReg, int FrameIndex,
60 const TargetRegisterClass *RC) const;
62 virtual MachineInstr* foldMemoryOperandImpl(MachineFunction &MF,
64 const SmallVectorImpl<unsigned> &Ops,
65 int FrameIndex) const;
67 virtual MachineInstr* foldMemoryOperandImpl(MachineFunction &MF,
69 const SmallVectorImpl<unsigned> &Ops,
70 MachineInstr* LoadMI) const {
74 bool AnalyzeBranch(MachineBasicBlock &MBB,MachineBasicBlock *&TBB,
75 MachineBasicBlock *&FBB,
76 SmallVectorImpl<MachineOperand> &Cond,
77 bool AllowModify) const;
78 unsigned RemoveBranch(MachineBasicBlock &MBB) const;
79 void insertNoop(MachineBasicBlock &MBB,
80 MachineBasicBlock::iterator MI) const;
81 bool BlockHasNoFallThrough(const MachineBasicBlock &MBB) const;
82 bool ReverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const;
84 /// getGlobalBaseReg - Return a virtual register initialized with the
85 /// the global base register value. Output instructions required to
86 /// initialize the register in the function entry block, if necessary.
88 unsigned getGlobalBaseReg(MachineFunction *MF) const;
90 /// getGlobalRetAddr - Return a virtual register initialized with the
91 /// the global return address register value. Output instructions required to
92 /// initialize the register in the function entry block, if necessary.
94 unsigned getGlobalRetAddr(MachineFunction *MF) const;