lib/Target/Alpha/AlphaInstrInfo.h

   1 //===- AlphaInstrInfo.h - Alpha Instruction Information ---------*- C++ -*-===//
   2 //
   3 //                     The LLVM Compiler Infrastructure
   4 //
   5 // This file is distributed under the University of Illinois Open Source
   6 // License. See LICENSE.TXT for details.
   7 //
   8 //===----------------------------------------------------------------------===//
   9 //
  10 // This file contains the Alpha implementation of the TargetInstrInfo class.
  11 //
  12 //===----------------------------------------------------------------------===//
  13
  14 #ifndef ALPHAINSTRUCTIONINFO_H
  15 #define ALPHAINSTRUCTIONINFO_H
  16
  17 #include "llvm/Target/TargetInstrInfo.h"
  18 #include "AlphaRegisterInfo.h"
  19
  20 namespace llvm {
  21
  22 class AlphaInstrInfo : public TargetInstrInfoImpl {
  23   const AlphaRegisterInfo RI;
  24 public:
  25   AlphaInstrInfo();
  26
  27   /// getRegisterInfo - TargetInstrInfo is a superset of MRegister info.  As
  28   /// such, whenever a client has an instance of instruction info, it should
  29   /// always be able to get register info as well (through this method).
  30   ///
  31   virtual const AlphaRegisterInfo &getRegisterInfo() const { return RI; }
  32
  33   virtual unsigned isLoadFromStackSlot(const MachineInstr *MI,
  34                                        int &FrameIndex) const;
  35   virtual unsigned isStoreToStackSlot(const MachineInstr *MI,
  36                                       int &FrameIndex) const;
  37
  38   virtual unsigned InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB,
  39                                 MachineBasicBlock *FBB,
  40                                 const SmallVectorImpl<MachineOperand> &Cond,
  41                                 DebugLoc DL) const;
  42   virtual void copyPhysReg(MachineBasicBlock &MBB,
  43                            MachineBasicBlock::iterator MI, DebugLoc DL,
  44                            unsigned DestReg, unsigned SrcReg,
  45                            bool KillSrc) const;
  46   virtual void storeRegToStackSlot(MachineBasicBlock &MBB,
  47                                    MachineBasicBlock::iterator MBBI,
  48                                    unsigned SrcReg, bool isKill, int FrameIndex,
  49                                    const TargetRegisterClass *RC,
  50                                    const TargetRegisterInfo *TRI) const;
  51
  52   virtual void loadRegFromStackSlot(MachineBasicBlock &MBB,
  53                                     MachineBasicBlock::iterator MBBI,
  54                                     unsigned DestReg, int FrameIndex,
  55                                     const TargetRegisterClass *RC,
  56                                     const TargetRegisterInfo *TRI) const;
  57
  58   bool AnalyzeBranch(MachineBasicBlock &MBB,MachineBasicBlock *&TBB,
  59                      MachineBasicBlock *&FBB,
  60                      SmallVectorImpl<MachineOperand> &Cond,
  61                      bool AllowModify) const;
  62   unsigned RemoveBranch(MachineBasicBlock &MBB) const;
  63   void insertNoop(MachineBasicBlock &MBB,
  64                   MachineBasicBlock::iterator MI) const;
  65   bool ReverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const;
  66
  67   /// getGlobalBaseReg - Return a virtual register initialized with the
  68   /// the global base register value. Output instructions required to
  69   /// initialize the register in the function entry block, if necessary.
  70   ///
  71   unsigned getGlobalBaseReg(MachineFunction *MF) const;
  72
  73   /// getGlobalRetAddr - Return a virtual register initialized with the
  74   /// the global return address register value. Output instructions required to
  75   /// initialize the register in the function entry block, if necessary.
  76   ///
  77   unsigned getGlobalRetAddr(MachineFunction *MF) const;
  78 };
  79
  80 }
  81
  82 #endif